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User's Manual
V850/SB1 , V850/SB2
32-Bit Single-Chip Microcontroller Hardware
PD703031A PD703031AY PD703032A PD703032AY PD703033A PD703033AY PD70F3032A PD70F3032AY PD70F3033A PD70F3033AY PD703030B PD703030BY PD703031B PD703031BY PD703032B PD703032BY PD703033B PD703033BY PD70F3030B PD70F3030BY PD70F3032B PD70F3032BY PD70F3033B PD70F3033BY
TM
TM
PD703034A PD703034AY PD703035A PD703035AY PD703037A PD703037AY PD70F3035A PD70F3035AY PD70F3037A PD70F3037AY
PD703034B PD703034BY PD703035B PD703035BY PD703036H PD703036HY PD703037H PD703037HY PD70F3035B PD70F3035BY PD70F3036H PD70F3036HY PD70F3037H PD70F3037HY
Document No. U13850EJ6V0UD00 (6th edition) Date Published February 2003 N CP(K) 1999, 2000, 2003 Printed in Japan
[MEMO]
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User's Manual U13850EJ6V0UD
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
V850 Series, V850/SA1, V850/SB1, V850/SB2, IEBus, and Inter Equipment Bus are trademarks of NEC Electronics Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
User's Manual U13850EJ6V0UD
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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User's Manual U13850EJ6V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
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NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Europe) GmbH
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NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
User's Manual U13850EJ6V0UD
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Major Revisions in This Edition (1/3)
Page Throughout Description * Addition of the following products. PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY * Deletion of the following products. PD703030A, 703030AY, 703036A, 703036AY Addition of description on minimum instruction execution time in 1.5.1 Addition of description on instruction set in 1.5.1 Addition of description in Table 2-1 Pin I/O Buffer Power Supplies Modification of description and addition of Notes in Table 2-3 Operating Mode Addition of description in 2.3 (9) (b) (i) LBEN Modification of P23 I/O circuit type and description on P33 in 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Addition of description on minimum instruction execution time in 3.1 Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW) Addition of 3.4.5 (2) (a) V850/SB1 (PD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) Modification of Note and addition of registers in 3.4.8 Peripheral I/O registers Addition of description in 3.4.9 Specific registers Modification of [Description example] in 3.4.9 Specific registers Modification of Caution 2 in 3.4.9 Specific registers Addition of Remarks in 3.4.9 (2) (b) Reset conditions (PRERR = 1) Addition of Note and Caution in 4.2.2 (1) System control register (SYC) Addition of Remark in 5.3.3 Priorities of maskable interrupts Addition of Caution 2 in 5.3.4 Interrupt control register (xxICn) Addition of Caution in 5.3.5 In-service priority register (ISPR) Addition of Remark in 5.3.6 ID flag Addition of Remark in 5.6.2 (2) To generate exception in service program Addition of 5.8.1 Interrupt request valid timing after EI instruction Addition of 5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer Addition of description in Cautions in 6.3.1 (1) Processor clock control register (PCC) Modification of description in 6.3.1 (1) (b) Example of subclock operation main clock operation setup Modification of description in 6.3.1 (2) Power save control register (PSC) Addition and deletion of description in Table 6-1 Operating Statuses in HALT Mode Modification of description in Table 6-2 Operating Statuses in IDLE Mode Addition of description in 6.4.4 (1) Settings and operating states Modification of description in Table 6-3 Operating Statuses in Software STOP Mode Operating States of Pins in Each
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User's Manual U13850EJ6V0UD
Major Revisions in This Edition (2/3)
Pages p. 197 p. 198 p. 206 p. 207 p. 213 p. 214 p. 214 p. 215 p. 217 p. 219 p. 221 Description Addition of 6.6 (1) While an instruction is being executed on internal ROM Addition of 6.6 (2) While an instruction is being executed on external ROM Addition of description in Caution in 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Addition of description in Caution in 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1) Modification of description in Figure 7-5 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Addition of Figure 7-6 Configuration of PPG Output Addition of Figure 7-7 PPG Output Operation Timing Modification of description in Figure 7-8 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-11 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-14 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-17 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) Modification of description in Figure 7-18 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Caution in 7.2.6 (2) One-shot pulse output with external trigger Modification of description in 7.2.7 (6) (a) One-shot pulse output by software Modification of description in 7.2.7 (6) (b) One-shot pulse output with external trigger Addition of 7.3.1 Outline Change of Figure 7-32 Timing of Interval Timer Operation (3/3) Addition of description to Remarks in Figure 7-34 Square Wave Output Operation Timing Addition of description to Remarks in Figure 7-35 Timing of PWM Output Addition of registers and Caution in Figure 8-1 Block Diagram of Watch Timer Addition of registers and Note in Table 8-2 Configuration of Watch Timer Addition of description and Caution in 8.3 Watch Timer Control Register Addition of 8.3 (2) Watch timer high-speed clock selection register (WTNHC) Addition of description in 8.3 (3) Watch timer clock selection register (WTNCS) Addition of Caution in 9.3 (2) Watchdog timer clock selection register (WDCS) Addition of description in 10.2 (2) 3-wire serial I/O mode (fixed to MSB first) Modification of Caution in 10.3.2 (1) IIC control registers 0, 1 (IICC0, IICC1) Addition of Caution in 10.3.2 (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1) Addition of 10.4 I2C Bus (B and H Versions) Addition of description to Cautions in 10.5.2 (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) Addition of description to Cautions in 10.5.2 (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) Addition of description to Cautions in Figure 10-45 ASIMn Setting (Operation Stop Mode) Addition of description to Cautions in Figure 10-46 ASIMn Setting (Asynchronous Serial Interface Mode) Addition of description to Cautions in Figure 10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode)
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User's Manual U13850EJ6V0UD
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Major Revisions in This Edition (3/3)
Pages p. 437 p. 447 p. 452 p. 455 p. 460 p. 462 p. 463 p. 466 p. 468 p. 471 p. 473 p. 474 p. 501 p. 504 p. 511, 512 p. 515 p. 517 p. 517 p. 524 p. 526 Description Addition of Caution in 11.3 (2) Analog input channel specification register (ADS) Addition of 11.7 How to Read A/D Converter Characteristics Table Addition of 12.3 Configuration Addition of 12.4 (2) (a) V850/SB1 (PD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) Addition of Caution in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) Addition of 12.5 Operation Addition of 12.6 Cautions Addition of 13.2 Features Addition of 13.3 (2) Output latch Addition of description in 13.5 Usage Addition of 13.7 (3) Addition of description in Table 14-1 Pin I/O Buffer Power Supplies Addition of Caution in 14.2.8 (1) Function of P9 pins Addition of Caution in 14.2.9 (1) Function of P10 pins Addition of description in Table 14-12 Setting When Port Pin is Used as Alternate Function Addition of 14.4 Port Function Operation Addition of description in 16.1 Outline Addition of description in Figure 16-1 Regulator Addition of 18.1.1 (2) V850/SB1 (PD70F3030B, 70F3030BY), V850/SB2 (PD70F3036H, 70F3036HY) Addition of Figure 18-1 100GC-8EU) Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-
p. 527
Addition of Table 18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC8EU) Addition of Figure 18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF3BA) Addition of Table 18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF3BA) Modification of description in Table 19-5 Acknowledge Signal Output Condition of Control Field Addition of register to Table 19-7 Internal Registers of IEBus Controller Addition of Remark in 19.3.2 (13) IEBus clock selection register (IECLK) Addition of 19.3.2 (14) IEBus high-speed clock selection register (IEHCLK) Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 21 PACKAGE DRAWINGS Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN Modification of APPENDIX D INDEX Addition of APPENDIX E REVISION HISTORY
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The mark
shows major revised points.
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User's Manual U13850EJ6V0UD
INTRODUCTION
Readers
This manual is intended for users who wish to understand the functions of the V850/SB1 and V850/SB2 and design application systems using the V850/SB1 or V850/SB2.
Purpose
This manual is intended to give users to an understanding of the hardware functions described in the Organization below.
Organization The V850/SB1, V850/SB2 User's Manual is divided into two parts: hardware (this manual) and architecture (V850 Series Hardware
* * * * * *
TM
Architecture User's Manual). Architecture
* * * * *
Pin function CPU function On-chip peripheral function Flash memory programming IEBus controller (V850/SB2 only) Electrical specifications
Data type Register set Instruction format and instruction set Interrupt and exception Pipeline operation
How to Read This Manual
It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.
To find out the details of a register whose name is known: Refer to APPENDIX B REGISTER INDEX. To find out the details of a function, etc., whose name is known: Refer to APPENDIX D INDEX. To understand the details of a instruction function: Refer to V850 Series Architecture User's Manual available separately. To know the electrical specifications of the V850/SB1 and V850/SB2: Refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS. How to read register formats: Names of bits whose numbers are enclosed in a square are defined in the device file under reserved words. To understand the overall functions of the V850/SB1 and V850/SB2: Read this manual in accordance with the CONTENTS.
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Conventions
Data significance: Higher digits on the left and lower digits on the right Active low: xxx (overscore over pin or signal name) Memory map address: Higher addresses at the top and lower addresses at the bottom Note: Footnote for items marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Number representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefixes indicating power of 2 (address space, memory capacity): K (kilo): 2 ... 1024 M (mega): 2 ... 1024 G (giga): 2 ... 1024
30 3 20 2 10
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User's Manual U13850EJ6V0UD
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Related documents for V850/SB1 and V850/SB2
Document Name V850 Series Architecture User's Manual V850/SB1, V850/SB2 Hardware User's Manual Document No. U10243E This manual
Related documents for development tool (user's manual)
Document Name CA850 Ver. 2.40 or Later C Compiler Package Operation C Language Project Manager Assembly Language ID850 Ver. 2.40 Integrated Debugger SM850 Ver. 2.40 System Simulator SM850 Ver. 2.00 or Later System Simulator RX850 Ver. 3.13 or Later Real-time OS Operation (WindowsTM Based) Operation (Windows Based) External Part User Open Interface Specifications Basic Installation Technical RX850 Pro Ver. 3.13 Real-time OS Basic Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger AZ850 Ver. 3.0 System Performance Analyzer PG-FP3 Flash Memory Programmer PG-FP4 Flash Memory Programmer Document No. U15024E U15025E U15026E U15027E U15181E U15182E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E
User's Manual U13850EJ6V0UD
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CONTENTS
CHAPTER 1 1.1 1.2
INTRODUCTION.................................................................................................................29
General.......................................................................................................................................29 V850/SB1 (A Versions) .............................................................................................................33
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 Features (V850/SB1 (A versions)) ..............................................................................................33 Application fields (V850/SB1 (A versions)) .................................................................................34 Ordering information (V850/SB1 (A versions))............................................................................35 Pin configuration (top view) (V850/SB1 (A versions)) .................................................................36 Function blocks (V850/SB1 (A versions)) ...................................................................................39 Features (V850/SB1 (B versions)) ..............................................................................................43 Application fields (V850/SB1 (B versions)) .................................................................................44 Ordering information (V850/SB1 (B versions))............................................................................45 Pin configuration (top view) (V850/SB1 (B versions)) .................................................................46 Function blocks (V850/SB1 (B versions)) ...................................................................................49 Features (V850/SB2 (A versions)) ..............................................................................................53 Application fields (V850/SB2 (A versions)) .................................................................................54 Ordering information (V850/SB2 (A versions))............................................................................55 Pin configuration (top view) (V850/SB2 (A versions)) .................................................................56 Function blocks (V850/SB2 (A versions)) ...................................................................................59 Features (V850/SB2 (B and H versions))....................................................................................63 Application fields (V850/SB2 (B and H versions)) .......................................................................64 Ordering information (V850/SB2 (B and H versions)) .................................................................65 Pin configuration (top view) (V850/SB2 (B and H versions)).......................................................66 Function blocks (V850/SB2 (B and H versions)) .........................................................................69
1.3
V850/SB1 (B Versions) .............................................................................................................43
1.3.1 1.3.2 1.3.3 1.3.4 1.3.5
1.4
V850/SB2 (A Versions) .............................................................................................................53
1.4.1 1.4.2 1.4.3 1.4.4 1.4.5
1.5
V850/SB2 (B and H Versions) ..................................................................................................63
1.5.1 1.5.2 1.5.3 1.5.4 1.5.5
CHAPTER 2 2.1 2.2 2.3 2.4 2.5
PIN FUNCTIONS ...............................................................................................................73
List of Pin Functions ................................................................................................................73 Pin States...................................................................................................................................80 Description of Pin Functions...................................................................................................81 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins...........92 Pin I/O Circuits ..........................................................................................................................94 CPU FUNCTIONS..............................................................................................................96
CHAPTER 3 3.1 3.2
Features .....................................................................................................................................96 CPU Register Set ......................................................................................................................97
3.2.1 3.2.2 Program register set....................................................................................................................98 System register set .....................................................................................................................99
3.3 3.4
Operation Modes ....................................................................................................................102 Address Space ........................................................................................................................103
3.4.1 CPU address space ..................................................................................................................103
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3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9
Image ........................................................................................................................................ 104 Wrap-around of CPU address space ........................................................................................ 105 Memory map ............................................................................................................................. 106 Area .......................................................................................................................................... 107 External expansion mode ......................................................................................................... 114 Recommended use of address space ...................................................................................... 117 Peripheral I/O registers ............................................................................................................. 119 Specific registers....................................................................................................................... 126
CHAPTER 4 4.1 4.2
BUS CONTROL FUNCTION ..........................................................................................128
Features...................................................................................................................................128 Bus Control Pins and Control Register................................................................................128
4.2.1 4.2.2 Bus control pins ........................................................................................................................ 128 Control register ......................................................................................................................... 129 Number of access clocks .......................................................................................................... 129 Bus width .................................................................................................................................. 130
4.3
Bus Access .............................................................................................................................129
4.3.1 4.3.2
4.4 4.5
Memory Block Function.........................................................................................................131 Wait Function..........................................................................................................................132
4.5.1 4.5.2 4.5.3 Programmable wait function...................................................................................................... 132 External wait function................................................................................................................ 133 Relationship between programmable wait and external wait .................................................... 133
4.6 4.7
Idle State Insertion Function .................................................................................................134 Bus Hold Function..................................................................................................................135
4.7.1 4.7.2 4.7.3 Outline of function ..................................................................................................................... 135 Bus hold procedure................................................................................................................... 136 Operation in power save mode ................................................................................................. 136
4.8 Bus Timing ..............................................................................................................................137 4.9 Bus Priority .............................................................................................................................144 4.10 Memory Boundary Operation Conditions ............................................................................145
4.10.1 4.10.2 Program space.......................................................................................................................... 145 Data space................................................................................................................................ 145
CHAPTER 5 5.1 5.2
INTERRUPT/EXCEPTION PROCESSING FUNCTION .................................................146
Outline .....................................................................................................................................146
5.1.1 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Features.................................................................................................................................... 146 Operation .................................................................................................................................. 150 Restore ..................................................................................................................................... 152 NP flag ...................................................................................................................................... 153 Noise eliminator of NMI pin ....................................................................................................... 153 Edge detection function of NMI pin ........................................................................................... 154 Operation .................................................................................................................................. 155 Restore ..................................................................................................................................... 157 Priorities of maskable interrupts................................................................................................ 158
Non-Maskable Interrupt .........................................................................................................149
5.3
Maskable Interrupts................................................................................................................155
5.3.1 5.3.2 5.3.3
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5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9
Interrupt control register (xxICn) ...............................................................................................162 In-service priority register (ISPR) ..............................................................................................165 ID flag........................................................................................................................................165 Watchdog timer mode register (WDTM)....................................................................................166 Noise elimination.......................................................................................................................166 Edge detection function.............................................................................................................168 Operation ..................................................................................................................................169 Restore......................................................................................................................................170 EP flag.......................................................................................................................................171 Illegal opcode definition.............................................................................................................171 Operation ..................................................................................................................................171 Restore......................................................................................................................................173 Priorities of interrupts and exceptions .......................................................................................174 Multiple interrupt servicing ........................................................................................................174
5.4
Software Exceptions ..............................................................................................................169
5.4.1 5.4.2 5.4.3
5.5
Exception Trap ........................................................................................................................171
5.5.1 5.5.2 5.5.3
5.6
Priority Control........................................................................................................................174
5.6.1 5.6.2
5.7 5.8
Interrupt Latency Time ...........................................................................................................177 Periods in Which Interrupt Is Not Acknowledged ...............................................................177
5.8.1 Interrupt request valid timing after EI instruction.......................................................................178
5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer..............179 5.10 Key Interrupt Function ...........................................................................................................180 CHAPTER 6 6.1 6.2 6.3 6.4 CLOCK GENERATION FUNCTION...............................................................................182
Outline......................................................................................................................................182 Configuration ..........................................................................................................................183 Clock Output Function ...........................................................................................................183
6.3.1 6.4.1 6.4.2 6.4.3 6.4.4 Control registers ........................................................................................................................184 Outline.......................................................................................................................................188 HALT mode ...............................................................................................................................189 IDLE mode ................................................................................................................................192 Software STOP mode ...............................................................................................................194
Power Save Functions ...........................................................................................................188
6.5 6.6
Oscillation Stabilization Time................................................................................................196 Notes on Power Save Function .............................................................................................197 TIMER/COUNTER FUNCTION........................................................................................200
CHAPTER 7 7.1
16-Bit Timer (TM0, TM1) .........................................................................................................200
7.1.1 7.1.2 7.1.3 7.1.4 Outline.......................................................................................................................................200 Function ....................................................................................................................................200 Configuration.............................................................................................................................202 Timer 0, 1 control registers .......................................................................................................205 Operation as interval timer (16 bits) ..........................................................................................211 PPG output operation................................................................................................................213 Pulse width measurement .........................................................................................................215
7.2
16-Bit Timer Operation ...........................................................................................................211
7.2.1 7.2.2 7.2.3
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7.2.4 7.2.5 7.2.6 7.2.7
Operation as external event counter......................................................................................... 222 Operation to output square wave.............................................................................................. 223 Operation to output one-shot pulse........................................................................................... 225 Cautions.................................................................................................................................... 230 Outline....................................................................................................................................... 234 Functions .................................................................................................................................. 234 Configuration............................................................................................................................. 235 Timer n control register ............................................................................................................. 236 Operation as interval timer (8-bit operation) ............................................................................. 242 Operation as external event counter......................................................................................... 245 Operation as square wave output (8-bit resolution) .................................................................. 246 Operation as 8-bit PWM output................................................................................................. 247 Operation as interval timer (16 bits).......................................................................................... 250 Cautions.................................................................................................................................... 252
7.3
8-Bit Timer (TM2 to TM7)........................................................................................................234
7.3.1 7.3.2 7.3.3 7.3.4
7.4
8-Bit Timer Operation.............................................................................................................242
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6
CHAPTER 8 8.1 8.2 8.3 8.4
WATCH TIMER................................................................................................................253
Function ..................................................................................................................................253 Configuration ..........................................................................................................................254 Watch Timer Control Registers.............................................................................................255 Operation.................................................................................................................................258
8.4.1 8.4.2 8.4.3 Operation as watch timer .......................................................................................................... 258 Operation as interval timer........................................................................................................ 258 Cautions.................................................................................................................................... 259
CHAPTER 9 9.1 9.2 9.3 9.4
WATCHDOG TIMER .......................................................................................................260
Functions ................................................................................................................................260 Configuration ..........................................................................................................................262 Watchdog Timer Control Register ........................................................................................262 Operation.................................................................................................................................265
9.4.1 9.4.2 Operation as watchdog timer .................................................................................................... 265 Operation as interval timer........................................................................................................ 266
9.5
Standby Function Control Register......................................................................................267 SERIAL INTERFACE FUNCTION................................................................................268
CHAPTER 10
10.1 Overview..................................................................................................................................268 10.2 3-Wire Serial I/O (CSI0 to CSI3) .............................................................................................268
10.2.1 10.2.2 10.2.3
2
Configuration............................................................................................................................. 269 CSIn control registers ............................................................................................................... 270 Operations ................................................................................................................................ 272 Configuration............................................................................................................................. 278 I C control registers................................................................................................................... 280 I C bus mode functions ............................................................................................................. 291
2 2
10.3 I C Bus (A Versions) ...............................................................................................................275
10.3.1 10.3.2 10.3.3
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10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9
I C bus definitions and control methods ....................................................................................292 I C interrupt requests (INTIICn) .................................................................................................299 Interrupt request (INTIICn) generation timing and wait control .................................................317 Address match detection method..............................................................................................318 Error detection...........................................................................................................................318 Extension code..........................................................................................................................318
2
2
10.3.10 Arbitration..................................................................................................................................319 10.3.11 Wakeup function .......................................................................................................................320 10.3.12 Communication reservation.......................................................................................................321 10.3.13 Cautions ....................................................................................................................................324 10.3.14 Communication operations........................................................................................................325 10.3.15 Timing of data communication ..................................................................................................327
10.4 I C Bus (B and H Versions) ....................................................................................................334
10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 Configuration.............................................................................................................................337 I C control register.....................................................................................................................339 I C bus mode functions .............................................................................................................352 I C bus definitions and control methods ....................................................................................353 I C interrupt requests (INTIICn) .................................................................................................360 Interrupt request (INTIICn) generation timing and wait control .................................................378 Address match detection method..............................................................................................379 Error detection...........................................................................................................................379 Extension code..........................................................................................................................379
2 2 2 2
2
10.4.10 Arbitration..................................................................................................................................380 10.4.11 Wakeup function .......................................................................................................................382 10.4.12 Communication reservation.......................................................................................................383 10.4.13 Cautions ....................................................................................................................................388 10.4.14 Communication operations........................................................................................................389 10.4.15 Timing of data communication ..................................................................................................392
10.5 Asynchronous Serial Interface (UART0, UART1) ................................................................399
10.5.1 10.5.2 10.5.3 10.5.4 10.6.1 10.6.2 10.6.3 Configuration.............................................................................................................................399 UARTn control registers ............................................................................................................401 Operations.................................................................................................................................406 Standby function .......................................................................................................................418 Configuration.............................................................................................................................419 CSI4 control registers................................................................................................................422 Operations.................................................................................................................................426
10.6 3-Wire Variable-Length Serial I/O (CSI4)...............................................................................419
CHAPTER 11 11.1 11.2 11.3 11.4
A/D CONVERTER..........................................................................................................431
Function...................................................................................................................................431 Configuration ..........................................................................................................................433 Control Registers....................................................................................................................435 Operation .................................................................................................................................438
11.4.1 11.4.2 11.4.3 Basic operation .........................................................................................................................438 Input voltage and conversion result ..........................................................................................440 A/D converter operation mode ..................................................................................................441
11.5 Low Power Consumption Mode ............................................................................................443 16
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11.6 Cautions ..................................................................................................................................443 11.7 How to Read A/D Converter Characteristics Table .............................................................447 CHAPTER 12 12.1 12.2 12.3 12.4 12.5 12.6 DMA FUNCTIONS .........................................................................................................451
Functions ................................................................................................................................451 Transfer Completion Interrupt Request ...............................................................................451 Configuration ..........................................................................................................................452 Control Registers ...................................................................................................................453 Operation.................................................................................................................................462 Cautions ..................................................................................................................................463 REAL-TIME OUTPUT FUNCTION (RTO) ...................................................................466
CHAPTER 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7
Function ..................................................................................................................................466 Features...................................................................................................................................466 Configuration ..........................................................................................................................467 RTO Control Registers...........................................................................................................469 Usage .......................................................................................................................................471 Operation.................................................................................................................................472 Cautions ..................................................................................................................................473 PORT FUNCTION..........................................................................................................474
CHAPTER 14
14.1 Port Configuration..................................................................................................................474 14.2 Port Pin Function....................................................................................................................474
14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 14.2.7 14.2.8 14.2.9 Port 0 ........................................................................................................................................ 474 Port 1 ........................................................................................................................................ 479 Port 2 ........................................................................................................................................ 483 Port 3 ........................................................................................................................................ 488 Ports 4 and 5............................................................................................................................. 492 Port 6 ........................................................................................................................................ 495 Ports 7 and 8............................................................................................................................. 498 Port 9 ........................................................................................................................................ 500 Port 10 ...................................................................................................................................... 503
14.2.10 Port 11 ..................................................................................................................................... 507
14.3 Setting When Port Pin Is Used as Alternate Function ........................................................511 14.4 Port Function Operation ........................................................................................................515
14.4.1 14.4.2 Write operation to I/O port......................................................................................................... 515 Read operation from I/O port .................................................................................................... 515
CHAPTER 15
RESET FUNCTION........................................................................................................516
15.1 General ....................................................................................................................................516 15.2 Pin Operations ........................................................................................................................516 CHAPTER 16 REGULATOR .................................................................................................................517
16.1 Outline .....................................................................................................................................517
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16.2 Operation .................................................................................................................................517 CHAPTER 17 ROM CORRECTION FUNCTION .................................................................................518
17.1 General.....................................................................................................................................518 17.2 ROM Correction Peripheral I/O Registers ............................................................................519 CHAPTER 18 FLASH MEMORY ..........................................................................................................523
18.1 Features ...................................................................................................................................523
18.1.1 18.1.2 Erase unit ..................................................................................................................................524 Write/read time ..........................................................................................................................524
18.2 18.3 18.4 18.5
Writing with Flash Programmer ............................................................................................525 Programming Environment ...................................................................................................530 Communication Mode ............................................................................................................530 Pin Connection .......................................................................................................................533
18.5.1 18.5.2 18.5.3 18.5.4 18.5.5 18.5.6 18.6.1 18.6.2 18.6.3 18.6.4 18.6.5 VPP pin .......................................................................................................................................533 Serial interface pin ....................................................................................................................533 RESET pin.................................................................................................................................536 Port pins (including NMI) ...........................................................................................................536 Other signal pins .......................................................................................................................536 Power supply.............................................................................................................................536 Flash memory control................................................................................................................537 Flash memory programming mode ...........................................................................................538 Selection of communication mode ............................................................................................539 Communication command.........................................................................................................539 Resources used ........................................................................................................................540
18.6 Programming Method.............................................................................................................537
CHAPTER 19
IEBus CONTROLLER (V850/SB2) ..............................................................................541
19.1 IEBus Controller Function .....................................................................................................541
19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 19.1.6 19.1.7 19.1.8 Communication protocol of IEBus .............................................................................................541 Determination of bus mastership (arbitration) ...........................................................................542 Communication mode ...............................................................................................................542 Communication address............................................................................................................543 Broadcasting communication ....................................................................................................543 Transfer format of IEBus ...........................................................................................................544 Transfer data.............................................................................................................................554 Bit format ...................................................................................................................................557
19.2 IEBus Controller Configuration.............................................................................................558 19.3 Internal Registers of IEBus Controller..................................................................................560
19.3.1 19.3.2 19.4.1 19.4.2 19.4.3 Internal register list....................................................................................................................560 Internal registers .......................................................................................................................561 Interrupt control block................................................................................................................584 Interrupt source list....................................................................................................................585 Communication error source processing list .............................................................................586
19.4 Interrupt Operations of IEBus Controller .............................................................................584
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19.5 Interrupt Generation Timing and Main CPU Processing ....................................................588
19.5.1 19.5.2 19.5.3 19.5.4 19.5.5 Master transmission.................................................................................................................. 588 Master reception ....................................................................................................................... 590 Slave transmission.................................................................................................................... 592 Slave reception ......................................................................................................................... 594 Interval of occurrence of interrupt for IEBus control.................................................................. 596
CHAPTER 20
ELECTRICAL SPECIFICATIONS .................................................................................600
CHAPTER 21
PACKAGE DRAWINGS ................................................................................................635
CHAPTER 22
RECOMMENDED SOLDERING CONDITIONS ...........................................................637
APPENDIX A
NOTES ON TARGET SYSTEM DESIGN ...................................................................642
APPENDIX B
REGISTER INDEX .........................................................................................................644
APPENDIX C
INSTRUCTION SET LIST .............................................................................................651
APPENDIX D
INDEX..............................................................................................................................658
APPENDIX E
REVISION HISTORY......................................................................................................664
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LIST OF FIGURES (1/6)
Figure No. 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12
Title
Page
CPU Register Set ...........................................................................................................................................97 CPU Address Space.....................................................................................................................................103 Image on Address Space .............................................................................................................................104 Program Space.............................................................................................................................................105 Data Space ...................................................................................................................................................105 Memory Map.................................................................................................................................................106 Internal ROM Area (128 KB).........................................................................................................................107 Internal ROM/Flash Memory Area (256 KB) .................................................................................................107 Internal ROM/Flash Memory Area (384 KB) .................................................................................................108 Internal ROM/Flash Memory Area (512 KB) .................................................................................................108 Internal RAM Area (8 KB) .............................................................................................................................110 Internal RAM Area (12 KB) ...........................................................................................................................110 Internal RAM Area (16 KB) ...........................................................................................................................111 Internal RAM Area (24 KB) ...........................................................................................................................111 On-Chip Peripheral I/O Area.........................................................................................................................112 External Memory Area (When Expanded to 64 K, 256 K, or 1 MB)..............................................................113 External Memory Area (When Expanded to 4 MB).......................................................................................114 Application of Wrap-Around..........................................................................................................................117 Recommended Memory Map (Flash Memory Version) ................................................................................118 Byte Access (8 Bits)......................................................................................................................................130 Halfword Access (16 Bits).............................................................................................................................130 Word Access (32 Bits) ..................................................................................................................................130 Memory Block ...............................................................................................................................................131 Wait Control ..................................................................................................................................................133 Example of Inserting Wait States..................................................................................................................133 Bus Hold Procedure......................................................................................................................................136 Memory Read ...............................................................................................................................................137 Memory Write ...............................................................................................................................................141 Bus Hold Timing ...........................................................................................................................................143 Non-Maskable Interrupt Servicing ................................................................................................................150 Acknowledging Non-Maskable Interrupt Request.........................................................................................151 RETI Instruction Processing .........................................................................................................................152 Maskable Interrupt Servicing ........................................................................................................................156 RETI Instruction Processing .........................................................................................................................157 Example of Multiple Interrupt Servicing ........................................................................................................159 Example of Servicing Interrupt Requests Generated Simultaneously ..........................................................161 Software Exception Processing ....................................................................................................................169 RETI Instruction Processing .........................................................................................................................170 Illegal Opcode...............................................................................................................................................171 Exception Trap Processing...........................................................................................................................172 RETI Instruction Processing .........................................................................................................................173
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LIST OF FIGURES (2/6)
Figure No. 5-13 5-14 5-15 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32
Title
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Pipeline Operation at Interrupt Request Acknowledgment........................................................................... 177 Pipeline Flow and Interrupt Request Signal Generation Timing................................................................... 179 Key Return Block Diagram ........................................................................................................................... 181 Clock Generator ........................................................................................................................................... 183 Oscillation Stabilization Time ....................................................................................................................... 196 Block Diagram of TM0 and TM1................................................................................................................... 201 Control Register Settings When TMn Operates as Interval Timer ............................................................... 211 Configuration of Interval Timer ..................................................................................................................... 212 Timing of Interval Timer Operation ............................................................................................................... 212 Control Register Settings in PPG Output Operation..................................................................................... 213 Configuration of PPG Output........................................................................................................................ 214 PPG Output Operation Timing...................................................................................................................... 214 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register............................................................................................................................ 215 Configuration for Pulse Width Measurement with Free-Running Counter.................................................... 216 Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) ......................................................................................................................... 216 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter.................... 217 CRn1 Capture Operation with Rising Edge Specified .................................................................................. 218 Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified) .................. 218 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers.......................................................................................................................... 219 Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified)......................................................................................................................... 220 Control Register Settings for Pulse Width Measurement by Restarting ....................................................... 221 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) ....................................... 221 Control Register Settings in External Event Counter Mode.......................................................................... 222 Configuration of External Event Counter ...................................................................................................... 223 Timing of External Event Counter Operation (with Rising Edge Specified).................................................. 223 Control Register Settings in Square Wave Output Mode ............................................................................. 224 Timing of Square Wave Output Operation ................................................................................................... 225 Control Register Settings for One-Shot Pulse Output with Software Trigger ............................................... 226 Timing of One-Shot Pulse Output Operation with Software Trigger ............................................................. 227 Control Register Settings for One-Shot Pulse Output with External Trigger ................................................ 228 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) ................ 229 Start Timing of 16-Bit Timer Register n ........................................................................................................ 230 Timing After Changing Compare Register During Timer Count Operation................................................... 230 Data Hold Timing of Capture Register.......................................................................................................... 231 Operation Timing of OVFn Bit ...................................................................................................................... 232 Block Diagram of TM2 to TM7...................................................................................................................... 235 Timing of Interval Timer Operation ............................................................................................................... 242
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LIST OF FIGURES (3/6)
Figure No. 7-33 7-34 7-35 7-36 7-37 7-38 7-39 8-1 8-2 8-3 9-1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27
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Timing of External Event Counter Operation (with Rising Edge Specified) ..................................................245 Square Wave Output Operation Timing........................................................................................................246 Timing of PWM Output .................................................................................................................................248 Timing of Operation Based on CRn0 Transitions .........................................................................................249 Cascade Connection Mode with 16-Bit Resolution.......................................................................................251 Start Timing of Timer n .................................................................................................................................252 Timing After Compare Register Changes During Timer Count Operation....................................................252 Block Diagram of Watch Timer .....................................................................................................................253 Operation Timing of Watch Timer/Interval Timer ..........................................................................................259 Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s).........................................259 Block Diagram of Watchdog Timer ...............................................................................................................260 Block Diagram of 3-Wire Serial I/O...............................................................................................................269 CSIMn Setting (Operation Stop Mode) .........................................................................................................272 CSIMn Setting (3-Wire Serial I/O Mode).......................................................................................................273 Timing of 3-Wire Serial I/O Mode .................................................................................................................274 Block Diagram of I C.....................................................................................................................................276 Serial Bus Configuration Example Using I C Bus .........................................................................................277 Pin Configuration Diagram............................................................................................................................292 I C Bus's Serial Data Transfer Timing ..........................................................................................................292 Start Condition ..............................................................................................................................................293 Address.........................................................................................................................................................293 Transfer Direction Specification....................................................................................................................294 ACK Signal ...................................................................................................................................................295 Stop Condition ..............................................................................................................................................296 Wait Signal....................................................................................................................................................297 Arbitration Timing Example...........................................................................................................................319 Communication Reservation Timing.............................................................................................................322 Timing for Acknowledging Communication Reservations.............................................................................322 Communication Reservation Flowchart ........................................................................................................323 Master Operation Flowchart .........................................................................................................................325 Slave Operation Flowchart ...........................................................................................................................326 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................328 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) .......................................................................331 Block Diagram of I C.....................................................................................................................................335 Serial Bus Configuration Example Using I C Bus .........................................................................................336 Pin Configuration Diagram............................................................................................................................353 I C Bus's Serial Data Transfer Timing ..........................................................................................................353 Start Conditions ............................................................................................................................................354
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LIST OF FIGURES (4/6)
Figure No. 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-50 10-51 10-52 10-53 10-54 10-55 10-56 10-57 10-58 10-59 10-60 10-61 11-1 11-2 11-3 11-4 11-5 11-6
Title
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Address ........................................................................................................................................................ 354 Transfer Direction Specification ................................................................................................................... 355 ACK Signal ................................................................................................................................................... 356 Stop Condition .............................................................................................................................................. 357 Wait Signal ................................................................................................................................................... 358 Arbitration Timing Example .......................................................................................................................... 381 Communication Reservation Timing............................................................................................................. 384 Timing for Accepting Communication Reservations..................................................................................... 384 Communication Reservation Flowchart........................................................................................................ 385 Timing at Which STTn = 1 Cannot Be Set.................................................................................................... 386 Master Communication Start or Stop Flowchart ........................................................................................... 387 Master Operation Flowchart (1).................................................................................................................... 389 Master Operation Flowchart (2).................................................................................................................... 390 Slave Operation Flowchart ........................................................................................................................... 391 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ....................................................................... 393 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) ....................................................................... 396 Block Diagram of UARTn ............................................................................................................................. 400 ASIMn Setting (Operation Stop Mode) ......................................................................................................... 406 ASIMn Setting (Asynchronous Serial Interface Mode) ................................................................................. 407 ASISn Setting (Asynchronous Serial Interface Mode).................................................................................. 408 BRGCn Setting (Asynchronous Serial Interface Mode)................................................................................ 409 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode)................................................ 410 Error Tolerance (When k = 16), Including Sampling Errors.......................................................................... 412 Format of Transmit/Receive Data in Asynchronous Serial Interface............................................................ 413 Timing of Asynchronous Serial Interface Transmit Completion Interrupt ..................................................... 415 Timing of Asynchronous Serial Interface Receive Completion Interrupt ...................................................... 416 Receive Error Timing.................................................................................................................................... 417 Block Diagram of CSI4 ................................................................................................................................. 420 When Transfer Bit Length Other Than 16 Bits Is Set ................................................................................... 421 CSIM4 Setting (Operation Stop Mode) ......................................................................................................... 426 CSIM4 Setting (3-Wire Variable-Length Serial I/O Mode) ............................................................................ 427 CSIB4 Setting (3-Wire Variable-Length Serial I/O Mode)............................................................................. 428 Timing of 3-Wire Variable-Length Serial I/O Mode....................................................................................... 429 Timing of 3-Wire Variable-Length Serial I/O Mode (When CSIB4 = 08H) .................................................... 430 Block Diagram of A/D Converter .................................................................................................................. 432 Basic Operation of A/D Converter ................................................................................................................ 439 Relationship Between Analog Input Voltage and A/D Conversion Result .................................................... 440 A/D Conversion by Hardware Start (with Falling Edge Specified)................................................................ 441 A/D Conversion by Software Start................................................................................................................ 442 Handling of Analog Input Pin ........................................................................................................................ 444
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LIST OF FIGURES (5/6)
Figure No. 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 13-1 13-2 13-3 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 15-1 16-1 17-1 17-2
Title
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A/D Conversion End Interrupt Generation Timing ........................................................................................445 Handling of AVDD Pin ....................................................................................................................................446 Overall Error .................................................................................................................................................447 Quantization Error.........................................................................................................................................448 Zero-Scale Error ...........................................................................................................................................448 Full-Scale Error.............................................................................................................................................449 Differential Linearity Error .............................................................................................................................449 Integral Linearity Error ..................................................................................................................................450 Sampling Time..............................................................................................................................................450 Block Diagram of DMA .................................................................................................................................452 Correspondence Between DRAn Setting Value and Internal RAM (8 KB) ...................................................455 Correspondence Between DRAn Setting Value and Internal RAM (12 KB) .................................................456 Correspondence Between DRAn Setting Value and Internal RAM (16 KB) .................................................457 Correspondence Between DRAn Setting Value and Internal RAM (24 KB) .................................................458 DMA Transfer Operation Timing ...................................................................................................................462 Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously ...............................463 When Interrupt Servicing Occurs Twice During DMA Operation ..................................................................464 Block Diagram of RTO..................................................................................................................................467 Configuration of Real-Time Output Buffer Registers ....................................................................................468 Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0) ............................................................472 Block Diagram of P00 to P07........................................................................................................................478 Block Diagram of P10 to P12, P14, and P15................................................................................................481 Block Diagram of P13 ...................................................................................................................................482 Block Diagram of P20 to P22, P24, and P25................................................................................................486 Block Diagram of P23, P26, and P27 ...........................................................................................................487 Block Diagram of P30 to P32 and P35 to P37..............................................................................................490 Block Diagram of P33 and P34.....................................................................................................................491 Block Diagram of P40 to P47 and P50 to P57..............................................................................................494 Block Diagram P60 to P65............................................................................................................................497 Block Diagram of P70 to P77 and P80 to P83..............................................................................................499 Block Diagram of P90 to P96........................................................................................................................502 Block Diagram of P100 to P107....................................................................................................................506 Block Diagram of P110 to P113....................................................................................................................510 System Reset Timing....................................................................................................................................516 Regulator ......................................................................................................................................................517 Block Diagram of ROM Correction................................................................................................................518 ROM Correction Operation and Program Flow.............................................................................................522
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LIST OF FIGURES (6/6)
Figure No. 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20 19-21 19-22 19-23 19-24 A-1 A-2
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Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)............................... 526 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ............................... 528 Environment Required for Writing Programs to Flash Memory .................................................................... 530 Communication with Dedicated Flash Programmer (UART0) ...................................................................... 530 Communication with Dedicated Flash Programmer (CSI0) .......................................................................... 531 Communication with Dedicated Flash Programmer (CSI0 + HS) ................................................................. 531 VPP Pin Connection Example........................................................................................................................ 533 Conflict of Signals (Serial Interface Input Pin) .............................................................................................. 534 Malfunction of Other Device ......................................................................................................................... 535 Conflict of Signals (RESET Pin) ................................................................................................................... 536 Procedure for Manipulating Flash Memory................................................................................................... 537 Flash Memory Programming Mode .............................................................................................................. 538 Communication Command ........................................................................................................................... 539 IEBus Transfer Signal Format ...................................................................................................................... 544 Master Address Field.................................................................................................................................... 545 Slave Address Field ..................................................................................................................................... 546 Control Field ................................................................................................................................................. 548 Telegraph Length Field ................................................................................................................................ 550 Data Field ..................................................................................................................................................... 551 Bit Configuration of Slave Status.................................................................................................................. 555 Configuration of Lock Address ..................................................................................................................... 556 Bit Format of IEBus ...................................................................................................................................... 557 IEBus Controller Block Diagram ................................................................................................................... 558 Interrupt Generation Timing (for (1), (3), and (4))......................................................................................... 567 Interrupt Generation Timing (for (2) and (5)) ................................................................................................ 568 Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5)) ...................................................... 568 Timing of INTIE2 Interrupt Generation in Locked State (for (3))................................................................... 569 Example of Broadcasting Communication Flag Operation........................................................................... 573 Configuration of Interrupt Control Block ....................................................................................................... 584 Master Transmission .................................................................................................................................... 588 Master Reception ......................................................................................................................................... 590 Slave Transmission ...................................................................................................................................... 592 Slave Reception ........................................................................................................................................... 594 Master Transmission (Interval of Interrupt Occurrence) ............................................................................... 596 Master Reception (Interval of Interrupt Occurrence) .................................................................................... 597 Slave Transmission (Interval of Interrupt Occurrence) ................................................................................. 598 Slave Reception (Interval of Interrupt Occurrence) ...................................................................................... 599 100-Pin Plastic LQFP (Fine Pitch) (14 x 14) ................................................................................................ 642 100-Pin Plastic QFP (14 x 20)...................................................................................................................... 643
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LIST OF TABLES (1/3)
Table No. 1-1 1-2 2-1 2-2 2-3 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 5-4 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3
Title
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Product Lineup of V850/SB1 ..........................................................................................................................30 Product Lineup of V850/SB2 ..........................................................................................................................31 Pin I/O Buffer Power Supplies ........................................................................................................................73 Differences in Pins Between V850/SB1 and V850/SB2 .................................................................................73 Operating States of Pins in Each Operating Mode .........................................................................................80 Program Registers..........................................................................................................................................98 System Register Numbers ..............................................................................................................................99 Interrupt/Exception Table..............................................................................................................................109 Bus Control Pins ...........................................................................................................................................128 Number of Access Clocks.............................................................................................................................129 Bus Priority ...................................................................................................................................................144 Interrupt Source List .....................................................................................................................................147 Interrupt Control Register (xxICn).................................................................................................................164 Priorities of Interrupts and Exceptions ..........................................................................................................174 Description of Key Return Detection Pin ......................................................................................................180 Operating Statuses in HALT Mode ...............................................................................................................190 Operating Statuses in IDLE Mode ................................................................................................................192 Operating Statuses in Software STOP Mode ...............................................................................................194 Configuration of Timers 0 and 1 ...................................................................................................................202 Valid Edge of TIn0 Pin and Capture Trigger of CRn0...................................................................................203 Valid Edge of TIn1 Pin and Capture Trigger of CRn0...................................................................................203 TIn0 Pin Valid Edge and CRn1 Capture Trigger...........................................................................................204 Configuration of Timers 2 to 7 ......................................................................................................................235 Interval Time of Interval Timer ......................................................................................................................254 Configuration of Watch Timer .......................................................................................................................254 Interval Time of Interval Timer ......................................................................................................................258 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................261 Interval Time of Interval Timer ......................................................................................................................261 Configuration of Watchdog Timer .................................................................................................................262 Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................265 Interval Time of Interval Timer ......................................................................................................................266 Configuration of CSIn ...................................................................................................................................269 Configuration of I Cn.....................................................................................................................................278 Selection Clock Setting.................................................................................................................................290
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LIST OF TABLES (2/3)
Table No. 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 11-1 12-1 13-1 13-2 13-3 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 18-1 18-2 18-3 18-4 18-5 18-6
Title
Page
INTIICn Generation Timing and Wait Control............................................................................................... 317 Extension Code Bit Definitions ..................................................................................................................... 319 Status During Arbitration and Interrupt Request Generation Timing ............................................................ 320 Wait Periods ................................................................................................................................................. 321 Configuration of I Cn..................................................................................................................................... 337 Selection Clock Setting ................................................................................................................................ 351 INTIICn Generation Timing and Wait Control............................................................................................... 378 Extension Code Bit Definitions ..................................................................................................................... 380 Status During Arbitration and Interrupt Request Generation Timing ............................................................ 381 Wait Periods ................................................................................................................................................. 383 Wait Time ..................................................................................................................................................... 386 Configuration of UARTn ............................................................................................................................... 399 Relationship Between Main Clock and Baud Rate ....................................................................................... 411 Receive Error Causes .................................................................................................................................. 417 Configuration of CSI4 ................................................................................................................................... 419 Configuration of A/D Converter .................................................................................................................... 433 Internal RAM Area Usable in DMA ............................................................................................................... 454 Configuration of RTO.................................................................................................................................... 467 Operation When Real-Time Output Buffer Registers Are Manipulated ........................................................ 468 Operation Mode and Output Trigger of Real-Time Output Port.................................................................... 470 Pin I/O Buffer Power Supplies ...................................................................................................................... 474 Port 0 Alternate Function Pins...................................................................................................................... 475 Port 1 Alternate Function Pins...................................................................................................................... 479 Port 2 Alternate Function Pins...................................................................................................................... 483 Port 3 Alternate Function Pins...................................................................................................................... 488 Alternate Function Pins of Ports 4 and 5 ...................................................................................................... 492 Port 6 Alternate Function Pins...................................................................................................................... 495 Alternate Function Pins of Ports 7 and 8 ...................................................................................................... 498 Port 9 Alternate Function Pins...................................................................................................................... 500 Port 10 Alternate Function Pins.................................................................................................................... 503 Port 11 Alternate Function Pins.................................................................................................................... 507 Setting When Port Pin Is Used as Alternate Function .................................................................................. 511 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)............................... 527 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) ............................... 529 Signal Generation of Dedicated Flash Programmer (PG-FP3)..................................................................... 532 Pins Used in Serial Interfaces ...................................................................................................................... 533 List of Communication Modes ...................................................................................................................... 539 Flash Memory Control Command................................................................................................................. 540
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LIST OF TABLES (3/3)
Table No. 18-7 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 22-1 C-1 C-2 C-3 C-4 C-5
Title
Page
Response Command ....................................................................................................................................540 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1....................................542 Contents of Control Bits................................................................................................................................547 Control Field for Locked Slave Unit ..............................................................................................................548 Control Field for Unlocked Slave Unit...........................................................................................................548 Acknowledge Signal Output Condition of Control Field ................................................................................549 Contents of Telegraph Length Bit .................................................................................................................550 Internal Registers of IEBus Controller ..........................................................................................................560 Reset Conditions of Flags in ISR Register ...................................................................................................575 Interrupt Source List .....................................................................................................................................585 Communication Error Source Processing List ..............................................................................................586 Surface Mounting Type Soldering Conditions ..............................................................................................637 Symbols in Operand Description ..................................................................................................................651 Symbols Used for Opcode............................................................................................................................652 Symbols Used for Operation Description......................................................................................................652 Symbols Used for Flag Operation.................................................................................................................653 Condition Codes ...........................................................................................................................................653
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The V850/SB1 and V850/SB2 are products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low power operation.
1.1 General
The V850/SB1 and V850/SB2 are 32-bit single-chip microcontrollers that include the V850 Series CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA controller. Based on the V850/SA1TM, the V850/SB1 and V850/SB2 feature various additions, including 3 to 5 V I/O interface support, and ROM correction. For V850/SB2, based on the V850/SB1TM, the peripheral functions of automobile LAN (IEBusTM (Inter Equipment BusTM)) are added. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850/SB1 and V850/SB2 have multiply, saturation operation, and bit manipulation instructions realized with a hardware multiplier for digital servo control. Moreover, as a real-time control system, the V850/SB1 and V850/SB2 enable the realization of extremely high cost-performance for applications that require low power consumption, such as audio equipment, car audio systems, and VCRs. Table 1-1 shows the outlines of the V850/SB1 and V850/SB2 product lineup.
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Table 1-1. Product Lineup of V850/SB1
Product Name Commercial Name V850/SB1 Part Number On-Chip I2C No Yes No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory No Yes No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory 512 KB 24 KB 100-pin QFP (14 x 20) 384 KB 24 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 256 KB 16 KB Mask ROM 128 KB 8 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 512 KB 24 KB 100-pin QFP (14 x 20) 256 KB 16 KB ROM Type Mask ROM Size 128 KB 12 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) RAM Size Package On-Chip IEBus No
PD703031A PD703031AY PD703033A PD70F3033A PD703033AY PD70F3033AY PD703032A PD70F3032A PD703032AY PD70F3032AY PD703031B PD703031BY PD703033B PD70F3033B PD703033BY PD70F3033BY PD703030B PD70F3030B PD703030BY PD70F3030BY PD703032B PD70F3032B PD703032BY PD70F3032BY
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Table 1-2. Product Lineup of V850/SB2
Product Name Commercial Name V850/SB2 Part Number On-Chip I2C No Yes No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory No Yes No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory No Mask ROM Flash memory Yes Mask ROM Flash memory 512 KB 24 KB 100-pin QFP (14 x 20) 384 KB 24 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 256 KB 16 KB Mask ROM 128 KB 8 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 512 KB 24 KB 100-pin QFP (14 x 20) 256 KB 16 KB ROM Type Mask ROM Size 128 KB 12 KB 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) 100-pin QFP (14 x 20)/ 100-pin LQFP (14 x 14) RAM Size Package On-Chip IEBus Yes
PD703034A PD703034AY PD703035A PD70F3035A PD703035AY PD70F3035AY PD703037A PD70F3037A PD703037AY PD70F3037AY PD703034B PD703034BY PD703035B PD70F3035B PD703035BY PD70F3035BY PD703036H PD70F3036H PD703036HY PD70F3036HY PD703037H PD70F3037H PD703037HY PD70F3037HY
The part numbers of the V850/SB1 and V850/SB2 are described as follows in this manual. * A versions A versions of the V850/SB1: PD703031A, A versions of the V850/SB2: PD703034A, * B versions, H versions B versions of the V850/SB1: 703031AY, 703034AY, 703032A, 703035A, 703032AY, 703035AY, 703033A, 703037A, 703033AY, 703037AY, 70F3032A, 70F3032AY, 70F3033A, 70F3033AY 70F3035A, 70F3035AY, 70F3037A, 70F3037AY
PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY,
703033B, 703033BY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY
B and H versions of the V850/SB2: PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY
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* Flash memory versions Flash memory versions of the V850/SB1:
PD70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B,
70F3032BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY
Flash memory versions of the V850/SB2: PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY * Mask ROM versions Mask ROM versions of the V850/SB1: PD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY, 703032A, 703032AY, 703032B, 703032BY, 703033A, 703033AY, 703033B, 703033BY Mask ROM versions of the V850/SB2: PD703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY, 703035B, 703035BY, 703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY * Y versions (with on-chip I C)
2
Y versions of the V850/SB1 (with on-chip I C): PD703030BY, 703031AY, 703031BY, 703032AY, 703032BY,
2
703033AY, 703033BY, 70F3030BY, 70F3032AY, 70F3032BY, 70F3033AY, 70F3033BY Y versions of the V850/SB2 (with on-chip I C): PD703034AY, 703034BY, 703035AY, 703035BY, 703036HY,
2
703037AY, 703037HY, 70F3035AY, 70F3035BY, 70F3036HY, 70F3037AY, 70F3037BY
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1.2 V850/SB1 (A Versions)
1.2.1 Features (V850/SB1 (A versions)) Number of instructions: 74 Minimum instruction execution time 50 ns (operating at 20 MHz, external power supply 5 V, regulator output 3.3 V) General-purpose registers Instruction set 32 bits x 32 registers Signed multiplication (16 x 16 32): 100 ns (operating at 20 MHz) (able to execute instructions in parallel continuously without creating any register hazards). Saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space 16 MB of linear address space (for programs and data) External expandability: expandable to 4 MB Memory block allocation function: 2 MB per block Programmable wait function Idle state insertion function External bus interface 16-bit data bus (address/data multiplex) Address bus: separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory
PD703031A, 703031AY (mask ROM: 128 KB/RAM: 12 KB) PD703033A, 703033AY (mask ROM: 256 KB/RAM: 16 KB) PD703032A, 703032AY (mask ROM: 512 KB/RAM: 24 KB) PD70F3033A, 70F3033AY (flash memory: 256 KB/RAM: 16 KB) PD70F3032A, 70F3032AY (flash memory: 512 KB/RAM: 24 KB)
Interrupts and exceptions
Non-maskable interrupts: 2 sources Maskable interrupts: 37 sources (PD703031A, 703032A, 703033A, 70F3032A, 70F3033A) 38 sources (PD703031AY, 703032AY, 703033AY, 70F3032AY, 70F3033AY) Software exceptions: 32 sources Exception trap: 1 source
I/O lines Timer/counter Watch timer Watchdog timer
Total: 83 (12 input ports and 71 I/O ports) 3 V to 5 V interface enabled 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled) When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. 1 channel
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Serial interface (SIO)
Asynchronous serial interface (UART) Clocked serial interface (CSI) I C bus interface (I C) (only for PD703031AY, 703032AY, 703033AY, 70F3032AY,
2 2
and 70F3033AY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I C: CSI (8-/16-bit valuable): A/D converter DMA controller Real-time output port (RTP) ROM correction Regulator Key return function Clock generator Power-saving functions Package CMOS structure 10-bit resolution: 12 channels Internal RAM on-chip peripheral I/O: 6 channels 8 bits x 1 channel or 4 bits x 2 channels Modifiable 4 points 4.0 V to 5.5 V input internal 3.3 V 4 to 8 selecting enabled, falling edge fixed During main clock or subclock operation 5-level CPU clock (including sub operations) HALT/IDLE/STOP modes 100-pin plastic LQFP (fine pitch, 14 x 14) 100-pin plastic QFP (14 x 20) All static circuits
2
2 channels 2 channels 1 channel
Dedicated baud rate generator: 3 channels
1.2.2 Application fields (V850/SB1 (A versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV.
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1.2.3 Ordering information (V850/SB1 (A versions))
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (512 KB) Mask ROM (512 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (512 KB) Flash memory (512 KB)
PD703031AGC-xxx-8EU PD703031AGF-xxx-3BA PD703031AYGC-xxx-8EU PD703031AYGF-xxx-3BA PD703033AGC-xxx-8EU PD703033AGF-xxx-3BA PD703033AYGC-xxx-8EU PD703033AYGF-xxx-3BA PD703032AGF-xxx-3BA PD703032AYGF-xxx-3BA PD70F3033AGC-8EU PD70F3033AGF-3BA PD70F3033AYGC-8EU PD70F3033AYGF-3BA PD70F3032AGF-3BA PD70F3032AYGF-3BA
Remarks 1. xxx indicates ROM code suffix. 2. ROMless devices are not provided.
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1.2.4 Pin configuration (top view) (V850/SB1 (A versions)) 100-pin plastic LQFP (fine pitch) (14 x 14) * PD703031AGC-xxx-8EU * PD703031AYGC-xxx-8EU * PD703033AGC-xxx-8EU * PD703033AYGC-xxx-8EU
P20/SI2/SDA1 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 Note 2 P12/SCK0/SCL0 P11/SO0 Note 2 P10/SI0/SDA0 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
* PD70F3033AGC-8EU * PD70F3033AYGC-8EU
Note 2
P21/SO2 Note 2 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/VPP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. 2.
IC (PD703031A, 703031AY, 703033A, 703033AY): Connect directly to VSS. VPP (PD70F3033A, 70F3033AY): Connect to VSS in normal operation mode. SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703033AY, and 70F3033AY.
36
P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3 User's Manual U13850EJ6V0UD
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100-pin plastic QFP (14 x 20) * PD703031AGF-xxx-3BA * PD703031AYGF-xxx-3BA * PD703032AGF-xxx-3BA * PD703032AYGF-xxx-3BA * PD703033AGF-xxx-3BA * PD703033AYGF-xxx-3BA * PD70F3032AGF-3BA * PD70F3032AYGF-3BA
P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
* PD70F3033AGF-3BA * PD70F3033AYGF-3BA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Notes 1.
IC (PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY): Connect directly to VSS. VPP (PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY): Connect to VSS in normal operation mode.
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703032AY, 703033AY, 70F3032AY, and 70F3033AY.
P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
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Pin names (V850/SB1 (A versions)) A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: Address bus Address/data bus A/D trigger input Analog input Asynchronous serial clock Address strobe Analog VDD Analog reference voltage Analog VSS Power supply for bus interface Ground for bus interface Clock output Data strobe Power supply for port Ground for port Hold acknowledge Hold request Internally connected Interrupt request from peripherals Key return Lower byte enable Non-maskable interrupt request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P77: P80 to P83: P90 to P96: P100 to P107: P110 to P113: RD: REGC: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TI00, TI01, TI10, TI11, TI2 to TI5: TO0 to TO5: TXD0,TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Timer input Timer output Transmit data Upper byte enable Power supply Programming power supply Ground Wait Write strobe high level data Write strobe low level data Crystal for main clock Crystal for subclock Port 7 Port 8 Port 9 Port 10 Port 11 Read Regulator control Reset Real-time output port RTP trigger Read/write status Receive data Serial clock Serial clock Serial data Serial input Serial output
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1.2.5 Function blocks (V850/SB1 (A versions)) (1) Internal block diagram
NMI INTP0 to INTP6 ROM INTC Note 1 Timer/counter 16-bit timer: TM0, TM1 8-bit timer: TM2 to TM7 SIO SO0 SI0/SDA0Note 3 Note 3 SCK0/SCL0 SO2 Note 3 SI2/SDA1 Note 3 SCK2/SCL1 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7 CSI0/I2C0 Note 4 CSI2/I2C1 Note 4 PC 32-bit barrel shifter RAM System register
General-purpose registers 32 bits x 32
CPU ROM correction Multiplier 16 x1632 BCU
ALU Instruction queue
HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W /WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
TI00,TI01, TI10,TI11 TO0,TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5
Note 2
CSI1/UART0 Ports RTP CSI3/UART1 CG Variable length CSI4 P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 A/D converter CLKOUT X1 X2 XT1 XT2 RESET
Key return
RTP0 to RTP7 RTPTRG
3.3 V
AVDD AVREF AVSS ANI0 to ANI11 ADTRG Regulator
DMAC: 6 ch
VDD
REGC
Watch timer Watchdog timer
VSS BVDD BVSS EVDD EVSS VPP IC
Note 5
Note 6
Notes 1.
PD703031A, 703031AY: PD703033A, 703033AY: PD703032A, 703032AY:
128 KB (mask ROM) 256 KB (mask ROM) 512 KB (mask ROM)
PD70F3033A, 70F3033AY: 256 KB (flash memory) PD70F3032A, 70F3032AY: 512 KB (flash memory)
2.
PD703031A, 703031AY: PD703032A, 703032AY, 70F3032A, 70F3032AY:
12 KB 24 KB
PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB
3. 4. 5. 6. SDA0, SDA1, SCL0, and SCL1 pins are available only in the PD703031AY, 703032AY, 703033AY, 70F3032AY, and 70F3033AY. I C function is available only in the PD703031AY, 703032AY, 703033AY, 70F3032AY, and
2
70F3033AY.
PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. prefetched instruction code is stored in an instruction queue. (c) ROM This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H. The ROM capacity varies depending on the product. The ROM capacity of each product is shown below. The
PD703031A, 703031AY: PD703033A, 703033AY: PD703032A, 703032AY:
128 KB (mask ROM) 256 KB (mask ROM) 512 KB (mask ROM)
PD70F3033A, 70F3033AY: 256 KB (flash memory) PD70F3032A, 70F3032AY: 512 KB (flash memory)
ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each product is shown below.
PD703031A, 703031AY:
12 KB (mapping starts at FFFFC000H)
PD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB (mapping starts at FFFFB000H) PD703032A, 703032AY, 70F3032A, 70F3032AY: 24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) Clock generator (CG) The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating clock for the CPU (fCPU).
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(g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) Watch timer This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the main clock. (i) Watchdog timer A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I C bus interfaces (I C0, I C1) comprise five channels.
2 2 2
Two of these channels are
2
switchable between the UART and CSI and another two switchable between CSI and I C. For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins. For I C0 and I C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins. I C0 and I C1 are equipped only in the PD703031AY, 703032AY, 703033AY, 70F3032AY, and
2 2 2 2
70F3033AY. For UART and CSI4, a dedicated baud rate generator is equipped. (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses the successive approximation method. (l) DMA controller A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. (m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit x 2 channels.
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(n) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 I/O 8-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 6-bit I/O 8-bit input 4-bit input 7-bit I/O 8-bit I/O 4-bit I/O External bus interface control signal I/O Real-time output port, external address bus, key return input Wait control, external address bus External address bus A/D converter analog input Port Function Generalpurpose port Control Function NMI, external interrupt, A/D converter trigger, RTP trigger Serial interface Serial interface, timer I/O Timer I/O, external address bus, serial interface External address/data bus
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1.3 V850/SB1 (B Versions)
1.3.1 Features (V850/SB1 (B versions)) Number of instructions: 74 Minimum instruction execution time 50 ns (@ 20 MHz operation, external power supply 5 V, regulator output 3.3 V operation) General-purpose registers Instruction set 32 bits x 32 registers Signed multiplication (16 x 16 32): 100 ns (@ 20 MHz operation) (able to execute instructions in parallel continuously without creating any register hazards). Saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space 16 MB of linear address space (for programs and data) External expandability: expandable to 4 MB Memory block allocation function: 2 MB per block Programmable wait function Idle state insertion function External bus interface 16-bit data bus (address/data multiplex) Address bus: separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory
PD703031B, 703031BY (mask ROM: 128 KB/RAM: 8 KB) PD703033B, 703033BY (mask ROM: 256 KB/RAM: 16 KB) PD703030B, 703030BY (mask ROM: 384 KB/RAM: 24 KB) PD703032B, 703032BY (mask ROM: 512 KB/RAM: 24 KB) PD70F3033B, 70F3033BY (flash memory: 256 KB/RAM: 16 KB) PD70F3030B, 70F3030BY (flash memory: 384 KB/RAM: 24 KB) PD70F3032B, 70F3032BY (flash memory: 512 KB/RAM: 24 KB)
Interrupts and exceptions
Non-maskable interrupts: 2 sources Maskable interrupts: 37 sources (PD703030B, 703031B, 703032B, 703033B, 70F3030B, 70F3032B, 70F3033B) 38 sources (PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY, 70F3032BY, 70F3033BY) Software exceptions: 32 sources Exception trap: 1 source
I/O lines Timer/counter Watch timer Watchdog timer
Total: 83 (12 input ports and 71 I/O ports) 3 V to 5 V interface enabled 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled) When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. 1 channel
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Serial interface (SIO)
Asynchronous serial interface (UART) Clocked serial interface (CSI) I C bus interface (I C) (only for PD703030BY, 703031BY, 703032BY, 703033BY,
2 2
70F3030BY, 70F3032BY, and 70F3033BY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I C: CSI (8-/16-bit valuable): A/D converter DMA controller Real-time output port (RTP) ROM correction Regulator Key return function Clock generator Power-saving functions Package CMOS structure 10-bit resolution: 12 channels Internal RAM on-chip peripheral I/O: 6 channels 8 bits x 1 channel or 4 bits x 2 channels Modifiable 4 points 4.0 V to 5.5 V input internal 3.3 V 4 to 8 selecting enabled, falling edge fixed During main clock or subclock operation 5-level CPU clock (including sub operations) HALT/IDLE/STOP modes 100-pin plastic LQFP (fine pitch, 14 x 14) 100-pin plastic QFP (14 x 20) All static circuits
2
2 channels 2 channels 1 channel
Dedicated baud rate generator: 3 channels
1.3.2 Application fields (V850/SB1 (B versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV.
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1.3.3 Ordering information (V850/SB1 (B versions))
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (512 KB) Mask ROM (512 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (512 KB) Flash memory (512 KB)
PD703031BGC-xxx-8EU PD703031BGF-xxx-3BA PD703031BYGC-xxx-8EU PD703031BYGF-xxx-3BA PD703033BGC-xxx-8EU PD703033BGF-xxx-3BA PD703033BYGC-xxx-8EU PD703033BYGF-xxx-3BA PD703030BGC-xxx-8EU PD703030BGF-xxx-3BA PD703030BYGC-xxx-8EU PD703030BYGF-xxx-3BA PD703032BGF-xxx-3BA PD703032BYGF-xxx-3BA PD70F3033BGC-8EU PD70F3033BGF-3BA PD70F3033BYGC-8EU PD70F3033BYGF-3BA PD70F3030BGC-8EU PD70F3030BGF-3BA PD70F3030BYGC-8EU PD70F3030BYGF-3BA PD70F3032BGF-3BA PD70F3032BYGF-3BA
Remarks 1. xxx indicates ROM code suffix. 2. ROMless devices are not provided.
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1.3.4 Pin configuration (top view) (V850/SB1 (B versions)) 100-pin plastic LQFP (fine pitch) (14 x 14) * PD703030BGC-xxx-8EU * PD703030BYGC-xxx-8EU * PD703031BGC-xxx-8EU * PD703031BYGC-xxx-8EU * PD703033BGC-xxx-8EU * PD703033BYGC-xxx-8EU * PD70F3030BGC-8EU * PD70F3030BYGC-8EU * PD70F3033BGC-8EU * PD70F3033BYGC-8EU
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P20/SI2/SDA1 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 Note 2 P12/SCK0/SCL0 P11/SO0 Note 2 P10/SI0/SDA0 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
Note 2
P21/SO2 Note 2 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/VPP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. 2.
IC (PD703030B, 703030BY, 703031B, 703031BY, 703033B, 703033BY): Connect directly to VSS. VPP (PD70F3030B, 70F3030BY, 70F3033B, 70F3033BY): Connect to VSS in normal operation mode. SCL0, SCL1, SDA0, and SDA1 are available only in the 703030BY, PD703031BY, 703033BY, 70F3030BY, and 70F3033BY.
46
P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3 User's Manual U13850EJ6V0UD
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100-pin plastic QFP (14 x 20) * PD703030BGF-xxx-3BA * PD703030BYGF-xxx-3BA * PD703031BGF-xxx-3BA * PD703031BYGF-xxx-3BA * PD703032BGF-xxx-3BA * PD703032BYGF-xxx-3BA * PD703033BGF-xxx-3BA * PD703033BYGF-xxx-3BA * PD70F3030BGF-3BA * PD70F3030BYGF-3BA * PD70F3032BGF-3BA * PD70F3032BYGF-3BA * PD70F3033BGF-3BA * PD70F3033BYGF-3BA
P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Notes 1.
IC (PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY): Connect directly to VSS. VPP (PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY): Connect to VSS in normal operation mode.
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY, 70F3032BY, and 70F3033BY.
P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
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Pin names (V850/SB1 (B versions)) A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: Address bus Address/data bus A/D trigger input Analog input Asynchronous serial clock Address strobe Analog VDD Analog reference voltage Analog VSS Power supply for bus interface Ground for bus interface Clock output Data strobe Power supply for port Ground for port Hold acknowledge Hold request Internally connected Interrupt request from peripherals Key return Lower byte enable Non-maskable interrupt request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P77: P80 to P83: P90 to P96: P100 to P107: P110 to P113: RD: REGC: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TI00, TI01, TI10, TI11, TI2 to TI5: TO0 to TO5: TXD0,TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Timer input Timer output Transmit data Upper byte enable Power supply Programming power supply Ground Wait Write strobe high level data Write strobe low level data Crystal for main clock Crystal for subclock Port 7 Port 8 Port 9 Port 10 Port 11 Read Regulator control Reset Real-time output port RTP trigger Read/write status Receive data Serial clock Serial clock Serial data Serial input Serial output
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1.3.5 Function blocks (V850/SB1 (B versions)) (1) Internal block diagram
NMI INTP0 to INTP6 ROM INTC Note 1 Timer/counter 16-bit timer: TM0, TM1 8-bit timer: TM2 to TM7 SIO SO0 SI0/SDA0Note 3 Note 3 SCK0/SCL0 SO2 Note 3 SI2/SDA1 Note 3 SCK2/SCL1 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7 CSI0/I2C0 Note 4 CSI2/I2C1 Note 4 PC 32-bit barrel shifter RAM System register
General-purpose registers 32 bits x 32
CPU ROM correction Multiplier 16 x1632 BCU
ALU Instruction queue
HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W /WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
TI00,TI01, TI10,TI11 TO0,TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5
Note 2
CSI1/UART0 Ports RTP CSI3/UART1 CG Variable length CSI4 P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 A/D converter CLKOUT X1 X2 XT1 XT2 RESET
Key return
RTP0 to RTP7 RTPTRG
3.3 V
AVDD AVREF AVSS ANI0 to ANI11 ADTRG Regulator
DMAC: 6 ch
VDD
REGC
Watch timer Watchdog timer
VSS BVDD BVSS EVDD EVSS VPP IC
Note 5
Note 6
Notes 1.
2.
3. 4. 5. 6.
128 KB (mask ROM) PD703031B, 703031BY: 256 KB (mask ROM) PD703033B, 703033BY: 384 K (mask ROM) PD703030B, 703030BY: 512 K (mask ROM) PD703032B, 703032BY: PD70F3033B, 70F3033BY: 256 K (flash memory) PD70F3030B, 70F3030BY: 384 K (flash memory) PD70F3032B, 70F3032BY: 512 K (flash memory) 8 KB PD703031B, 703031BY: PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB 24 KB PD703030B, 703030BY, 703032B, 703032BY,: 70F3030B, 70F3030BY, 70F3032B, 70F3032BY SDA0, SDA1, SCL0, and SCL1 pins are available only in the PD703030BY, 703031BY, 703032BY, 703033BY, 70F3032BY, 70F3030BY, and 70F3033BY 2 I C function is available only in the PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY, 70F3032BY, and 70F3033BY PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. prefetched instruction code is stored in an instruction queue. (c) ROM This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H. The ROM capacity varies depending on the product. The ROM capacity of each product is shown below. The
PD703031B, 703031BY: PD703033B, 703033BY: PD703030B, 703030BY: PD703032B, 703032BY:
128 KB (mask ROM) 256 KB (mask ROM) 384 KB (mask ROM) 512 KB (mask ROM)
PD70F3033B, 70F3033BY: 256 KB (flash memory) PD70F3030B, 70F3030BY: 384 KB (flash memory) PD70F3032B, 70F3032BY: 512 KB (flash memory)
ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each product is shown below.
PD703031B, 703031BY: PD703030B, 703030BY, 70F3030B, 70F3030BY,
703032B, 703032BY, 70F3032B, 70F3032BY:
8 KB (mapping starts at FFFFD000H)
PD703033B, 703033BY, 70F3033B, 70F3033BY: 16 KB (mapping starts at FFFFB000H)
24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources.
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(f) Clock generator (CG) The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) Watch timer This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the main clock. (i) Watchdog timer A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB1 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I C bus interfaces (I C0, I C1) comprise five channels.
2 2 2
Two of these channels are
2
switchable between the UART and CSI and another two switchable between CSI and I C. For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins. For I C0 and I C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins. I C0 and I C1 are equipped only in the PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY,
2 2 2 2
70F3032BY, and 70F3033BY. For UART and CSI4, a dedicated baud rate generator is equipped. (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses the successive approximation method. (l) DMA controller A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
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(m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit x 2 channels. (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 I/O 8-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 6-bit I/O 8-bit input 4-bit input 7-bit I/O 8-bit I/O 4-bit I/O External bus interface control signal I/O Real-time output port, external address bus, key return input Wait control, external address bus External address bus A/D converter analog input Port Function Generalpurpose port Control Function NMI, external interrupt, A/D converter trigger, RTP trigger Serial interface Serial interface, timer I/O Timer I/O, external address bus, serial interface External address/data bus
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1.4 V850/SB2 (A Versions)
1.4.1 Features (V850/SB2 (A versions)) Number of instructions: 74 Minimum instruction execution time 79 ns (operating at 12.58 MHz, external power supply 5 V, regulator output 3.0 V) General-purpose registers Instruction set 32 bits x 32 registers Signed multiplication (16 x 16 32): 158 ns (operating at 12.58 MHz) (able to execute instructions in parallel continuously without creating any register hazards). Saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space 16 MB of linear address space (for programs and data) External expandability: expandable to 4 MB Memory block allocation function: 2 MB per block Programmable wait function Idle state insertion function External bus interface 16-bit data bus (address/data multiplex) Address bus: separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory
PD703034A, 703034AY (mask ROM: 128 KB/RAM: 12 KB) PD703035A, 703035AY (mask ROM: 256 KB/RAM: 16 KB) PD703037A, 703037AY (mask ROM: 512 KB/RAM: 24 KB) PD70F3035A, 70F3035AY (flash memory: 256 KB/RAM: 16 KB) PD70F3037A, 70F3037AY (flash memory: 512 KB/RAM: 24 KB)
Interrupts and exceptions
Non-maskable interrupts: 2 sources Maskable interrupts: 39 sources (PD703034A, 703035A, 703037A, 70F3035A, 70F3037A) 40 sources (PD703034AY, 703035AY, 703037AY, 70F3035AY, 70F3037AY) Software exceptions: 32 sources Exception trap: 1 source
I/O lines Timer/counter Watch timer Watchdog timer Serial interface (SIO)
Total: 83 (12 input ports and 71 I/O ports) 3 V to 5 V interface enabled 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (four PWM outputs, cascade connection enabled) When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. 1 channel Asynchronous serial interface (UART) Clocked serial interface (CSI)
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I C bus interface (I C) (only for PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I C: CSI (8-/16-bit valuable): A/D converter DMA controller Real-time output port (RTP) ROM correction Regulator Key return function Clock generator Power-saving functions IEBus controller Package CMOS structure 10-bit resolution: 12 channels Internal RAM on-chip peripheral I/O: 6 channels 8 bits x 1 channel or 4 bits x 2 channels Modifiable 4 points 4.0 V to 5.5 V input internal 3.0 V 4 to 8 selecting enabled, falling edge fixed During main clock or subclock operation 5-level CPU clock (including sub operations) HALT/IDLE/STOP modes 1 ch 100-pin plastic LQFP (fine pitch, 14 x 14) 100-pin plastic QFP (14 x 20) All static circuits
2
2
2
2 channels 2 channels 1 channel
Dedicated baud rate generator: 3 channels
1.4.2 Application fields (V850/SB2 (A versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV.
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1.4.3 Ordering information (V850/SB2 (A versions))
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (512 KB) Mask ROM (512 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (512 KB) Flash memory (512 KB)
PD703034AGC-xxx-8EU PD703034AGF-xxx-3BA PD703034AYGC-xxx-8EU PD703034AYGF-xxx-3BA PD703035AGC-xxx-8EU PD703035AGF-xxx-3BA PD703035AYGC-xxx-8EU PD703035AYGF-xxx-3BA PD703037AGF-xxx-3BA PD703037AYGF-xxx-3BA PD70F3035AGC-8EU PD70F3035AGF-3BA PD70F3035AYGF-8EU PD70F3035AYGF-3BA PD70F3037AGF-3BA PD70F3037AYGF-3BA
Remarks 1. xxx indicates ROM code suffix. 2. ROMless devices are not provided.
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1.4.4 Pin configuration (top view) (V850/SB2 (A versions)) 100-pin plastic LQFP (fine pitch) (14 x 14) * PD703034AGC-xxx-8EU * PD703034AYGC-xxx-8EU * PD703035AGC-xxx-8EU * PD703035AYGC-xxx-8EU
P20/SI2/SDA1 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 Note 2 P12/SCK0/SCL0 P11/SO0 Note 2 P10/SI0/SDA0 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
* PD70F3035AGC-8EU * PD70F3035AYGC-8EU
Note 2
P21/SO2 Note 2 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/VPP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. 2.
IC (PD703034A, 703034AY, 703035A, 703035AY): Connect directly to VSS. VPP (PD70F3035A, 70F3035AY): Connect to VSS in normal operation mode. SCL0, SCL1, SDA0, and SDA1 are available only in the PD703034AY, 703035AY, and 70F3035AY.
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P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3 User's Manual U13850EJ6V0UD
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100-pin plastic QFP (14 x 20) * PD703034AGF-xxx-3BA * PD703034AYGF-xxx-3BA * PD703035AGF-xxx-3BA * PD703035AYGF-xxx-3BA * PD703037AGF-xxx-3BA * PD703037AYGF-xxx-3BA * PD70F3035AGF-3BA * PD70F3035AYGF-3BA
P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
* PD70F3037AGF-3BA * PD70F3037AYGF-3BA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Notes 1.
IC (PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY): Connect directly to VSS. VPP (PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY): Connect to VSS in normal operation mode.
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY.
P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
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Pin names (V850/SB2) A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: IC: IERX: IETX: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: Address bus Address/data bus A/D trigger input Analog input Asynchronous serial clock Address strobe Analog VDD Analog reference voltage Analog VSS Power supply for bus interface Ground for bus interface Clock output Data strobe Power supply for port Ground for port Hold acknowledge Hold request Internally connected IEBus receive data IEBus transmit data Interrupt request from peripherals Key return Lower byte enable Non-maskable interrupt request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P77: P80 to P83: P90 to P96: P100 to P107: P110 to P113: RD: REGC: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TI00, TI01, TI10, TI11, TI2 to TI5: TO0 to TO5: TXD0,TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Timer input Timer output Transmit data Upper byte enable Power supply Programming power supply Ground Wait Write strobe high level data Write strobe low level data Crystal for main clock Crystal for subclock Port 7 Port 8 Port 9 Port 10 Port 11 Read Regulator control Reset Real-time output port RTP trigger Read/write status Receive data Serial clock Serial clock Serial data Serial input Serial output
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1.4.5 Function blocks (V850/SB2 (A versions)) (1) Internal block diagram
ROM NMI INTP0 to INTP6 INTC Note 1 Timer/counter 16-bit timer: TM0, TM1 8-bit timer: TM2 to TM7 SIO SI0/SDA0 SCK0/SCL0Note 3 SO2 SI2/SDA1Note 3 SCK2/SCL1Note 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7
Note 3
CPU PC 32-bit barrel shifter ROM correction Multiplier 16 x1632 BCU
ALU Instruction queue
HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W /WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
TI00,TI01, TI10,TI11 TO0,TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5
RAM
System register
General-purpose registers 32 bits x 32
Note 2
SO0
CSI0/I2C0 Note 4 CSI2/I2C1 Note 4
CSI1/UART0 Ports RTP CSI3/UART1 CG Variable length CSI4 P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 A/D converter CLKOUT X1 X2 XT1 XT2 RESET
Key return
RTP0 to RTP7 RTPTRG
3.0 V
AVDD AVREF AVSS ANI0 to ANI11 ADTRG Regulator
DMAC: 6 ch
VDD
REGC
Watch timer Watchdog timer IETX IERX IEBus
VSS BVDD BVSS EVDD EVSS VPPNote 6 ICNote 6
Notes 1.
2.
3. 4. 5. 6.
128 KB (mask ROM) PD703034A, 703034AY: 256 KB (mask ROM) PD703035A, 703035AY: 512 KB (mask ROM) PD703037A, 703037AY: PD70F3035A, 70F3035AY: 256 KB (flash memory) PD70F3037A, 70F3037AY: 512 KB (flash memory) 12 KB PD703034A, 703034AY: PD703035A, 703035AY, 70F3035A, 70F3035AY: 16 KB 20 KB PD703036A, 703036AY: PD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB SDA0, SDA1, SCL0, and SCL1 pins are available only in the PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY 2 I C function is available only in the PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. prefetched instruction code is stored in an instruction queue. (c) ROM This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H. The ROM capacity varies depending on the product. The ROM capacity of each product is shown below. The
PD703034A, 703034AY: PD703035A, 703035AY: PD70F3035A, 70F3035AY: PD703037A, 703037AY: PD70F3037A, 70F3037AY:
128 KB (mask ROM) 256 KB (mask ROM) 256 KB (flash memory) 512 KB (mask ROM) 512 KB (flash memory)
ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each product is shown below.
PD703034A, 703034AY:
12 KB (mapping starts at FFFFC000H)
PD703035A, 703035AY, 70F3035A, 70F3035AY: 16 KB (mapping starts at FFFFB000H) PD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) Clock generator (CG) The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating clock for the CPU (fCPU).
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(g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) Watch timer This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the main clock. (i) Watchdog timer A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB2 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I C bus interfaces (I C0, I C1) comprise five channels.
2 2 2
Two of these channels are
2
switchable between the UART and CSI and another two switchable between CSI and I C. For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins. For I C0 and I C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins. I C0 and I C1 are equipped only in the PD703034AY, 703035AY, 703037AY, 70F3035AY, and
2 2 2 2
70F3037AY. For UART and CSI4, a dedicated baud rate generator is equipped. (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses the successive approximation method. (l) DMA controller A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. (m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit x 2 channels.
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(n) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 I/O 8-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 6-bit I/O 8-bit input 4-bit input 7-bit I/O 8-bit I/O External bus interface control signal I/O Real-time output port, external address bus, key return input, IEBus data I/O Wait control, external address bus External address bus A/D converter analog input Port Function Generalpurpose port Control Function NMI, external interrupt, A/D converter trigger, RTP trigger Serial interface Serial interface, timer I/O Timer I/O, external address bus, serial interface External address/data bus
Port 11
4-bit I/O
(o) IEBus controller The IEBus controller is a small-scale digital data transfer system aiming at data transfer among units. The IEBus controller is incorporated only in the V850/SB2.
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1.5 V850/SB2 (B and H Versions)
1.5.1 Features (V850/SB2 (B and H versions)) Number of instructions: 74 Minimum instruction execution time B versions: 79 ns (@ 12.58 MHz operation, external power supply 5 V, regulator output 3.0 V operation) H versions: 53 ns (@ 18.87 MHz operation, external power supply 5 V, regulator output 3.3 V operation) General-purpose registers Instruction set 32 bits x 32 registers Signed multiplication (16 x 16 32): (able to execute instructions in parallel continuously without creating any register hazards). B versions: 158 ns (@ 12.58 MHz operation) H versions: 106 ns (@ 18.87 MHz operation) Saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space 16 MB of linear address space (for programs and data) External expandability: expandable to 4 MB Memory block allocation function: 2 MB per block Programmable wait function Idle state insertion function External bus interface 16-bit data bus (address/data multiplex) Address bus: separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory
PD703034B, 703034BY (mask ROM: 128 KB/RAM: 8 KB) PD703035B, 703035BY (mask ROM: 256 KB/RAM: 16 KB) PD703036H, 703036HY (mask ROM: 384 KB/RAM: 24 KB) PD703037H, 703037HY (mask ROM: 512 KB/RAM: 24 KB) PD70F3035B, 70F3035BY (flash memory: 256 KB/RAM: 16 KB) PD70F3036H, 70F3036HY (flash memory: 384 KB/RAM: 24 KB) PD70F3037H, 70F3037HY (flash memory: 512 KB/RAM: 24 KB)
Interrupts and exceptions
Non-maskable interrupts: 2 sources Maskable interrupts: 39 sources (PD703034B, 703035B, 703036H, 703037H, 70F3035B, 70F3036H, 70F3037H) 40 sources (PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, 70F3037HY) Software exceptions: 32 sources Exception trap: 1 source
I/O lines Timer/counter
Total: 83 (12 input ports and 71 I/O ports) 3 V to 5 V interface enabled 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (four PWM outputs, cascade connection enabled)
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Watch timer Watchdog timer Serial interface (SIO)
When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. 1 channel Asynchronous serial interface (UART) Clocked serial interface (CSI) I C bus interface (I C) (only for PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, and 70F3037HY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I C: CSI (8-/16-bit valuable):
2 2 2
2 channels 2 channels 1 channel
Dedicated baud rate generator: 3 channels A/D converter DMA controller Real-time output port (RTP) ROM correction Regulator Key return function Clock generator Power-saving functions IEBus controller Package CMOS structure 10-bit resolution: 12 channels Internal RAM on-chip peripheral I/O: 6 channels 8 bits x 1 channel or 4 bits x 2 channels Modifiable 4 points 4.0 V to 5.5 V input internal 3.0 V 4 to 8 selecting enabled, falling edge fixed During main clock or subclock operation 5-level CPU clock (including sub operations) HALT/IDLE/STOP modes 1 ch 100-pin plastic LQFP (fine pitch, 14 x 14) 100-pin plastic QFP (14 x 20) All static circuits
1.5.2 Application fields (V850/SB2 (B and H versions)) AV equipment Example: Audio, car audio equipment, VCR, and TV.
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1.5.3 Ordering information (V850/SB2 (B and H versions))
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (384 KB) Mask ROM (512 KB) Mask ROM (512 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (384 KB) Flash memory (512 KB) Flash memory (512 KB)
PD703034BGC-xxx-8EU PD703034BGF-xxx-3BA PD703034BYGC-xxx-8EU PD703034BYGF-xxx-3BA PD703035BGC-xxx-8EU PD703035BGF-xxx-3BA PD703035BYGC-xxx-8EU PD703035BYGF-xxx-3BA
PD703036HGC-xxx-8EU PD703036HGF-xxx-3BA PD703036HYGC-xxx-8EU PD703036HYGF-xxx-3BA
PD703037HGF-xxx-3BA PD703037HYGF-xxx-3BA PD70F3035BGC-8EU PD70F3035BGF-3BA PD70F3035BYGF-8EU PD70F3035BYGF-3BA
PD70F3036HGC-8EU PD70F3036HGF-3BA PD70F3036HYGC-8EU PD70F3036HYGF-3BA
PD70F3037HGF-3BA PD70F3037HYGF-3BA
Note In planning
Remarks 1. xxx indicates ROM code suffix. 2. ROMless devices are not provided.
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1.5.4 Pin configuration (top view) (V850/SB2 (B and H versions)) 100-pin plastic LQFP (fine pitch) (14 x 14) * PD703034BGC-xxx-8EU * PD703034BYGC-xxx-8EU * PD703035BGC-xxx-8EU * PD703035BYGC-xxx-8EU * PD703036HGC-xxx-8EU * PD703036HYGC-xxx-8EU * PD70F3035BGC-8EU * PD70F3035BYGC-8EU
P20/SI2/SDA1 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 Note 2 P12/SCK0/SCL0 P11/SO0 Note 2 P10/SI0/SDA0 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
* PD70F3036HGC-8EU * PD70F3036HYGC-8EU
Note 2
P21/SO2 Note 2 P22/SCK2/SCL1 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/VPP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. 2.
IC (PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY): Connect directly to VSS. VPP (PD70F3035B, 70F3035BY, 70F3036H, 70F3036HY): Connect to VSS in normal operation mode. SCL0, SCL1, SDA0, and SDA1 are available only in the PD703034BY, 703035BY, 703036HY, 70F3035BY, and 70F3036HY.
66
P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3 User's Manual U13850EJ6V0UD
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100-pin plastic QFP (14 x 20) * PD703034BGF-xxx-3BA * PD703034BYGF-xxx-3BA * PD703035BGF-xxx-3BA * PD703035BYGF-xxx-3BA * PD703036HGF-xxx-3BA * PD703036HYGF-xxx-3BA * PD703037HGF-xxx-3BA * PD703037HYGF-xxx-3BA * PD70F3035BGF-3BA * PD70F3035BYGF-3BA * PD70F3036HGF-xxx-3BA * PD70F3036HYGF-xxx-3BA * PD70F3037HGF-3BA * PD70F3037HYGF-3BA
P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Notes 1.
IC (PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY): Connect directly to VSS. VPP (PD70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY): Connect to VSS in normal operation mode.
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, and 70F3037HY.
P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
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Pin names (V850/SB2 (B and H versions)) A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: IC: IERX: IETX: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: Address bus Address/data bus A/D trigger input Analog input Asynchronous serial clock Address strobe Analog VDD Analog reference voltage Analog VSS Power supply for bus interface Ground for bus interface Clock output Data strobe Power supply for port Ground for port Hold acknowledge Hold request Internally connected IEBus receive data IEBus transmit data Interrupt request from peripherals Key return Lower byte enable Non-maskable interrupt request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P77: P80 to P83: P90 to P96: P100 to P107: P110 to P113: RD: REGC: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TI00, TI01, TI10, TI11, TI2 to TI5: TO0 to TO5: TXD0,TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Timer input Timer output Transmit data Upper byte enable Power supply Programming power supply Ground Wait Write strobe high level data Write strobe low level data Crystal for main clock Crystal for subclock Port 7 Port 8 Port 9 Port 10 Port 11 Read Regulator control Reset Real-time output port RTP trigger Read/write status Receive data Serial clock Serial clock Serial data Serial input Serial output
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1.5.5 Function blocks (V850/SB2 (B and H versions)) (1) Internal block diagram
ROM NMI INTP0 to INTP6 INTC Note 1 Timer/counter 16-bit timer: TM0, TM1 8-bit timer: TM2 to TM7 SIO SI0/SDA0 SCK0/SCL0Note 3 SO2 SI2/SDA1Note 3 SCK2/SCL1Note 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7
Note 3
CPU PC 32-bit barrel shifter ROM correction Multiplier 16 x1632 BCU
ALU Instruction queue
HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W /WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
TI00,TI01, TI10,TI11 TO0,TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5
RAM
System register
General-purpose registers 32 bits x 32
Note 2
SO0
CSI0/I2C0 Note 4 CSI2/I2C1 Note 4
CSI1/UART0 Ports RTP CSI3/UART1 CG Variable length CSI4 P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 A/D converter CLKOUT X1 X2 XT1 XT2 RESET
Key return
RTP0 to RTP7 RTPTRG
Note 5
AVDD AVREF AVSS ANI0 to ANI11 ADTRG Regulator
DMAC: 6 ch
VDD
REGC
Watch timer Watchdog timer IETX IERX IEBus
VSS BVDD BVSS EVDD EVSS VPPNote 6 ICNote 7
Notes 1.
2.
3. 4. 5. 6. 7.
128 K (mask ROM) PD703034B, 703034BY: 256 K (mask ROM) PD703035B, 703035BY: 384 K (mask ROM) PD703036H, 703036HY: 512 K (mask ROM) PD703037H, 703037HY: PD70F3035B, 70F3035BY: 256 K (flash memory) PD70F3036H, 70F3036HY: 384 K (flash memory) PD70F3037H, 70F3037HY: 512 K (flash memory) 8 KB PD703034B, 703034BY PD703035B, 703035BY, 70F3035B, 70F3035BY: 16 KB PD703036H, 703036HY, 703037H, 703037HY,: 24 KB 70F3036H, 70F3036HY, 70F3037H, 70F3037HY SDA0, SDA1, SCL0, SCL1 pins are available only in the PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, and 70F3037HY 2 I C functions is available only in the PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, and 70F3037HY B versions: 3.0 V, H versions: 3.3 V PD70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY
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(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. prefetched instruction code is stored in an instruction queue. (c) ROM This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H. The ROM capacity varies depending on the product. The ROM capacity of each product is shown below. The
PD703034B, 703034BY: PD703035B, 703035BY: PD70F3035B, 70F3035BY: PD703036H, 703036HY: PD70F3036H, 70F3036HY: PD703037H, 703037HY: PD70F3037H, 70F3037HY:
128 KB (mask ROM) 256 KB (mask ROM) 256 KB (flash memory) 384 KB (mask ROM) 384 KB (flash memory) 512 KB (mask ROM) 512 KB (flash memory)
ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM The RAM capacity and mapping addresses vary depending on the product. The RAM capacity of each product is shown below.
PD703034B, 703034BY: PD703036H, 703036HY, 70F3036H, 70F3036HY,
703037H, 703037HY, 70F3037H, 70F3037HY:
8 KB (mapping starts at FFFFD000H)
PD703035B, 703035BY, 70F3035B, 70F3035BY: 16 KB (mapping starts at FFFFB000H)
24 KB (mapping starts at FFFF9000H)
RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources.
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(f) Clock generator (CG) The clock generator includes two types of oscillators; each for main clock (fXX) and for subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (g) Timer/counter A two-channel 16-bit timer/event counter, a four-channel 8-bit timer/event counter, and a two-channel 8bit interval timer are equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) Watch timer This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz subclock or the main clock). At the same time, the watch timer can be used as an interval timer for the main clock. (i) Watchdog timer A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (j) Serial interface (SIO) The V850/SB2 includes three kinds of serial interfaces: asynchronous serial interfaces (UART0, UART1), clocked serial interfaces (CSI0 to CSI3), and an 8-/16-bit variable-length serial interface (CSI4). These plus the I C bus interfaces (I C0, I C1) comprise five channels.
2 2 2
Two of these channels are
2
switchable between the UART and CSI and another two switchable between CSI and I C. For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins. For I C0 and I C1, data is transferred via the SDA0, SDA1, SCL0, and SCL1 pins. I C0 and I C1 are equipped only in the PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY,
2 2 2 2
70F3036HY, and 70F3037HY. For UART and CSI4, a dedicated baud rate generator is equipped. (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion uses the successive approximation method. (l) DMA controller A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
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(m) Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It can also be used for 4-bit x 2 channels. (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 I/O 8-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 6-bit I/O 8-bit input 4-bit input 7-bit I/O 8-bit I/O External bus interface control signal I/O Real-time output port, external address bus, key return input, IEBus data I/O Wait control, external address bus External address bus A/D converter analog input Port Function Generalpurpose port Control Function NMI, external interrupt, A/D converter trigger, RTP trigger Serial interface Serial interface, timer I/O Timer I/O, external address bus, serial interface External address/data bus
Port 11
4-bit I/O
(o) IEBus controller The IEBus controller is a small-scale digital data transfer system aiming at data transfer among units. The IEBus controller is incorporated only in the V850/SB2.
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2.1 List of Pin Functions
The names and functions of the pins of the V850/SB1 and V850/SB2 are described below divided into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: AVDD, BVDD, and EVDD. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies
Power Supply AVDD Port 7, port 8 Corresponding Pins Usable Voltage Range When using A/D converter: 4.5 V AVDD 5.5 V When not using A/D converter: 3.5 V AVDD 5.5 V 3.0 V BVDD 5.5 V 3.0 V EVDD 5.5 V
BVDD EVDD
Port 4, port 5, port 6, port 9, CLKOUT Port 0, port 1, port 2, port 3, port 10, port 11, RESET
Caution The electrical specifications in the case of 3.0 V to up to 4.0 V are different from those for 4.0 to 5.5 V. Differences in pins between the V850/SB1 and V850/SB2 are shown below. Table 2-2. Differences in Pins Between V850/SB1 and V850/SB2
Pin
PD703031A, PD703032A, PD703033A, PD703030B, PD703031B, PD703032B, PD703033B
V850/SB1
PD70F3032A, PD703031AY, PD70F3032AY, PD703034A, PD70F3033A, PD703032AY, PD70F3033AY, PD703035A, PD70F3030B, PD703033AY, PD70F3030BY, PD703037A, PD70F3032B, PD703030BY, PD70F3032BY, PD703034B, PD70F3033B PD703031BY, PD70F3033BY PD703035B, PD703032BY, PD703033BY PD703036H, PD703037H
V850/SB2
PD70F3035A, PD703034AY, PD70F3035AY, PD70F3037A, PD703035AY, PD70F3037AY, PD70F3035B, PD703037AY, PD70F3035BY, PD70F3036H, PD703034BY, PD70F3036HY, PD70F3037H PD703035BY, PD70F3037HY PD703036HY, PD703037HY
IC VPP SDA0, SDA1 SCL0, SCL1 IERX IETX
Available None None
None Available
Available None
None Available
Available None None
None Available
Available None
None Available
Available
Available
None
Available
None
Available
None None
Available Available
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(1) Port pins (1/3)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 I/O Yes Port 2 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 1 6-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL Yes Function Port 0 8-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3
Remark
PULL: On-chip pull-up resistor
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(2/3)
Pin Name P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 I/O No Port 6 6-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL Yes Function Port 3 8-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21
Remark
PULL: On-chip pull-up resistor
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(3/3)
Pin Name P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P90 P91 P92 P93 P94 P95 P96 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 I/O Yes Port 11 4-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 10 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 9 7-bit I/O port Input/output mode can be specified in 1-bit units. Input No Port 8 4-bit input port I/O Input PULL No Port 7 8-bit input port Function Alternate Function ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4/IERX RTP5/A10/KR5/IETX RTP6/A11/KR6 RTP7/A12/KR7 A1/WAIT A2 A3 A4
Remark
PULL: On-chip pull-up resistor
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(2) Non-port pins (1/3)
Pin Name A1 A2 to A4 A5 to A8 I/O Output PULL Yes Function Lower address bus used for external memory expansion Alternate Function P110/WAIT P111 to P113 P100/RTP0/KR0 to P103/RTP3/KR3 P104/RTP4/KR4/IERX P105/RTP5/KR5/IETX P106/RTP6/KR6 to P107/RTP7/KR7 P34/TO0/SCK4 P35/TO1 P36/TI4/TO4 Output I/O No No Higher address bus used for external memory expansion 16-bit multiplexed address/data bus used for external memory expansion A/D converter external trigger input Analog input to A/D converter P60 to P65 P40 to P47 P50 to P57 P05/INTP4 P70 to P77 P80 to P83 Serial clock input for UART0 and UART1 P15/SCK1 P25/SCK3 Output - Input - - - Output Output - - Output Input Input Output Input Yes No - - - - - - No - - No No Yes External address strobe signal output Positive power supply for A/D converter and alternate-function port Reference voltage input for A/D converter Ground potential for A/D converter and alternate-function port Positive power supply for bus interface and alternate-function port Ground potential for bus interface and alternate-function port Internal system clock output External data strobe signal output Power supply for I/O port and alternate-function pin (except for bus interface) Ground potential for I/O port and alternate-function pin (except for bus interface) Bus hold acknowledge output Bus hold request input IEBus data input (V850/SB2 only) IEBus data output (V850/SB2 only) External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination) P95 P96 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P01 to P04 P05/ADTRG P06/RTPTRG P93/RD - - P94 - - - - - -
A9 A10 A11, A12
A13 A14 A15 A16 to A21 AD0 to AD7 AD8 to AD15 ADTRG ANI0 to ANI7 ANI8 to ANI11 ASCK0 ASCK1 ASTB AVDD AVREF AVSS BVDD BVSS CLKOUT DSTB EVDD Input Input Input Input Yes No No Yes
EVSS
HLDAK HLDRQ IERX IETX INTP0 to INTP3 INTP4 INTP5
Remark
PULL: On-chip pull-up resistor
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Pin Name INTP6 I/O Input PULL Yes Function External interrupt request input (digital noise elimination for remote control) Key return input Alternate Function P07
KR0 to KR3
P100/A5/RTP0 to P103/A8/RTP3 P104/A9/RTP4/IERX P105/A10/RTP5/IETX P106/A11/RTP6 to P107/A12/RTP7
KR4 KR5 KR6, KR7
LBEN IC NMI RD REGC RESET RTP0 to RTP3
Output - Input Output - Input Output
No - Yes No - - Yes
External data bus's lower byte enable signal output Internally connected (mask ROM versions only) Non-maskable interrupt request input (analog noise elimination) Read strobe signal output Capacitor connection for regulator output stabilization System reset input Real-time output port
P90/WRL - P00 P93/DSTB - - P100/A5/KR0 to P103/A8/KR3 P104/A9/KR4/IERX P105/A10/KR5/IETX P106/A11/KR6, P107/A12/KR7
RTP4 RTP5 RTP6, RTP7
RTPTRG R/W RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 SCK4 SCL0 SCL1 SDA0 SDA1 SI0 SI1 SI2 SI3 SI4 SO0
Input Output Input
Yes No Yes
RTP external trigger input External read/write status output Serial receive data input for UART0 and UART1
P06/INTP5 P92/WRH P13/SI1 P23/SI3
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI3
P12/SCL0 P15/ASCK0 P22/SCL1 P25/ASCK1
Serial clock I/O for variable-length CSI4 (3-wire type) I/O Yes Serial clock I/O for I2C0 and I2C1 (Y versions (products with onchip I2C) only) Serial transmit/receive data I/O for I C0 and I C1 (Y versions (products with on-chip I 2 C) only) Serial receive data input (3-wire type) for CSI0 to CSI3
2 2
P34/TO0/A13 P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0 P13/RXD0 P20/SDA1 P23/RXD1
I/O
Yes
Input
Yes
Serial receive data input (3-wire type) for variable-length CSI4 Output Yes Serial transmit data output (3-wire type) for CSI0 to CSI3
P32/TI10 P11
Remark
PULL: On-chip pull-up resistor
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Pin Name SO1 SO2 SO3 SO4 TI00 Input Yes Serial transmit data output for variable-length CSI4 (3-wire type) Shared as external capture trigger input and external count clock input for TM0 External capture trigger input for TM0 Shared as external capture trigger input and external count clock input for TM1 External capture trigger input for TM1 External count clock input for TM2 External count clock input for TM3 Input Yes External count clock input for TM4 External count clock input for TM5 Output Yes Pulse signal output for TM0, TM1 I/O Output PULL Yes Function Serial transmit data output (3-wire type) for CSI0 to CSI3 Alternate Function P14/TXD0 P21 P24/TXD1 P33/TI11 P30
TI01 TI10
P31 P32/SI4
TI11 TI2 TI3 TI4 TI5 TO0, TO1
P33/SO4 P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5 P34/A13/SCK4/P35/ A14 P26/TI2 P27/TI3 P36/TI4/A15 P37/TI5 P14/SO1 P24/SO3
TO2 TO3 TO4 TO5 TXD0 TXD1 UBEN VDD VPP Output - - - Input Output No - - - Yes No Output Yes
Pulse signal output for TM2 Pulse signal output for TM3 Pulse signal output for TM4 Pulse signal output for TM5 Serial transmit data output for UART0 and UART1
Higher byte enable signal output for external data bus Positive power supply pin High-voltage apply pin for program write/verify (flash memory versions only) GND potential Control signal input for inserting wait in bus cycle Higher byte write strobe signal output for external data bus Lower byte write strobe signal output for external data bus
P91 - - - P110/A1 P92/R/W P90/LBEN - -
VSS WAIT WRH WRL X1 X2 XT1 XT2
Input - Input -
No
Resonator connection for main clock
No
Resonator connection for subclock
- -
Remark PULL: On-chip pull-up resistor
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2.2 Pin States
The operating states of various pins are described below with reference to their operating modes. Table 2-3. Operating States of Pins in Each Operating Mode
Operating State Pin AD0 to AD15 A1 to A15 A16 to A21 LBEN, UBEN R/W DSTB, WRL, WRH, RD ASTB HLDRQ HLDAK WAIT CLKOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z -- Hi-Z -- Hi-Z ResetNote 1 HALT Mode/ Idle State Hi-Z Held Held Held H H H Operating Operating -- Operating
Note 4
IDLE Mode/ STOP Mode Hi-Z Held Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z -- Hi-Z -- L
Bus Hold
Bus Cycle InactiveNote 2 Hi-Z HeldNote 3 HeldNote 3 HeldNote 3 H H H Operating Operating --
Hi-Z Held Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating L -- Operating
Note 4
OperatingNote 4
Notes 1. 2. 3.
Pins (except the CLKOUT pin) are used as port pins (input mode) after reset. The bus cycle inactivation timing occurs when the internal memory area is specified by the program counter (PC) in the external expansion mode. * When the external memory area has not been accessed even once after reset is released and the external expansion mode is set: Undefined * When the bus cycle is inactivated after access to the external memory area, or when the external memory area has not been accessed even once after the external expansion mode is released and set again: The state of the external bus cycle when the external memory area accessed last is held.
4. Remark
Low level (L) when in clock output inhibit mode Hi-Z: High impedance Held: State is held during preset external bus cycle L: H: -: Low-level output High-level output Input without sampling sampled (not acknowledged)
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2.3 Description of Pin Functions
(1) P00 to P07 (Port 0) *** 3-state I/O P00 to P07 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P00 to P07 can also function as an NMI input, external interrupt request inputs, external trigger for the A/D converter, and external trigger for the real-time output port. The valid edges of the NMI and INTP0 to INTP6 pins are specified by the EGP0 and EGN0 registers. (a) Port function P00 to P07 can be set to input or output in 1-bit units using the port 0 mode register (PM0). (b) Alternate functions (i) NMI (Non-maskable interrupt request) *** input This is a non-maskable interrupt request signal input pin. (ii) INTP0 to INTP6 (Interrupt request from peripherals) *** input These are external interrupt request input pins. (iii) ADTRG (A/D trigger input) *** input This is the A/D converter's external trigger input pin. This pin is controlled by A/D converter mode register 1 (ADM1). (iv) RTPTRG (Real-time output port trigger input) *** input This is the real-time output port's external trigger input pin. This pin is controlled by the real-time output port control register (RTPC).
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(2) P10 to P15 (Port 1) *** 3-state I/O P10 to P15 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P10 to P15 can also function as input or output pins for the serial interface. P10 to P12, P14, and P15 can be selected as normal output or N-ch open-drain output. (a) Port function P10 to P15 can be set to input or output in 1-bit units using the port 1 mode register (PM1). (b) Alternate functions (i) SI0, SI1 (Serial input 0, 1) *** input These are the serial receive data input pins of CSI0 and CSI1. (ii) SO0, SO1 (Serial output 0, 1) *** output These are the serial transmit data output pins of CSI0 and CSI1. (iii) SCK0, SCK1 (Serial clock 0, 1) *** 3-state I/O These are the serial clock I/O pins for CSI0 and CSI1. (iv) SDA0 (Serial data 0) *** I/O This is the serial transmit/receive data I/O pin of I C0 (Y versions (products with on-chip I C) only). (v) SCL0 (Serial clock 0) *** I/O This is the serial clock I/O pin for I C0 (Y versions (products with on-chip I C) only). (vi) RXD0 (Receive data 0) *** input This is the serial receive data input pin of UART0. (vii) TXD0 (Transmit data 0) *** output This is the serial transmit data output pin of UART0. (viii) ASCK0 (Asynchronous serial clock 0) *** input This is the serial baud rate clock input pin of UART0.
2 2 2 2
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(3) P20 to P27 (Port 2) *** 3-state I/O P20 to P27 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P20 to P27 can also function as input or output pins for the serial interface, and input or output pins for the timer/counter. P20 to P22, P24, and P25 can be selected as normal output or N-ch open-drain output. (a) Port function P20 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2). (b) Alternate functions (i) SI2, SI3 (Serial input 2, 3) *** input These are the serial receive data input pins of CSI2 and CSI3. (ii) SO2, SO3 (Serial output 2, 3) *** output These are the serial transmit data output pins of CSI2 and CSI3. (iii) SCK2, SCK3 (Serial clock 2, 3) *** 3-state I/O These are the serial clock I/O pins of CSI2 and CSI3. (iv) SDA1 (Serial data 1) ... I/O This is the serial transmit/receive data I/O pin of I C1 (Y versions (products with on-chip I C) only). (v) SCL1 (Serial clock) ... I/O This is the serial clock I/O pin of I C1 (Y versions (products with I C) only). (vi) RXD1 (Receive data 1) ... input This is the serial receive data input pin of UART1. (vii) TXD1 (Transmit data 1) ... output This is the serial transmit data output pin of UART1. (viii) ASCK1 (Asynchronous serial clock 1) ... input This is the serial baud rate clock input pin of UART1. (ix) TI2, TI3 (Timer input 2, 3) ... input These are the external count clock input pins of timer 2 and timer 3. (x) TO2, TO3 (Timer output 2, 3) ... output These are the pulse signal output pins of timer 2 and timer 3.
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(4) P30 to P37 (Port 3) *** 3-state I/O P30 to P37 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P30 to P37 can also function as input or output pins for the timer/counter, an address bus (A13 to A15) when memory is expanded externally, and serial interface I/O. P33 and P34 can be selected as normal output or N-ch open-drain output. (a) Port function P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3). (b) Alternate functions (i) TI00, TI01, TI10, TI11, TI4, TI5 (Timer input 00, 01, 10, 11, 4, 5) *** input These are the external count clock input pins of timer 0, timer 1, timer 4, and timer 5. (ii) TO0, TO1, TO4, TO5 (Timer output 0, 1, 4, 5) *** output These are the pulse signal output pins of timer 0, timer 1, timer 4, and timer 5. (iii) A13 to A15 (Address bus 13 to 15) *** output These comprise an address bus that is used for external access. These pins operate as the A13 to A15 bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle to inactive, the previous bus cycle's address is retained. (iv) SI4 (Serial input 4) *** input This is the serial receive data input pin of CSI4. (v) SO4 (Serial output 4) *** output This is the serial transmit data output pin of CSI4. (vi) SCK4 (Serial clock 4) *** 3-state I/O This is the I/O pin of the CSI4 serial clock.
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(5) P40 to P47 (Port 4) *** 3-state I/O P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units. P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded externally. The I/O signal level uses the bus interface power supply pins BVDD and BVSS as a reference. (a) Port function P40 to P47 can be set to input or output in 1-bit units using the port 4 mode register (PM4). (b) Alternate functions (External expansion function) P40 to P47 can be set as AD0 to AD7 using the memory expansion mode register (MM). (i) AD0 to AD7 (Address/data bus 0 to 7) *** 3-state I/O These comprise a multiplexed address/data bus that is used for external access. At the address timing (T1 state), these pins operate as AD0 to AD7 (22-bit address) output pins. At the data timing (T2, TW, T3), they operate as the lower 8-bit I/O bus pins for 16-bit data. The output changes in synchronization with the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle to inactive, these pins go into a high-impedance state. (6) P50 to P57 (Port 5) *** 3-state I/O P50 to P57 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P50 to P57 can also function as I/O port pins and as a time division address/data buses (AD8 to AD15) when memory is expanded externally. The I/O signal level uses the bus interface power supply pins BVDD and BVSS as reference. (a) Port function P50 to P57 can be set to input or output in 1-bit units using the port 5 mode register (PM5). (b) Alternate functions (External expansion function) P50 to P57 can be set as AD8 to AD15 using the memory expansion mode register (MM). (i) AD8 to AD15 (Address/data bus 8 to 15) *** 3-state I/O These comprise a multiplexed address/data bus that is used for external access. At the address timing (T1 state), these pins operate as AD8 to AD15 (22-bit address) output pins. At the data timing (T2, TW, T3), they operate as the higher 8-bit I/O bus pins for 16-bit data. sets the bus cycle to inactive, these pins go into a high-impedance state. The output changes in synchronization with the rising edge of the clock in each state within the bus cycle. When the timing
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(7) P60 to P65 (Port 6) *** 3-state I/O P60 to P65 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P60 to P65 can also function as an address bus (A16 to A21) when memory is expanded externally. When the port 6 is accessed in 8-bit units, the higher 2 bits of port 6 are ignored when they are written to and 00 is read when they are read. The I/O signal level uses the bus interface power supply pins BVDD and BVSS as reference. (a) Port function P60 to P65 can be set to input or output in 1-bit units using the port 6 mode register (PM6). (b) Alternate functions (External expansion function) P60 to P65 can be set as A16 to A21 using the memory expansion mode register (MM). (i) A16 to A21 (Address bus 16 to 21) *** output These comprise an address bus that is used for external access. These pins operate as the higher 6bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle to inactive, the previous bus cycle's address is retained. (8) P70 to P77 (Port 7), P80 to P83 (Port 8) *** input P70 to P77 constitute an 8-bit input-only port in which all the pins are fixed to input mode. P80 to P83 constitute a 4-bit input-only port in which all the pins are fixed to input. P70 to P77 and P80 to P83 can also function as analog input pins for the A/D converter. (a) Port function P70 to P77 and P80 to P83 are input-only pins. (b) Alternate functions P70 to P77 also function as ANI0 to ANI7 and P80 to P83 also function as ANI8 to ANI11. (i) ANI0 to ANI11 (Analog input 0 to 11) *** input These are analog input pins for the A/D converter. Connect a capacitor between these pins and AVSS to prevent noise-related operation faults. Also, do not apply voltage that is outside the range for AVSS and AVREF to pins that are being used as inputs for the A/D converter. If it is possible for noise above the AVREF range or below the AVSS to enter, clamp these pins using a diode that has a small VF value.
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(9) P90 to P96 (Port 9) *** 3-state I/O P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units. P90 to P96 can also function as control signal output pins and bus hold control signal output pins when memory is expanded externally. During 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a "0" during a read operation. The I/O signal level uses the bus interface power supply pins BVDD and BVSS as a reference. (a) Port function P90 to P96 can be set to input or output in 1-bit units using the port 9 mode register (PM9). (b) Alternate functions (External expansion function) P90 to P96 can be set to operate as control signal outputs for external memory expansion using the memory expansion mode register (MM). (i) LBEN (Lower byte enable) *** output This is a lower byte enable signal output pin for the external 16-bit data bus. During byte access of odd-numbered addresses, these pins are set as inactive (high level). the bus cycle as inactive, the previous bus cycle's address is retained. (ii) UBEN (Upper byte enable) *** output This is an upper byte enable signal output pin for the external 16-bit data bus. During byte access of even-numbered addresses, these pins are set as inactive (high level). the bus cycle as inactive, the previous bus cycle's address is retained.
Access Word access Halfword access Byte access Even-numbered address Odd-numbered address UBEN 0 0 1 0 LBEN 0 0 0 1 AD0 0 0 0 1
The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
(iii) R/W (Read/write status) *** output This is an output pin for the status signal pin that indicates whether the bus cycle is a read cycle or write cycle during external access. High level is set during a read cycle and low level is set during a write cycle. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. High level is set when the timing sets the bus cycle as inactive. (iv) DSTB (Data strobe) *** output This is an output pin for the external data bus's access strobe signal. Output becomes active (low level) during the T2 and TW states of the bus cycle. Output becomes inactive (high level) when the timing sets the bus cycle as inactive.
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(v) ASTB (Address strobe) *** output This is an output pin for the external address bus's latch strobe signal. Output becomes active (low level) in synchronization with the falling edge of the clock during the T1 state of the bus cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the T3 state of the bus cycle. Output becomes inactive when the timing sets the bus cycle as inactive. (vi) HLDAK (Hold acknowledge) *** output This is an output pin for the acknowledge signal that indicates high impedance status for the address bus, data bus, and control bus when the V850/SB1 and V850/SB2 receive a bus hold request. The address bus, data bus, and control bus are set to high impedance status when this signal is active. (vii) HLDRQ (Hold request) *** input This is an input pin by which an external device requests the V850/SB1 and V850/SB2 to release the address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this pin is active, the address bus, data bus, and control bus are set to high impedance status. This occurs either when the V850/SB1 and V850/SB2 complete execution of the current bus cycle or immediately if no bus cycle is being executed, then the HLDAK signal is set as active and the bus is released. (viii) WRL (Write strobe low level data) *** output This is a write strobe signal output pin for the lower data in the external 16-bit data bus. Output occurs during the write cycle, similar to DSTB. (ix) WRH (Write strobe high level data) *** output This is a write strobe signal output pin for the higher data in the external 16-bit data bus. Output occurs during the write cycle, similar to DSTB. (x) RD (Read strobe) *** output This is a read strobe signal output pin for the external 16-bit data bus. Output occurs during the read cycle, similar to DSTB.
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(10) P100 to P107 (Port 10) *** 3-state I/O P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P100 to P107 can also function as a real-time output port, an address bus (A5 to A12) when memory is expanded externally, key return input, and IEBus data I/O (V850/SB2 only). P100 to P107 can be selected as normal output or N-ch open-drain output. (a) Port function P100 to P107 can be set to input or output in 1-bit units using the port 10 mode register (PM10). (b) Alternate functions (i) RTP0 to RTP7 (Real-time output port 0 to 7) *** output These pins comprise a real-time output port. (ii) A5 to A12 (Address bus 5 to 12) *** output These comprise the address bus that is used for external access. These pins operate as the A5 to A12 bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus cycle's address is retained. (iii) KR0 to KR7 (Key return 0 to 7) ... input These are key return input pins. Their operations are specified by the key return mode register (KRM). (iv) IERX (IEBus receive data) ... input This is an IEBus data input signal. This pin is only available in the V850/SB2. (v) IETX (IEBus transmit data) ... output This is an IEBus data output signal. This pin is only available in the V850/SB2.
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(11) P110 to P113 (Port 11) *** 3-state I/O P110 to P113 constitute a 4-bit I/O port that can be set to input or output in 1-bit units. P110 to P113 can also function as an address bus (A1 to A4) when memory is expanded externally, signal (WAIT) that inserts waits into the bus cycle and a control. (a) Port function P110 to P113 can be set to input or output in 1-bit units using the port 11 mode register (PM11). (b) Alternate functions (i) A1 to A4 (Address bus 1 to 4) *** output These comprise the address bus that is used for external access. These pins operate as the lower 4bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus cycle's address is retained. (ii) WAIT (Wait) *** input This is an input pin for the control signal used to insert waits into the bus cycle. This pin is sampled at the falling edge of the clock during the T2 or TW state of the bus cycle. ON/OFF switching of the wait function is performed by the port alternate function control register (PAC). Caution Because the supply voltage to the I/O buffer of the WAIT pin is EVDD, if the voltage of EVDD and that of BVDD differ, use EVDD as the voltage of the external wait signal, instead of BVDD. (12) RESET (Reset) *** input The RESET pin is an asynchronous input and inputs a signal that has a constant low level width regardless of the status of the operating clock. When this signal is input, a system reset is executed as the first priority ahead of all other operations. In addition to being used for ordinary initialization/start operations, this pin can also be used to release a standby mode (HALT, IDLE, or STOP mode). (13) REGC (Regulator control) ... input This pin is used to connect the capacitor for the regulator. (14) CLKOUT (Clock out) ... output This pin outputs the bus clock generated internally. (15) X1, X2 (Crystal) These pins are used to connect the resonator that generates the main clock. (16) XT1, XT2 (Crystal for subclock) These pins are used to connect the resonator that generates the subclock. (17) AVDD (Analog VDD) This is the analog positive power supply pin for the A/D converter or alternate-function port.
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(18) AVSS (Analog VSS) This is the ground pin for the A/D converter or alternate-function port. (19) AVREF (Analog reference voltage) ... input This is the reference voltage supply pin for the A/D converter. (20) BVDD (Power supply for bus interface) This is the positive power supply pin for the bus interface and its alternate-function ports. (21) BVSS (Ground for bus interface) This is the ground pin for the bus interface and its alternate-function ports. (22) EVDD (Power supply for port) This is the positive power supply pin for I/O ports and alternate-function pins (except for the alternate-function ports of the bus interface). (23) EVSS (Ground for port) This is the ground pin for I/O ports and alternate-function pins (except for the alternate-function ports of the bus interface). (24) VDD (Power supply) This is the positive power supply pin. All VDD pins should be connected to a positive power supply. (25) VSS (Ground) This is the ground pin. All VSS pins should be grounded. (26) VPP (Programming power supply) This is the positive power supply pin used for flash memory programming mode. This pin is used in the flash memory versions. In normal operation mode, connect directly to VSS. (27) IC (Internally connected) This is an internally connected pin used in the mask ROM versions. Be sure to connect directly to VSS.
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2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins
(1/2)
Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply EVDD 8-A Input: Recommended Connection Method
P00 P01 to P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26, P27 P30, P31 P32 P33 P34 P35 P36 P37 P40 to P47 P50 to P57 P60 to P65 P70 to P77 P80 to P83
NMI INTP0 to INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2, TI3/TO3 TI00, TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 AD0 to AD7 AD8 to AD15 A16 to A21 ANI0 to ANI7 ANI8 to ANI11
Independently connect to EVDD or EVSS via a resistor
Output: Leave open
EVDD
10-A 26 10-A 8-A 26 10-A
EVDD
10-A 26 10-A 8-A 26 10-A 8-A
EVDD
8-A
10-A
5-A 8-A
BVDD
5
Input:
Independently connect to BVDD or BVSS via a resistor
Output: Leave open
AVDD
9
Independently connect to AVDD or AVSS via a resistor
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Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply BVDD 5 Input: Recommended Connection Method
P90 P91 P92 P93 P94 P95 P96
LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ
Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P100 to P103 RTP0/A5/KR0 to RTP3/A8/KR3 P104 P105 P106, P107 RTP4/A9/KR4/IERX RTP5/A10/KR5/IETX RTP6/A11/KR6, RTP7/A12/KR7 A1/WAIT
EVDD
10-A
Input:
Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P110
EVDD
5-A
P111 to P113 A2 to A4 AVREF CLKOUT RESET X1 X2 XT1 XT2 VPP IC
Note 1
- - - - - - - - - - - - - - - -
- BVDD EVDD - - - - - - - - - - - - -
- 4 2 - - 16 16 - - - - - - - - -
Connect to AVSS via a resistor Leave open - - - Connect to VSS via a resistor Leave open Connect to VSS Connect directly to VSS - - - - - - -
Note 2
VSS AVDD AVSS BVDD BVSS EVDD EVSS
Notes 1. 2.
Flash memory versions only Mask ROM versions only
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2.5 Pin I/O Circuits
(1/2)
Type 2 Type 5-A VDD
IN
Pullup enable VDD Data P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable Input enable N-ch
Type 4 VDD Data P-ch
Type 8-A
VDD Pullup enable P-ch VDD P-ch IN/OUT
OUT Output disable
Data
N-ch
Output disable
N-ch
Push-pull output that can be set for high impedance output (both P-ch and N-ch off). Type 5 V DD Data P-ch IN/OUT Output disable Input enable N- ch VREF (threshold voltage) P-ch N- ch Type 9
+ -
Comparator
Input enable
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Type 10-A
VDD Pullup enable VDD Data P-ch IN/OUT Open drain Output disable N-ch Open drain Output disable N-ch Data P-ch Pullup enable VDD P-ch IN/OUT P-ch
Type 26
VDD
Type 16
Feedback cut-off P-ch
XT1
XT2
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The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline.
3.1 Features
* Minimum instruction execution time V850/SB1 (A version, B version): 50 ns (@20 MHz internal operation) V850/SB2 (A version, B version): 79 ns (@12.58 MHz internal operation) V850/SB2 (H version): 53 ns (@18.87 MHz internal operation) * * * * * * * * * Address space: 16 MB linear Thirty-two 32-bit general-purpose registers Internal 32-bit architecture Five-stage pipeline control Multiplication/division instructions Saturated operation instructions One-clock 32-bit shift instruction Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1
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3.2 CPU Register Set
The CPU registers of the V850/SB1 and V850/SB2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Series Architecture User's Manual Figure 3-1. CPU Register Set
Program register set
31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Element Pointer (EP) Link Pointer (LP) 31 PSW Program Status Word 0 31 ECR Exception Cause Register 0 Stack Pointer (SP) Global Pointer (GP) Text Pointer (TP) 31 FEPC FEPSW Fatal Error PC Fatal Error PSW 0 0 Zero Register Reserved for Address Register
System register set
31 EIPC EIPSW Exception/Interrupt PC Exception/Interrupt PSW 0
31 PC Program Counter
0
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3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. Also, r1, r3, r4, r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost. The contents must be restored to the registers after the registers have been used. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register. Table 3-1. Program Registers
Name r0 r1 r2 r3 r4 r5 r6 to r29 r30 r31 PC Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate Operation
Address/data variable register (when r2 is not used by the real-time OS) Stack pointer Global pointer Text pointer Address/data variable registers Element pointer Link pointer Program counter Base pointer when memory is accessed Used by compiler when calling function Holds instruction address during program execution Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text areaNote
Note
Area in which program code is mapped.
(2) Program counter (PC) This register holds the address of the instruction under execution. The lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. If a carry occurs from bit 23 to 24, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
After reset: 00000000H Symbol PC 31 Fixed to 0 24 23 Instruction address under execution 1 0 0
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3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers
No. 0 1 System Register Name EIPC EIPSW Usage Interrupt status saving registers Operation These registers save the PC and PSW when an exception or interrupt occurs. Because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. These registers save PC and PSW when NMI occurs.
2 3 4
FEPC FEPSW ECR
NMI status saving registers
Interrupt source register
If exception, maskable interrupt, or NMI occurs, this register will contain information referencing the interrupt source. The higher 16 bits of this register are called FECC, to which exception code of NMI is set. The lower 16 bits are called EICC, to which exception code of exception/interrupt is set. A program status word is a collection of flags that indicate program status (instruction execution result) and CPU status.
5
PSW
Program status word
6 to 31
Reserved
To read/write these system registers, specify a system register number indicated by the system register load/store instruction (LDSR or STSR instruction). (1) Interrupt source register (ECR)
After reset: 00000000H Symbol ECR 31 FECC 16 15 EICC 0
FECC EICC
Exception code of NMI (For exception code, refer to Table 5-1.) Exception code of exception/interrupt
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(2) Program status word (PSW) (1/2)
After reset: 00000020H 31 PSW RFU 8 7 NP 6 EP 5 4 3 2 OV 1 S 0 Z
ID SAT CY
RFU
Reserved field (fixed to 0).
NP 0 1
Non-maskable interrupt (NMI) servicing status NMI servicing not under execution. NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables multiple interrupts. For details, refer to 5.2.3 NP flag.
EP 0 1
Exception processing status Exception processing not under execution. Exception processing under execution. This flag is set (1) when an exception is generated. Interrupt requests can be acknowledged when this bit is set. For details, refer to 5.4.3 EP flag.
ID 0 1
Maskable interrupt servicing specification Maskable interrupt acknowledgment enabled (EI). Maskable interrupt acknowledgment disabled (DI). This flag is set (1) when a maskable interrupt request is acknowledged. For details, refer to 5.3.6 ID flag.
SATNote 0
Saturation detection of operation result of saturation operation instruction Not saturated. This flag is not cleared (0) if the result of saturated operation instruction execution is not saturated while this flag is set (1). To clear (0) this flag, write the PSW directly. Saturated.
1
CY 0 1
Detection of carry or borrow of operation result Carry or borrow has not occurred. Carry or borrow occurred.
OVNote 0 1
Detection of overflow during operation Overflow has not occurred. Overflow occurred.
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S
Note
Detection of operation result positive/negative The operation result was positive or 0. The operation result was negative.
0 1
Z 0 1
Detection of operation result zero The operation result was not 0. The operation result was 0.
Note The result of a saturation-processed operation is determined by the contents of the OV and S bits in the saturation operation. Simply setting (1) the OV bit will set (1) the SAT bit in a saturation operation.
Status of operation result SAT Maximum positive value exceeded Maximum negative value exceeded Positive (not exceeding the maximum) Negative (not exceeding the maximum) 1 1
Retains the value before operation
Flag status OV 1 1 0 S 0 1 0 1
Saturation-processed operation result 7FFFFFFFH 80000000H Operation result itself
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3.3 Operation Modes
The V850/SB1 and V850/SB2 have the following operation modes. (1) Normal operation mode (single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started. However, external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register (MM) by instruction. (2) Flash memory programming mode This mode is provided only in the flash memory versions. The internal flash memory is programmable or erasable when the VPP voltage is applied to the VPP pin.
VPP 0 7.8 V VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited
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3.4 Address Space
3.4.1 CPU address space The CPUs of the V850/SB1 and V850/SB2 are of 32-bit architecture and support up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear address space (program space) of up to 16 MB is supported. The CPU address space is shown below. Figure 3-2. CPU Address Space
CPU address space FFFFFFFFH
Data area (4 GB linear)
01000000H 00FFFFFFH Program area (16 MB linear)
00000000H
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3.4.2 Image The core CPU supports 4 GB of "virtual" addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits 31 to 24 of the CPU address. The image of the virtual addressing space is shown below. Because the higher 8 bits of a 32-bit CPU address are ignored and the CPU address is only seen as a 24-bit external physical address, the physical location xx000000H is equally referenced by multiple address values 00000000H, 01000000H, 02000000H, ... FE000000H, FF000000H. Figure 3-3. Image on Address Space
CPU address space FFFFFFFFH
Image
FF000000H FEFFFFFFH
Image Physical address space FE000000H FDFFFFFFH Image (Access prohibited) 02000000H 01FFFFFFH Internal ROM On-chip peripheral I/O Internal RAM xxFFFFFFH
xx000000H
Image
01000000H 00FFFFFFH
Image
00000000H
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3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address 00FFFFFFH are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. Figure 3-4. Program Space
Program space 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space (+) direction (-) direction
(2) Data space The result of operand address calculation that exceeds 32 bits is ignored. Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address FFFFFFFFH are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. Figure 3-5. Data Space
Data space FFFFFFFEH FFFFFFFFH 00000000H 00000001H Data space (+) direction (-) direction
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3.4.4 Memory map The V850/SB1 and V850/SB2 reserve areas as shown below. Figure 3-6. Memory Map
Single-chip mode xxFFFFFFH On-chip peripheral I/O area xxFFF000H xxFFEFFFH Internal RAM area xxFF8000H xxFF7FFFH Internal RAM area 28 KB On-chip peripheral I/O area 4 KB Single-chip mode (external expansion mode)
(Reserved)
External memory area
16 MB
xx100000H xx0FFFFFH On-chip flash memory/ ROM area On-chip flash memory/ ROM area 1 MB
xx000000H
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3.4.5 Area (1) Internal ROM/flash memory area An area of 1 MB maximum is reserved for the internal ROM/flash memory area. (a) V850/SB1 (PD703031A, 703031AY, 703031B, 703031BY) V850/SB2 (PD703034A, 703034AY, 703034B, 703034BY) 128 KB are available for the addresses xx000000H to xx01FFFFH. Addresses xx020000H to xx0FFFFFH are an access-prohibited area Figure 3-7. Internal ROM Area (128 KB)
xx0FFFFFH
Access-prohibited area
xx020000H xx01FFFFH xx000000H Internal ROM
(b) V850/SB1 (PD703033A, 703033AY, 70F3033A, 70F3033AY, 703033B, 703033BY, 70F3033B, 70F3033BY) V850/SB2 (PD703035A, 703035AY, 70F3035A, 70F3035AY, 703035B, 703035BY, 70F3035B, 70F3035BY) 256 KB are available for the addresses xx000000H to xx03FFFFH. Addresses xx040000H to xx0FFFFFH are an access-prohibited area Figure 3-8. Internal ROM/Flash Memory Area (256 KB)
xx0FFFFFH
Access-prohibited area
xx040000H xx03FFFFH Internal ROM/ flash memory xx000000H
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(c) V850/SB1 (PD703030B, 703030BY, 70F3030B, 70F3030BY) V850/SB2 (PD703036H, 703036HY, 70F3036H, 70F3036HY) 384 KB are available for the addresses xx000000H to xx05FFFFH. Addresses xx060000H to xx0FFFFFH are an access-prohibited area Figure 3-9. Internal ROM/Flash Memory Area (384 KB)
xx0FFFFFH
Access-prohibited area xx060000H xx05FFFFH Internal ROM/ flash memory
xx000000H
(d) V850/SB1 (PD703032A, 703032AY, 70F3032A, 70F3032AY, 703032B, 703032BY, 70F3032B, 70F3032BY) V850/SB2 (PD703037A, 703037AY, 70F3037A, 70F3037AY, 703037H, 703037HY, 70F3037H, 70F3037HY) 512 KB are available for the addresses xx000000H to xx07FFFFH. Addresses xx080000H to xx0FFFFFH are an access-prohibited area Figure 3-10. Internal ROM/Flash Memory Area (512 KB)
xx0FFFFFH Access-prohibited area xx080000H xx07FFFFH
Internal ROM/ flash memory
xx000000H
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Interrupt/exception table The V850/SB1 and V850/SB2 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is granted, execution jumps to the handler address, and the program written at that memory address is executed. corresponding addresses are shown below. Table 3-3. Interrupt/Exception Table
Start Address of Interrupt/Exception Table 00000000H 00000010H 00000020H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H Interrupt/Exception Source RESET NMI INTWDT TRAP0n (n = 0 to F) TRAP1n (n = 0 to F) ILGOP INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTWTNI INTTM00 INTTM01 INTTM10 INTTM11 INTTM2 INTTM3 INTTM4 INTTM5 Start Address of Interrupt/Exception Table 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H
2
The sources of interrupts/exceptions, and the
Interrupt/Exception Source INTTM6 INTTM7 INTIIC0Note/INTCSI0 INTSER0 INTSR0/INTCSI1 INTST0 INTCSI2 INTIIC1Note INTSER1 INTSR1/INTCSI3 INTST1 INTCSI4 INTIE1 (V850/SB2 only) INTIE2 (V850/SB2 only) INTAD INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTDMA4 INTDMA5 INTWTN INTKR
Note Available only in the Y versions (products with on-chip I C).
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(2) Internal RAM area An area of 28 KB maximum is reserved for the internal RAM area. (a) V850/SB1 (PD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) 8 KB are available for the addresses xxFFD000H to xxFFEFFFH. Addresses xxFF8000H to xxFFCFFFH are an access-prohibited area Figure 3-11. Internal RAM Area (8 KB)
xxFFEFFFH Internal RAM xxFFD000H xxFFCFFFH
Access-prohibited area
xxFF8000H
(b) V850/SB1 (PD703031A, 703031AY), V850/SB2 (PD703034A, 703034AY) 12 KB are available for the addresses xxFFC000H to xxFFEFFFH. Addresses xxFF8000H to xxFFBFFFH are an access-prohibited area Figure 3-12. Internal RAM Area (12 KB)
xxFFEFFFH Internal RAM xxFFC000H xxFFBFFFH
Access-prohibited area
xxFF8000H
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(c) V850/SB1 (PD703033A, 703033AY, 70F3033A, 70F3033AY, 703033B, 703033BY, 70F3033B, 70F3033BY) V850/SB2 (PD703035A, 703035AY, 70F3035A, 70F3035AY, 703035B, 703035BY, 70F3035B, 70F3035BY) 16 KB are available for the addresses xxFFB000H to xxFFEFFFH. Addresses xxFF8000H to xxFFAFFFH are an access-prohibited area Figure 3-13. Internal RAM Area (16 KB)
xxFFEFFFH
Internal RAM
xxFFB000H xxFFAFFFH Access-prohibited area xxFF8000H
(d) V850/SB1 (PD703030B, 703030BY, 70F3030B, 70F3030BY, 703032A, 703032AY, 70F3032A, 70F3032AY, 703032BY, 70F3032B, 70F3032BY) V850/SB2 (PD703036H, 703036HY, 70F3036H, 70F3036HY, 703037A, 703037AY, 70F3037A, 70F3037AY, 703037H, 703037HY, 70F3037H, 70F3037HY) 24 KB are available for the addresses xxFF9000H to xxFFEFFFH. Addresses xxFF8000H to xxFF8FFFH are an access-prohibited area Figure 3-14. Internal RAM Area (24 KB)
xxFFEFFFH
Internal RAM
xxFF9000H xxFF8FFFH xxFF8000H
Access-prohibited area
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(3) On-chip peripheral I/O area A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SB1 and V850/SB2 are provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH). Peripheral I/O registers associated with the operation mode specification and the state monitoring for the on-chip peripherals are all memory-mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Figure 3-15. On-Chip Peripheral I/O Area
xxFFFFFFH Image xxFFFC00H xxFFFBFFH Physical on-chip peripheral I/O Image xxFFF800H xxFFF7FFH Image Peripheral I/O 3FFH
000H
xxFFF400H xxFFF3FFH Image
xxFFF000H
Cautions 1. The least significant bit of an address is not decoded since all registers reside on an even address. If an odd address (2n + 1) in the peripheral I/O area is referenced (accessed in byte units), the register at the next lowest even address (2n) will be accessed. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined, if the access is a read operation. If a write access is made, only the data in the lower 8 bits is written to the register. 3. If a register with n address that can be accessed only in halfword units is accessed in word units, the operation is replaced with two halfword operations. The first operation (lower 16 bits) accesses to the register with n address and the second operation (higher 16 bits) accesses to the register with n + 2 address. 4. If a register with n address that can be accessed in word units is accessed with a word operation, the operation is replaced with two halfword operations. The first operation (lower 16 bits) accesses to the register with n address and the second operation (higher 16 bits) accesses to the register with n + 2 address. 5. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed.
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(4) External memory The V850/SB1 and V850/SB2 can use an area of up to 16 MB (xx100000H to xxFF7FFFH) for external memory accesses (in single-chip mode: external expansion). 64 K, 256 K, 1 M, or 4 MB of physical external memory can be allocated when the external expansion mode is specified. In the area of other than the physical external memory, the image of the physical external memory can be seen. The internal RAM area and on-chip peripheral I/O area are not subject to external memory access. Figure 3-16. External Memory Area (When Expanded to 64 K, 256 K, or 1 MB)
xxFFFFFFH On-chip peripheral I/O Internal RAM xxFF7FFFH Image Physical external memory xFFFFH
Image
External memory 00000H
Image
xx100000H
Internal ROM
xx000000H
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Figure 3-17. External Memory Area (When Expanded to 4 MB)
xxFFFFFFH On-chip peripheral I/O Internal RAM xxFF7FFFH Image xxC00000H xxBFFFFFH
Physical external memory 3FFFFFH Image External memory
xx800000H xx7FFFFFH 000000H Image
xx400000H xx3FFFFFH Image xx100000H xx0FFFFFH Internal ROM xx000000H
3.4.6 External expansion mode The V850/SB1 and V850/SB2 allow external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using the memory expansion mode register (MM). The address bus (A1 to A15) is set to multiplexed output with data bus (D1 to D15), though separate output is also available by setting the memory address output mode register (MAM) (see the User's Manual of relevant in-circuit emulator about debugging when using the separate bus). Caution Because the A1 pin and WAIT pin are alternate-function pins, the wait function by the WAIT pin cannot be used when using a separate bus (programmable wait can be used however). Similarly, a separate bus cannot be used when the wait function by the WAIT pin is being used. Because the V850/SB1 and V850/SB2 are fixed to single-chip mode in the normal operation mode, the port alternate pins become the port mode, thereby the external memory cannot be used. When the external memory is used (external expansion mode), specify the MM register by the program.
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(1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to the external memory area of up to 4 MB. However, the external device cannot be connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed). The MM register can be read/written in 8-bit or 1-bit units. However, bits 4 to 7 are fixed to 0.
After reset: 00H Symbol MM 7 0 R/W 6 0 5 0 Address: FFFFF04CH 4 0 <3> MM3 <2> MM2 <1> MM1 <0> MM0
MM3 0 1 Port mode
P95 and P96 operation modes
External expansion mode (HLDAK: P95, HLDRQ: P96)
MM2 0 0
MM1 0 1
MM0 0 1
Address space - 64 KB expansion mode
Port 4
Port 5 Port mode
Port 6
Port 9
AD0 to AD7
AD8 to AD15 A16, A17 A18, A19 A20, A21
LBEN, UBEN, R/W, DSTB, ASTB, WRL, WRH, RD
1
0
0
256 KB expansion mode
1
0
1
1 MB expansion mode
1
1
x
4 MB expansion mode
Other than above
RFU (reserved)
Caution Before switching to the external expansion mode, be sure to set P93 and P94 of Port 9 (P9) to 1. Remark For the details of the operation of each port pin, refer to 2.3 Description of Pin Functions.
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(2) Memory address output mode register (MAM) Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. The MAM register can be written in 8-bit units. If read is performed, undefined values will be read. However, bits 3 to 7 are fixed to 0.
After reset: 00H Symbol MAM 7 0 W 6 0 5 0 Address: FFFFF068H 4 0 3 0 2 MAM2 1 MAM1 0 MAM0
MAM2 0 0 0 1 1 1 1
MAM1 0 1 1 0 0 1 1
MAM0 0 0 1 0 1 0 1
Address space - 32 bytes 512 bytes 8 KB 16 KB 32 KB 64 KB
Port 11
Port 10 Port mode
Port 3
A1 to A4 A5 to A8 A9 to A12 A13 A14 A15
Caution
Debugging the memory address output mode register (MAM) an in-circuit emulator is not available. Also, setting the MAM register by software cannot switch to the separate bus. For details, refer to the relevant User's Manual of in-circuit emulator.
Remark
For details of the operation of each port, see 2.3 Description of Pin Functions.
The separate path outputs are output from P34 to P36, P100 to P107, and P110 to P113. The procedure for performing separate path output is shown below. <1> Set the Pn bit of Port m (Pm) used for separate output to 0 (m = 3, 10, 11). <2> Set the PMn bit of the port m mode register (PMm) to 0 (output mode) (m = 3, 10, 11). <3> When the port to be used for the separate path is used as an alternate-function pin for other than the separate path, turn off the function used by the alternate-function pin. <4> Set the memory address output mode register (MAM). <5> Set the memory expansion mode register (MM). Remark m = 3: n = 34 to 36
m = 10: n = 100 to 107 m = 11: n = 110 to 113
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3.4.7 Recommended use of address space The architectures of the V850/SB1 and V850/SB2 require that a register that serves as a pointer be secured for address generation in operand data accessing for data space. The address in this pointer register 32 KB can be accessed directly from instruction. However, general-purpose register used as a pointer register is limited. Therefore, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved because instructions for calculating pointer addresses are not required. To enhance the efficiency of using the pointer in connection with the memory maps of the V850/SB1 and V850/SB2, the following points are recommended: (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Therefore, a continuous 16 MB space, starting from address 00000000H, unconditionally corresponds to the memory map of the program space. (2) Data space For the efficient use of resources to be performed through the wrap-around feature of the data space, the continuous 8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space. With the V850/SB1 or V850/SB2, 16 MB physical address space is seen as 256 images in the 4 GB CPU address space. The highest bit (bit 23) of this 24-bit address is assigned as address sign-extended to 32 bits. (a) Application of wrap-around For example, when R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, an addressing range of 00000000H 32 KB can be referenced with the sign-extended, 16-bit displacement value. All resources including on-chip hardware can be accessed with one pointer. The zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. Figure 3-18. Application of Wrap-Around
0001FFFFH 00007FFFH Internal ROM area (R =) 00000000H FFFFF000H On-chip peripheral I/O area 4 KB 32 KB
Internal RAM area FFFF8000H
28 KB
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Figure 3-19. Recommended Memory Map (Flash Memory Version)
Program space FFFFFFFFH FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH Data space On-chip peripheral I/O
Internal RAM FFFF8000H FFFF7FFFH External memory FF800000H FF7FFFFFH
On-chip peripheral I/O
xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH
Internal RAM xxFFB000H On-chip peripheral I/O Note
Access-prohibited xxFFAFFFH area xxFF8000H
01000000H 00FFFFFFH
External memory
xxFF7FFFH xx800000H xx7FFFFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx000000H
00FFF000H 00FFEFFFH Internal RAM 16 MB 00FF8000H 00FF7FFFH Internal ROM
00800000H 007FFFFFH 00100000H 000FFFFFH 00040000H 0003FFFFH 00000000H
External memory External memory
8 MB
Internal ROM
Internal ROM
Note This area cannot be used as a program area. Remarks 1. The arrows indicate the recommended area. 2. This is a recommended memory map for V850/SB1 (PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY), V850/SB2 (PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY).
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3.4.8 Peripheral I/O registers (1/7)
Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF000H FFFFF002H FFFFF004H FFFFF006H FFFFF008H FFFFF00AH FFFFF00CH FFFFF00EH FFFFF010H FFFFF012H FFFFF014H FFFFF016H FFFFF020H FFFFF022H FFFFF024H FFFFF026H FFFFF028H FFFFF02AH FFFFF02CH FFFFF032H FFFFF034H FFFFF036H FFFFF040H FFFFF04CH FFFFF060H FFFFF062H FFFFF064H FFFFF068H FFFFF070H FFFFF074H FFFFF078H FFFFF080H FFFFF082H FFFFF084H FFFFF086H FFFFF094H Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 0 mode register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 9 mode register Port 10 mode register Port 11 mode register Port alternate function control register Memory expansion mode register Data wait control register Bus cycle control register System control register Memory address output mode register Power save control register Processor clock control register System status register Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 10 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM9 PM10 PM11 PAC MM DWC BCC SYC MAM PSC PCC SYS PU0 PU1 PU2 PU3 PU10 W R/W

After Reset
8 Bits 16 Bits 32 Bits

R/W

00HNote
R

Undefined
R/W

00HNote
FFH 3FH FFH
3FH 7FH FFH 1FH 00H
FFFFH AAAAH 00H
C0H 03H 00H
Note Resetting initializes registers to input mode and the pin level is read. Output latches are initialized to 00H.
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF096H FFFFF0A2H FFFFF0A4H FFFFF0A6H FFFFF0B4H FFFFF0C0H FFFFF0C2H FFFFF100H FFFFF102H FFFFF104H FFFFF106H FFFFF108H FFFFF10AH FFFFF10CH FFFFF10EH FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH Pull-up resistor option register 11 Port 1 function register Port 2 function register Port 3 function register Port 10 function register Rising edge specification register 0 Falling edge specification register 0 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register
Note
After Reset
8 Bits 16 Bits 32 Bits

PU11 PF1 PF2 PF3 PF10 EGP0 EGN0 WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 WTNIIC TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 TMIC6 TMIC7 CSIC0 SERIC0 CSIC1 STIC0 CSIC2 IICIC1 SERIC1 CSIC3 STIC1
2
R/W

00H
47H
Interrupt control register Interrupt control register Interrupt control register
Note Available only in the Y versions (products with on-chip I C).
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF166H FFFFF170H FFFFF180H FFFFF182H FFFFF184H FFFFF186H FFFFF190H FFFFF192H FFFFF194H FFFFF196H FFFFF1A0H FFFFF1A2H FFFFF1A4H FFFFF1A6H FFFFF1B0H FFFFF1B2H FFFFF1B4H FFFFF1B6H FFFFF1C0H FFFFF1C2H FFFFF1C4H FFFFF1C6H FFFFF1D0H FFFFF1D2H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register In-service priority register Command register DMA peripheral I/O address register 0 DMA internal RAM address register 0 DMA byte count register 0 DMA channel control register 0 DMA peripheral I/O address register 1 DMA internal RAM address register 1 DMA byte count register 1 DMA channel control register 1 DMA peripheral I/O address register 2 DMA internal RAM address register 2 DMA byte count register 2 DMA channel control register 2 DMA peripheral I/O address register 3 DMA internal RAM address register 3 DMA byte count register 3 DMA channel control register 3 DMA peripheral I/O address register 4 DMA internal RAM address register 4 DMA byte count register 4 DMA channel control register 4 DMA peripheral I/O address register 5 DMA internal RAM address register 5
Note
After Reset
8 Bits 16 Bits 32 Bits

CSIC4 IEBIC1 IEBIC2 ADIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 DMAIC4 DMAIC5 WTNIC KRIC ISPR PRCMD DIOA0 DRA0 DBC0 DCHC0 DIOA1 DRA1 DBC1 DCHC1 DIOA2 DRA2 DBC2 DCHC2 DIOA3 DRA3 DBC3 DCHC3 DIOA4 DRA4 DBC4 DCHC4 DIOA5 DRA5 R W R/W

47H
Note
00H Undefined

00H Undefined

00H Undefined

00H Undefined

00H Undefined

00H Undefined
Note Available only in the V850/SB2.
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF1D4H FFFFF1D6H FFFFF200H FFFFF202H FFFFF204H FFFFF206H FFFFF208H FFFFF20AH FFFFF20CH FFFFF20EH FFFFF210H FFFFF212H FFFFF214H FFFFF216H FFFFF218H FFFFF21AH FFFFF21CH FFFFF21EH FFFFF240H FFFFF242H FFFFF244H FFFFF246H FFFFF24AH DMA byte count register 5 DMA channel control register 5 16-bit timer register 0 16-bit capture/compare register 00 16-bit capture/compare register 01 Prescaler mode register 00 16-bit timer mode control register 0 Capture/compare control register 0 Timer output control register 0 Prescaler mode register 01 16-bit timer register 1 16-bit capture/compare register 10 16-bit capture/compare register 11 Prescaler mode register 10 16-bit timer mode control register 1 Capture/compare control register 1 Timer output control register 1 Prescaler mode register 11 8-bit counter 2 8-bit compare register 2 Timer clock selection register 20 8-bit timer mode control register 2 16-bit counter 23 (during cascade connection only) 16-bit compare register 23 (during cascade connection only) Timer clock selection register 21 8-bit counter 3 8-bit compare register 3 Timer clock selection register 30 8-bit timer mode control register 3 Timer clock selection register 31 8-bit counter 4 8-bit compare register 4 Timer clock selection register 40 8-bit timer mode control register 4 DBC5 DCHC5 TM0 CR00 CR01 PRM00 TMC0 CRC0 TOC0 PRM01 TM1 CR10 CR11 PRM10 TMC1 CRC1 TOC1 PRM11 TM2 CR20 TCL20 TMC2 TM23 R
After Reset
8 Bits 16 Bits 32 Bits
R/W
Undefined 00H

R Note Note R/W

0000H
00H
R Note Note R/W

0000H
00H
R R/W

00H
04H 0000H
FFFFF24CH
CR23
R/W
FFFFF24EH FFFFF250H FFFFF252H FFFFF254H FFFFF256H FFFFF25EH FFFFF260H FFFFF262H FFFFF264H FFFFF266H
TCL21 TM3 CR30 TCL30 TMC3 TCL31 TM4 CR40 TCL40 TMC4

00H
R R/W

04H 00H
R R/W

04H
Note In compare mode: R/W In capture mode: R
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF26AH 16-bit counter 45 (during cascade connection only) 16-bit compare register 45 (during cascade connection only) Timer clock selection register 41 8-bit counter 5 8-bit compare register 5 Timer clock selection register 50 8-bit timer mode control register 5 Timer clock selection register 51 8-bit counter 6 8-bit compare register 6 Timer clock selection register 60 8-bit timer mode control register 6 16-bit counter 67 (during cascade connection only) 16-bit compare register 67 (during cascade connection only) Timer clock selection register 61 8-bit counter 7 8-bit compare register 7 Timer clock selection register 70 8-bit timer mode control register 7 Timer clock selection register 71 Serial I/O shift register 0 Serial operation mode register 0 Serial clock selection register 0 Serial I/O shift register 1 Serial operation mode register 1 Serial clock selection register 1 Serial I/O shift register 2 Serial operation mode register 2 Serial clock selection register 2 Serial I/O shift register 3 Serial operation mode register 3 Serial clock selection register 3 Variable-length serial I/O shift register 4 TM45 R 8 Bits 16 Bits 32 Bits
After Reset
0000H
FFFFF26CH
CR45
R/W
FFFFF26EH FFFFF270H FFFFF272H FFFFF274H FFFFF276H FFFFF27EH FFFFF280H FFFFF282H FFFFF284H FFFFF286H FFFFF28AH
TCL41 TM5 CR50 TCL50 TMC5 TCL51 TM6 CR60 TCL60 TMC6 TM67 R

00H
R R/W

04H 00H
R R/W

04H 0000H
FFFFF28CH
CR67
R/W
FFFFF28EH FFFFF290H FFFFF292H FFFFF294H FFFFF296H FFFFF29EH FFFFF2A0H FFFFF2A2H FFFFF2A4H FFFFF2B0H FFFFF2B2H FFFFF2B4H FFFFF2C0H FFFFF2C2H FFFFF2C4H FFFFF2D0H FFFFF2D2H FFFFF2D4H FFFFF2E0H
TCL61 TM7 CR70 TCL70 TMC7 TCL71 SIO0 CSIM0 CSIS0 SIO1 CSIM1 CSIS1 SIO2 CSIM2 CSIS2 SIO3 CSIM3 CSIS3 SIO4

00H
R R/W

04H 00H
0000H
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF2E2H FFFFF2E4H FFFFF2E6H Variable-length serial control register 4 Variable-length serial setting register 4 Baud rate generator source clock selection register 4 Baud rate generator output clock selection register 4 Asynchronous serial interface mode register 0 Asynchronous serial interface status register 0 Baud rate generator control register 0 Transmission shift register 0 Reception buffer register 0 Baud rate generator mode control register 00 Asynchronous serial interface mode register 1 Asynchronous serial interface status register 1 Baud rate generator control register 1 Transmission shift register 1 Reception buffer register 1 Baud rate generator mode control register 10 Baud rate generator mode control register 01 Baud rate generator mode control register 11 IIC flag register 0
Note 1
After Reset
8 Bits 16 Bits 32 Bits

CSIM4 CSIB4 BRGCN4
R/W

00H
FFFFF2E8H
BRGCK4
7FH
FFFFF300H FFFFF302H FFFFF304H FFFFF306H FFFFF308H FFFFF30EH FFFFF310H FFFFF312H FFFFF314H FFFFF316H FFFFF318H FFFFF31EH FFFFF320H FFFFF322H FFFFF33CH FFFFF33EH FFFFF340H FFFFF342H FFFFF344H FFFFF346H FFFFF348H FFFFF34AH FFFFF34CH FFFFF350H FFFFF352H FFFFF354H FFFFF356H FFFFF358H FFFFF35AH FFFFF35CH FFFFF360H FFFFF364H
ASIM0 ASIS0 BRGC0 TXS0 RXB0 R R/W W R

00H
FFH
BRGMC00 R/W ASIM1 ASIS1 BRGC1 TXS1 RXB1 R R/W W R

00H

FFH
BRGMC10 R/W BRGMC01 BRGMC11 IICF0 IICF1 IICC0 IICS0 R R/W

00H

IIC flag register 1
Note 1
IIC control register 0 IIC state register 0
Note 2
Note 2
IIC clock selection register 0 Slave address register 0 IIC shift register 0
Note 2 Note 2
Note 2
IICCL0 SVA0 IIC0
Note 2
IIC function expansion register 0 IIC clock expansion register 0 IIC control register 1 IIC state register 1
Note 2
IICX0 IICCE0 IICC1 IICS1 R R/W

Note 2

Note 2
IIC clock selection register 1 Slave address register 1 IIC shift register 1Note 2
Note 2
Note 2
IICCL1 SVA1 IIC1 IICX1 IICCE1 WTNM WTNCS
IIC function expansion register 1Note 2 IIC clock expansion register 1 Watch timer mode register Watch timer clock selection register
Note 2

Notes 1. 2.
Available only in the BY and HY versions (products with on-chip I C). Available only in the Y versions (products with on-chip I C).
2
2
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Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF366H Watch timer high-speed clock selection registerNote 1 Correction control register Correction request register Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Oscillation stable time selection register Watchdog timer clock selection register Watchdog timer mode register DMA start factor expansion register Real-time output buffer register L Real-time output buffer register H Real-time output port mode register Real-time output port control register A/D converter mode register 1 Analog input channel specification register A/D conversion result register A/D conversion result register H (higher 8 bits) A/D converter mode register 2 Key return mode register Noise elimination control register IEBus high-speed clock selection register IEBus control register IEBus unit address register IEBus slave address register IEBus partner address register IEBus control data register IEBus telegraph length register IEBus data register IEBus unit status register IEBus interrupt status register IEBus slave status register IEBus communication success counter IEBus transfer counter IEBus clock selection register WTNHC R/W

After Reset
8 Bits 16 Bits 32 Bits
00H
FFFFF36CH FFFFF36EH FFFFF370H FFFFF374H FFFFF378H FFFFF37CH FFFFF380H FFFFF382H FFFFF384H FFFFF38EH FFFFF3A0H FFFFF3A2H FFFFF3A4H FFFFF3A6H FFFFF3C0H FFFFF3C2H FFFFF3C4H FFFFF3C6H FFFFF3C8H FFFFF3D0H FFFFF3D4H FFFFF3DEH
CORCN CORRQ CORAD0 CORAD1 CORAD2 CORAD3 OSTS WDCS WDTM DMAS RTBL RTBH RTPM RTPC ADM1 ADS ADCR ADCRH ADM2 KRM NCC V850/SB2 IEHCLK
Note 2

00000000H
04H 00H

R
0000H 00H
R/W

FFFFF3E0H FFFFF3E2H FFFFF3E4H FFFFF3E6H FFFFF3E8H FFFFF3EAH FFFFF3ECH FFFFF3EEH FFFFF3F0H FFFFF3F2H FFFFF3F4H
V850/SB2 BCR V850/SB2 UAR V850/SB2 SAR V850/SB2 PAR V850/SB2 CDR V850/SB2 DLR V850/SB2 DR V850/SB2 USR V850/SB2 ISR V850/SB2 SSR V850/SB2 SCR R R/W R R R/W

0000H
01H
00H

41H 01H
FFFFF3F6H FFFFF3F8H
V850/SB2 CCR V850/SB2 IECLK R/W

20H 00H
Notes 1. 2.
Available only in the B versions of the V850/SB1 and H versions of the V850/SB2. Available only in the H versions of the V850/SB2.
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3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, it is notified by the system status register (SYS). The V850/SB1 and V850/SB2 have two specific registers, the power save control register (PSC) and processor clock control register (PCC). For details of the PSC register, refer to 6.3.1 (2) Power save control register (PSC), and for details of the PCC register, refer to 6.3.1 (1) Processor clock control register (PCC). The following sequence shows the data setting of the specific registers. <1> Disable DMA operation. <2> Set the PSW NP bit to 1 (interrupt disabled). <3> Write any 8-bit data in the command register (PRCMD). <4> Write the set data in the specific registers (by the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Return the PSW NP bit to 0 (interrupt disable canceled). <6> Insert the NOP instructions (5 instructions). <7> If necessary, enable DMA operation. No special sequence is required when reading the specific registers. Cautions 1. If an interrupt request or a DMA request is accepted between the time PRCMD is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (PRERR bit of SYS register is 1) may occur. Therefore, set the NP bit of PSW to 1 (<2>) to disable the acceptance of INT/NMI or to disable DMA transfer. The above also applies when a bit manipulation instruction is used to set a specific register. A description example is given below. [Description example]: In case of PCC register LDSR ST.B ST.B LDSR rX.5 r0, PRCMD[r0] rD, PCC[r0] rY, 5 . . . ; NP bit = 1 ; Write to PRCMD ; PCC register setting ; NP bit = 0
Remark
The above example assumes that rD (PCC set value), rX (value to be written to PSW), and rY (value rewritten to PSW) are already set.
When saving the value of the PSW, the value of the PSW prior to setting the NP bit must be transferred to the rY register. 2. Always stop DMA prior to accessing specific registers. 3. If data is set to the PSC register to set IDLE mode or STOP mode, a dummy instruction needs to be inserted for correct execution of the routine after IDLE or STOP mode is released. For details, refer to 6.6 Cautions on Power Save Function.
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(1) Command register (PRCMD) The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. This register can be written in 8-bit units. It becomes undefined values in a read cycle. Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
After reset: Undefined Symbol PRCMD 7 REG7 W 6 REG6 5 REG5 Address: FFFFF170H 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0
REGn 0/1 Any 8-bit data
Registration code
Remark n = 0 to 7 (2) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read/written in 8-bit or 1-bit units.
After reset: 00H Symbol SYS 7 0 R/W 6 0 5 0 Address: FFFFF078H <4> PRERR 3 0 2 0 1 0 0 0
PRERR 0 1
Detection of protection error Protection error does not occur Protection error occurs
Operation conditions of PRERR flag are shown as follows. (a) Set conditions (PRERR = 1) (1) When a write operation to the specific register took place in a state where the store instruction operation for the recent peripheral I/O was not a write operation to the PRCMD register. (2) When the first store instruction operation following a write operation to the PRCMD register is to any peripheral I/O register apart from specific registers. (b) Reset conditions: (PRERR = 0) (1) When 0 is written to the PRERR flag of the SYS register. However, except for the case of Remark 1. (2) At system reset. Remarks 1. If 0 is written to the PRERR bit immediately after a write operation to the PRCMD register, the PRERR bit is set to 1 (because the SYS register is not a specific register). 2. If the PRCMD register is written again immediately after a write operation to the PRCMD register, the PRERR bit of the SYS register is set to 1 (because the SYS register is not a specific register).
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The V850/SB1 and V850/SB2 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected.
4.1 Features
* * * * Address bus (capable of separate output) 16-bit data bus Able to be connected to external devices via the pins that have alternate functions as ports Wait function * Programmable wait function, capable of inserting up to 3 wait states per 2 blocks * External wait control through WAIT pin input * * * Idle state insertion function Bus mastership arbitration function Bus hold function
4.2 Bus Control Pins and Control Register
4.2.1 Bus control pins The following pins are used for interfacing with external devices. Table 4-1. Bus Control Pins
External Bus Interface Function Address/data bus (AD0 to AD7) Address/data bus (AD8 to AD15) Address bus (A1 to A4) Address bus (A5 to A12) Address bus (A13 to A15) Address bus (A16 to A21) Read/write control (LBEN, UBEN, R/W, DSTB, WRL, WRH, RD) Address strobe (ASTB) Bus hold control (HLDRQ, HLDAK) External wait control (WAIT) Corresponding Port (Pins) Port 4 (P40 to P47) Port 5 (P50 to P57) Port 11 (P110 to P113) Port 10 (P100 to P107) Port 3 (P34 to P36) Port 6 (P60 to P65) Port 9 (P90 to P93) Port 9 (P94) Port 9 (P95, P96) Port 11 (P110)
The bus interface function of each pin is enabled by specifying the memory expansion mode register (MM) or the memory address output mode register (MAM). For the details of specifying an operation mode of the external bus interface, refer to 3.4.6 (1) Memory expansion mode register (MM) and (2) Memory address output mode register (MAM). Caution For debugging using the separate bus, refer to the user's manual of the corresponding in-circuit emulator.
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4.2.2 Control register (1) System control register (SYC) This register switches control signals for the bus interface. The system control register can be read/written in 8-bit or 1-bit units.
After reset: 00H Symbol SYC 7 0 R/W 6 0 5 0 Address: FFFFF064H 4 0 3 0 2 0 1 0 <0> BIC
BIC 0 1 DSTB, R/W, LBEN, UBEN RD, WRL, WRH, UBEN
Note Note
Bus interface control signal output
signal output
Note
The UBEN signal is output regardless of the BIC bit setting in the external expansion mode (set by the memory expansion mode register (MM)).
Caution In the V850/SB1 and V850/SB2, when using port 9 as an I/O port, set the BIC bit of the system control register (SYC) to 0. Note that the BIC bit is 0 after system reset.
4.3 Bus Access
4.3.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 4-2. Number of Access Clocks
Bus Cycle Type Internal ROM (32 Bits) Instruction fetch Operand data access 1 3 Peripheral I/O (Bus Width) Internal RAM (32 Bits) 3 1 Peripheral I/O (16 Bits) Disabled 3 External Memory (16 bits) 3+n 3+n
Remarks 1. Unit: Clock/access 2. n: Number of waits inserted
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4.3.2 Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, access to even addresses and access to odd addresses. Figure 4-1. Byte Access (8 Bits)
(a) Access to even address
15
(b) Access to odd address
15
7
8 7
7
8 7
0 Byte data
0 External data bus
0 Byte data
0 External data bus
(2) Halfword access (16 bits) In halfword access to external memory, data is dealt with as is because the data bus is fixed to 16 bits. Figure 4-2. Halfword Access (16 Bits)
15 15
0 Halfword data
0 External data bus
(3) Word access (32 bits) In word access to external memory, the lower halfword is accessed first and then the higher halfword is accessed. Figure 4-3. Word Access (32 Bits)
First
31 31
Second
16 15
15
16 15
15
0 Word data
0 External data bus
0 Word data
0 External data bus
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4.4 Memory Block Function
The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 4-4. Memory Block
FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH Block 10 A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 400000H 3FFFFFH Block 3 300000H 2FFFFFH Block 2 200000H 1FFFFFH Block 1 100000H 0FFFFFH Block 0 000000H Internal ROM area Block 5 Block 4 Block 9 Block 8 External memory area Block 7 Block 6 Block 15 Block 14 Internal RAM area Block 13 Block 12 Block 11 On-chip peripheral I/O area
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4.5 Wait Function
4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data waits can be inserted in a bus cycle that starts every two memory blocks. The number of waits can be programmed by using the data wait control register (DWC). Immediately after the system has been reset, a state in which three data waits are inserted is automatically programmed for all memory blocks. (1) Data wait control register (DWC) This register can be read/written in 16-bit units.
After reset: FFFFH Symbol DWC 15 14 R/W 13 12 11 Address: FFFFF060H 10 9 8 7 6 5 4 3 2 1 0
DW71 DW70 DW61 DW60 DW51 DW50 DW41 DW40 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00
DWn1 DWn0 0 0 1 1 0 1 0 1
Number of wait states to be inserted 0 1 2 3
n 0 1 2 3 4 5 6 7 Blocks 0/1 Blocks 2/3 Blocks 4/5 Blocks 6/7 Blocks 8/9 Blocks 10/11 Blocks 12/13 Blocks 14/15
Blocks into which wait states are inserted
Block 0 is reserved for the internal ROM area. It is not subject to programmable wait control, regardless of the setting of DWC, and is always accessed without wait states. The internal RAM area of block 15 is not subject to programmable wait control and is always accessed without wait states. The on-chip peripheral I/O area of this block is not subject to programmable wait control either; only wait control from each peripheral function is performed.
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4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in the bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait. Input of the external WAIT signal can be done asynchronously to CLKOUT and is sampled at the falling edge of the clock in the T2 and TW states of a bus cycle. If the setup/hold time at sampling timing is not satisfied, the wait state may or may not be inserted in the next state. Caution Because the A1 pin and WAIT pin are alternate-function pins, the wait function by the WAIT pin cannot be used when using a separate bus (programmable wait can be used, however). Similarly, a separate bus cannot be used when the wait function by the WAIT pin is being used. 4.5.3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of programmable wait and the wait cycle controlled by the WAIT pin. In other words, the number of wait cycles is determined by whichever has the greater number. Figure 4-5. Wait Control
Programmable wait Wait control Wait by WAIT pin
For example, if the number of programmable waits and the timing of the WAIT pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. Figure 4-6. Example of Inserting Wait States
T1 CLKOUT WAIT pin Wait by WAIT pin Programmable wait Wait control
T2
TW
TW
TW
T3
Remark
: Valid sampling timing
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4.6 Idle State Insertion Function
To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The following bus cycle starts after one idle state. Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC). Immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) Bus cycle control register (BCC) This register can be read/written in 16-bit units.
After reset: AAAAH Symbol BCC 15 BC71 14 0 R/W 13 BC61 12 0 11 BC51 Address: FFFFF062H 10 0 9 BC41 8 0 7 BC31 6 0 5 BC21 4 0 3 BC11 2 0 1 BC01 0 0
BCn1 0 1 Not inserted Inserted
Idle state insertion specification
n 0 1 2 3 4 5 6 7 Blocks 0/1 Blocks 2/3 Blocks 4/5 Blocks 6/7 Blocks 8/9 Blocks 10/11 Blocks 12/13 Blocks 14/15
Blocks into which idle state is inserted
Block 0 is reserved for the internal ROM area; therefore, no idle state can be specified. The internal RAM area and on-chip peripheral I/O area of block 15 are not subject to insertion of an idle state. Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation is not guaranteed.
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4.7 Bus Hold Function
4.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state are driven again. During the bus hold period, the internal operation continues until the next external memory access. The bus hold status can be recognized by the HLDAK pin becoming active (low). This feature can be used to design a system where two or more bus masters exist, such as when a multiprocessor configuration is used and when a DMA controller is connected. A bus hold request is not acknowledged between the first and the second word access, and between the read access and write access of the read-modify-write access executed using a bit manipulation instruction. Note A1 to A15 are set to the hold state when a separate bus is used.
Note
, and the bus is released (bus hold
status). When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins
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4.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 4-7. Bus Hold Procedure
<1>HLDRQ = 0 acknowledged <2>All bus cycle start requests held pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0
Normal status
Bus hold status <6>HLDRQ = 1 acknowledged <7>HLDAK = 1 <8>Clears pending bus cycle start requests <9>Start of bus cycle Normal status
HLDRQ HLDAK
<1> <2> <3><4><5> <6> <7><8><9>
4.7.3 Operation in power save mode In the IDLE or software STOP mode, the system clock is stopped. Consequently, the bus hold status is not set even if the HLDRQ pin becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold status is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the bus hold status is cleared, and the HALT mode is set again.
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4.8 Bus Timing
The V850/SB1 and V850/SB2 can execute read/write control for an external device using the following two modes. * Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals * Mode using RD, WRL, WRH, and ASTB signals Set these modes by using the BIC bit of the system control register (SYC) (see 4.2.2 (1) System control register (SYC)). Figure 4-8. Memory Read (1/4) (a) 0 waits
T1 CLKOUT (output)
T2
T3
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
Data
ASTB (output)
R/W (output)
WRH, WRL (output)
H
DSTB, RD (output)
UBEN, LBEN (output)
WAIT (input)
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
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Figure 4-8. Memory Read (2/4) (b) 1 wait
T1 CLKOUT (output) T2 TW T3
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
Data
ASTB (output)
R/W (output)
WRH, WRL (output)
H
DSTB, RD (output)
UBEN, LBEN (output)
WAIT (input)
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 1.
2. The broken line indicates the high-impedance state.
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Figure 4-8. Memory Read (3/4) (c) 0 waits, idle state
T1 CLKOUT (output) T2 T3 TI
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
Data
ASTB (output)
R/W (output)
WRH, WRL (output)
H
DSTB, RD (output)
UBEN, LBEN (output)
WAIT (input)
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
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Figure 4-8. Memory Read (4/4) (d) 1 wait, idle state
T1 CLKOUT (output) T2 TW T3 TI
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
Data
ASTB (output)
R/W (output)
WRH, WRL (output)
H
DSTB, RD (output)
UBEN, LBEN (output)
WAIT (input)
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 1.
2. The broken line indicates the high-impedance state.
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Figure 4-9. Memory Write (1/2) (a) 0 waits
T1 CLKOUT (output) T2 T3
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
DataNote
ASTB (output)
R/W (output)
RD (output)
H
DSTB (output)
WRH, WRL (output)
UBEN, LBEN (output)
WAIT (input)
Note
AD0 to AD7 output invalid data when odd-address byte data is accessed. AD8 to AD15 output invalid data when even-address byte data is accessed.
Remarks 1.
indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
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Figure 4-9. Memory Write (2/2) (b) 1 wait
T1 CLKOUT (output) T2 TW T3
A16 to A21 (output)
Address
A1 to A15 (output)
Address
AD0 to AD15 (I/O)
Address
DataNote
ASTB (output)
R/W (output)
RD (output)
H
DSTB (output)
WRH, WRL (output)
UBEN, LBEN (output)
WAIT (input)
Note AD0 to AD7 output invalid data when odd-address byte data is accessed. AD8 to AD15 output invalid data when even-address byte data is accessed. Remarks 1. indicates the sampling timing when the number of programmable waits is set to 1.
2. The broken line indicates the high-impedance state.
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Figure 4-10. Bus Hold Timing
T2 T3 TH TH TH TH TI T1
CLKOUT (output)
HLDRQ (input)
Note 1
HLDAK (output)
A16 to A21 (output)
Address
Address
A1 to A15 (output)
Address
Address
AD0 to AD15 (I/O)
Address
Data
Undefined
Address
ASTB (output)
Note 2
R/W (output)
DSTB, RD, WRH, WRL (output)
UBEN, LBEN (output)
WAIT (input)
Notes 1. If the HLDRQ signal is inactive (high level) at this sampling timing, the bus hold state is not entered. 2. If the bus hold status is entered after a write cycle, a high level may be output momentarily from the R/W pin immediately before the HLDAK signal changes from high level to low level. Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
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4.9 Bus Priority
There are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch), and instruction fetch (continuous) in that order. The instruction fetch cycle may be inserted between the read access and write access in a read-modify-write access. No instruction fetch cycle is inserted between the lower halfword access and higher halfword access of word access operations. Table 4-3. Bus Priority
External Bus Cycle Bus hold Memory access Instruction fetch (branch) Instruction fetch (continuous) Priority 1 2 3 4
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4.10 Memory Boundary Operation Conditions
4.10.1 Program space (1) Do not execute a branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to the peripheral I/O area. If a branch or instruction fetch is executed, the NOP instruction code is continuously fetched and no data is fetched from external memory. (2) A prefetch operation straddling over the on-chip peripheral I/O area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal RAM area. 4.10.2 Data space Only the address aligned at the halfword boundary (when the least significant bit of the address is "0")/word boundary (when the lowest 2 bits of the address are "0") boundary is accessed by halfword (16 bits)/word (32 bits) data. Therefore, access that straddles over the memory or memory block boundary does not take place. For details, refer to V850 Series Architecture User's Manual.
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5.1 Outline
The V850/SB1 and V850/SB2 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 37 to 40 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event that is dependent on program execution. Generally, an exception takes precedence over an interrupt. The V850/SB1 and V850/SB2 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 5.1.1 Features * Interrupts * * Non-maskable interrupts: 2 sources Maskable interrupts: (the number of maskable interrupt sources differs depending on the product) (V850/SB1)
PD703030B, 703031A, 703031B, 703032A, 703032B, 703033A, 703033B,
70F3030B, 70F3032A, 70F3032B, 70F3033A, 70F3033B: 70F3030BY, 70F3032AY, 70F3032BY, 70F3033AY, 70F3033BY: (V850/SB2) 37 sources 38 sources
PD703030BY, 703031AY, 703031BY, 703032AY, 703032BY, 703033AY, 703033BY,
PD703034A, 703034B, 703035A, 703035B, 703036H, 703037A, 703037H,
70F3035A, 70F3035B, 70F3036H, 70F3037A, 70F3037H: 70F3035AY, 70F3035BY, 70F3036HY, 70F3037AY, 70F3037HY: * * * * * * * 8 levels of programmable priorities Mask specification for interrupt requests according to priority Masks can be specified for each maskable interrupt request. Noise elimination, edge detection, and valid edge of external interrupt request signal can be specified. Software exceptions: 32 sources Exception trap: 1 source (illegal opcode exception) 39 sources 40 sources
PD703034AY, 703034BY, 703035AY, 703035BY, 703036HY, 703037AY, 703037HY,
Exceptions
The interrupt/exception sources are listed in Table 5-1.
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Table 5-1. Interrupt Source List (1/2)
Type Classification Default Priority - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name Trigger Interrupt Exception Source Code - - WDT - - - WDT Pin Pin Pin Pin Pin Pin Pin WT TM0 TM0 TM1 TM1 Handler Address Restored Interrupt PC Control Register Undefined nextPC nextPC nextPC nextPC nextPC - - - - - - WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 WTNIIC TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 TMIC6 TMIC7 CSIC0
Reset
Interrupt
RESET
Reset input
0000H
00000000H
NonInterrupt maskable Interrupt Software Exception exception Exception Exception Exception trap Maskable Interrupt
NMI INTWDT TRAP0n TRAP1n ILGOP
Note 1
NMI pin input WDTOVF non-maskable TRAP instruction TRAP instruction Illegal opcode
0010H 0020H 004nH 005nH
Note 1
00000010H 00000020H 00000040H 00000050H 00000060H
Note 1
Note 1
0060H
INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTWTNI INTTM00 INTTM01 INTTM10 INTTM11 INTTM2 INTTM3 INTTM4 INTTM5 INTTM6 INTTM7 INTIIC0Note 2/ INTCSI0 INTSER0 INTSR0/ INTCSI1 INTST0
WDTOVF maskable INTP0 pin INTP1 pin INTP2 pin INTP3 pin INTP4 pin INTP5 pin INTP6 pin Watch timer prescaler INTTM00 INTTM01 INTTM10 INTTM11
0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01C0H 01D0H 01E0H 01F0H
00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
TM2 compare match/OVF TM2 TM3 compare match/OVF TM3 TM4 compare match/OVF TM4 TM5 compare match/OVF TM5 TM6 compare match/OVF TM6 TM7 compare match/OVF TM7 I2C interrupt/ CSI0 transmit end UART0 serial error UART0 receive end/ CSI1 transmit end UART0 transmit end I2C/ CSI0 UART0 UART0/ CSI1 UART0
20 21
0200H 0210H
00000200H 00000210H
nextPC nextPC
SERIC0 CSIC1
22
0220H
00000220H
nextPC
STIC0
Notes 1. 2.
n: 0 to FH Available only in the Y versions (products with on-chip I C).
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Table 5-1. Interrupt Source List (2/2)
Type Classification Default Priority Name Trigger Interrupt Exception Source Code Handler Address Restored Interrupt PC Control Register nextPC nextPC nextPC nextPC CSIC2 IICIC1 SERIC1 CSIC3
Maskable Interrupt
23 24 25 26
INTCSI2 INTIIC1Note 1 INTSER1 INTSR1/ INTCSI3 INTST1 INTCSI4 INTIE1Note 2 INTIE2
Note 2
CSI2 transmit end I2C1 interrupt UART1 serial error UART1 receive end/ CSI3 transmit end UART1 transmit end CSI4 transmit end IEBus transfer end IEBus communication end A/D conversion end DMA0 transfer end DMA1 transfer end DMA2 transfer end DMA3 transfer end DMA4 transfer end DMA5 transfer end Watch timer OVF Key return interrupt
CSI2 I2C1 UART1 UART1/ CSI3 UART1 CSI4 IEBus IEBus
0230H 0240H 0250H 0260H
00000230H 00000240H 00000250H 00000260H
27 28 29 30
0270H 0280H 0290H 02A0H
00000270H 00000280H 00000290H 000002A0H
nextPC nextPC nextPC nextPC
STIC1 CSIC4 IEBIC1 IEBIC2
31 32 33 34 35 36 37 38 39
INTAD INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTDMA4 INTDMA5 INTWTN INTKR
A/D DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 WT KR
02B0H 02C0H 02D0H 02E0H 02F0H 0300H 0310H 0320H 0330H
000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
ADIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 DMAIC4 DMAIC5 WTNIC KRIC
Notes 1. 2.
Available only in the Y versions (products with on-chip I C). Available only in the V850/SB2. Default Priority: Restored PC: Priority when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The value of the PC saved to EIPC or FEPC when interrupt/exception processing is started. However, the value of the PC saved when an interrupt is acknowledged during DIVH (division) instruction execution is the value of the PC of the current instruction (DIVH). 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). 3. The restored PC of an interrupt/exception other than RESET is the value of the PC (when an event occurred) + 1. 4. Non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM) are set by the WDTM4 bit of the watchdog timer mode register (WDTM).
2
Remarks 1.
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5.2 Non-Maskable Interrupt
A non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are available in the V850/SB2. * * NMI pin input (NMI) Non-maskable watchdog timer interrupt request (INTWDT)
When the valid edge specified by rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) is detected at the NMI pin, an interrupt occurs. INTWDT functions as the non-maskable interrupt (INTWDT) only in the state in which the WDTM4 bit of the watchdog timer mode register (WDTM) is set to 1. While the service routine of a non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgment of another non-maskable interrupt request is held pending. The pending NMI is acknowledged after the original service routine of the non-maskable interrupt under execution has been terminated (by the RETI instruction), or when PSW.NP is cleared to 0 by the LDSR instruction. Note that if two or more NMI requests are input during the execution of the service routine for an NMI, the number of NMIs that will be acknowledged after PSW.NP goes to ``0'', is only one. Caution If PSW.NP is cleared to 0 by the LDSR instruction during non-maskable interrupt servicing, the interrupt afterwards cannot be acknowledged correctly.
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5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception codes 0010H and 0020H to the higher halfword (FECC) of ECR. (4) Sets the NP and ID bits of the PSW and clears the EP bit. (5) Loads the handler address (00000010H, 00000020H) of the non-maskable interrupt routine to the PC, and transfers control. Figure 5-1. Non-Maskable Interrupt Servicing
NMI input
INTC accepted Non-maskable interrupt request
CPU processing PSW. NP 0 1
FEPC FEPSW ECR. FECC PSW. NP PSW. EP PSW. ID PC
Restored PC PSW Exception code 1 0 1 00000010H, 00000020H
Interrupt request pending
Interrupt servicing
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Figure 5-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is being executed:
Main routine
(PSW. NP = 1)
NMI request
NMI request
NMI request held pending because PSW. NP = 1
Pending NMI request processed
(b) If a new NMI request is generated twice while an NMI service routine is being executed:
Main routine
NMI request NMI request NMI request
Held pending because NMI service program is being processed
Held pending because NMI service program is being processed
Only one NMI request is acknowledged even though two or more NMI requests are generated
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5.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. (2) Transfers control back to the address of the restored PC and PSW. How the RETI instruction is processed is shown below. Figure 5-3. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
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5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged.
After reset: 00000020H Symbol PSW 31 0 8 7 6 5 4 3 2 1 S 0 Z
NP EP ID SAT CY OV
NP 0 1 No NMI interrupt servicing
NMI servicing state
NMI interrupt currently being serviced
5.2.4 Noise eliminator of NMI pin NMI pin noise is eliminated by the noise eliminator using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge, unless it maintains its input level for a certain period. The edge is detected after a certain period has elapsed. The NMI pin is used for releasing the software stop mode. In the software stop mode, the system clock is not used for noise elimination because the internal system clock is stopped.
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5.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, or neither edge. Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of the non-maskable interrupt (NMI). These two registers can be read/written in 1-bit or 8-bit units. After reset, the valid edge of the NMI pin is set to the "detect neither rising nor falling edge" state. Therefore, the NMI pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the EGP0 and EGN0 registers. When using P00 as an output port, set the NMI valid edge to "detect neither rising nor falling edge". (1) Rising edge specification register 0 (EGP0)
After reset: 00H Symbol EGP0 <7> EGP07 R/W <6> EGP06 <5> EGP05 Address: FFFFF0C0H <4> EGP04 <3> EGP03 <2> EGP02 <1> EGP01 <0> EGP00
EGP0n 0 1
Rising edge valid control No interrupt request signal occurred at the rising edge Interrupt request signal occurred at the rising edge
n = 0: NMI pin control n = 1 to 7: INTP0 to INTP6 pin control (2) Falling edge specification register 0 (EGN0)
After reset: 00H Symbol EGN0 <7> EGN07 R/W <6> EGN06 <5> EGN05 Address: FFFFF0C2H <4> EGN04 <3> EGN03 <2> EGN02 <1> EGN01 <0> EGN00
EGN0n 0 1
Falling edge valid control No interrupt request signal occurred at the falling edge Interrupt request signal occurred at the falling edge
n = 0: NMI pin control n = 1 to 7: INTP0 to INTP6 pin control
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5.3 Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers. The V850/SB1 and V850/SB2 have 37 to 40 maskable interrupt sources (see 5.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers, allowing programmable priority control. When an interrupt request has been acknowledged, the acknowledgment of other maskable interrupts is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set which enables interrupts having a higher priority to immediately interrupt the current service routine in progress. Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction. When the WDTM4 bit of the watchdog timer mode register (WDTM) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (INTWDTM). 5.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower halfword of ECR (EICC). (4) Sets the ID bit of the PSW and clears the EP bit. (5) Loads the corresponding handler address to the PC, and transfers control. The INT input masked by INTC and the INT input that occurs during the other interrupt servicing (when PSW.NP = 1 or PSW.ID = 1) are internally held pending. When the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT is input to start the new maskable interrupt servicing. How the maskable interrupts are serviced is shown below.
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Figure 5-4. Maskable Interrupt Servicing
INT input
INTC accepted Mask? No PSW. ID = 0 Yes
Priority higher than that of interrupt currently serviced?
Yes
No Interrupt enable mode?
No
Yes
Priority higher than that of other interrupt request?
No
Yes
Highest default priority of interrupt requests with the same priority?
No
Yes Maskable interrupt request CPU processing 1 PSW. NP 0 1 PSW. ID 0 EIPC EIPSW ECR. EICC PSW. EP PSW. ID PC Restored PC PSW Exception code 0 1 Handler address Interrupt request pending Interrupt request pending
Interrupt servicing
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5.3.2 Restore To restore execution from maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of PSW is 0. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 5-5. RETI Instruction Processing
RETI instruction
1 PSW. EP 0 1
PSW. NP 0
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Restores original processing
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
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5.3.3 Priorities of maskable interrupts The V850/SB1 and V850/SB2 provide multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by the interrupt priority level specification bit (xxPRn). When two or more interrupts having the same priority level specified by xxPRn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, refer to Table 5-1. Programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request is acknowledged, the ID flag of the PSW is automatically set to ``1''. Therefore, when multiple interrupts are to be used, clear the ID flag to ``0'' beforehand (for example, by placing the EI instruction into the interrupt service program) to set the interrupt enabled mode. Remark xx: Identification name of each peripheral unit (refer to Table 5-2) n: Number of each peripheral unit (refer to Table 5-2)
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Figure 5-6. Example of Multiple Interrupt Servicing (1/2)
Main routine Servicing of a EI Interrupt request a (level 3) Interrupt request b (level 2) EI Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b
Servicing of c
Interrupt request c (level 3)
Interrupt request d (level 2) Servicing of d Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled.
Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Servicing of f Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e.
Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Servicing of h
Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g.
Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts. Remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests.
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Figure 5-6. Example of Multiple Interrupt Servicing (2/2)
Main routine Servicing of i EI Interrupt request i (level 2) EI Interrupt request j (level 3) Interrupt request k (level 1) Processing of k
Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority.
Servicing of j
Servicing of l Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status.
Interrupt request l (level 2)
Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m.
Servicing of m
Interrupt request o (level 3)
Interrupt request p (level 2)
Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q EI Interrupt (level 1) request r (level 0)
If levels 3 to 0 are acknowledged Servicing of s Interrupt request t (level 2) Interrupt request u (level 2) Pending interrupt requests t and u are acknowledged after processing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated.
Interrupt request s (level 1)
Note 1
Note 2
Servicing of u
Servicing of t
Notes 1. 2.
Lower default priority Higher default priority
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Figure 5-7. Example of Servicing Interrupt Requests Generated Simultaneously
Main routine EI Interrupt request a (level 2) Interrupt request b (level 1)Note 1 Interrupt request c (level 1)Note 2 Servicing of interrupt request b * Interrupt request b and c are acknowledged first according to their priorities. * Because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority.
NMI request
Servicing of interrupt request c
Servicing of interrupt request a
Notes 1. 2.
Higher default priority Lower default priority
Remarks 1. a, b, and c in the above figure are the names of interrupt requests shown for the sake of explanation. 2. The default priority in the above figure indicates the relative priority between two interrupt requests.
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5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Cautions 1. If the following three conditions conflict, interrupt servicing is executed twice. However, when DMA is not used, interrupt servicing is not executed twice. * Execution of a bit manipulation instruction corresponding to the interrupt request flag (xxIFn) * An interrupt via hardware of the same interrupt control register (xxICn) as the interrupt request flag (xxIFn) is generated * DMA is started during execution of a bit manipulation instruction corresponding to the interrupt request flag (xxIFn) Two workarounds using software are shown below. * Insert a DI instruction before the software-based bit manipulation instruction and an EI instruction after it, so that jumping to an interrupt immediately after the bit manipulation instruction execution does not occur. * When an interrupt request is acknowledged, since the hardware becomes interrupt disabled (DI state), clear the interrupt request flag (xxIFn) before executing the EI instruction in each interrupt servicing routine. 2. Read the xxIFn bit of the xxICn register with interrupts disabled. When the xxIFn bit is read with interrupts enabled, a normal value may not be read if the interrupt acknowledgment timing and the bit read timing conflict.
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After reset: 47H Symbol xxICn <7> xxIFn
R/W <6> xxMKn 5 0
Address: FFFFF100H to FFFFF156H 4 0 3 0 2 xxPRn2 1 xxPRn1 0 xxPRn0
xxIFn 0 1
Interrupt request flagNote Interrupt request not generated Interrupt request generated
xxMKn 0 1 Interrupt servicing enabled
Interrupt mask flag
Interrupt servicing disabled (pending)
xxPRn2 0 0 0 0 1 1 1 1
xxPRn1 0 0 1 1 0 0 1 1
xxPRn0 0 1 0 1 0 1 0 1
Interrupt priority specification bit Specifies level 0 (highest) Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 (lowest)
Note Automatically reset by hardware when an interrupt request is acknowledged. Remark xx: Identification name of each peripheral unit (see Table 5-2) n: Peripheral unit number (see Table 5-2)
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The address and bits of each interrupt control register are as follows. Table 5-2. Interrupt Control Register (xxICn)
Address FFFFF100H FFFFF102H FFFFF104H FFFFF106H FFFFF108H FFFFF10AH FFFFF10CH FFFFF10EH FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H Register <7> WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 WTNIIC TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 TMIC6 TMIC7 CSIC0 SERIC0 CSIC1 STIC0 CSIC2 IICIC1Note 1 SERIC1 CSIC3 STIC1 CSIC4 IEBIC1Note 2 IEBIC2Note 2 ADIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 DMAIC4 DMAIC5 WTNIC KRIC WDTIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 WTNIIF TMIF00 TMIF01 TMIF10 TMIF11 TMIF2 TMIF3 TMIF4 TMIF5 TMIF6 TMIF7 CSIF0 SERIF0 CSIF1 STIF0 CSIF2 IICIF1 SERIF1 CSIF3 STIF1 CSIF4 IEBIF1 IEBIF2 ADIF DMAIF0 DMAIF1 DMAIF2 DMAIF3 DMAIF4 DMAIF5 WTNIF KRIF <6> WDTMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 WTNIMK TMMK00 TMMK01 TMMK10 TMMK11 TMMK2 TMMK3 TMMK4 TMMK5 TMMK6 TMMK7 CSMK0 SERMK0 CSMK1 STMK0 CSMK2 IICMK1 SERMK1 CSMK3 STMK1 CSMK4 IEBMK1 IEBMK2 ADMK DMAMK0 DMAMK1 DMAMK2 DMAMK3 DMAMK4 DMAMK5 WTNMK KRMK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 WDTPR2 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 WTNIPR2 TMPR002 TMPR012 TMPR102 TMPR112 TMPR22 TMPR32 TMPR42 TMPR52 TMPR62 TMPR72 CSPR02 SERPR02 CSPR12 STPR02 CSPR22 IICPR12 SERPR12 CSPR32 STPR12 CSPR42 IEBPR12 IEBPR22 ADPR2 DMAPR02 DMAPR12 DMAPR22 DMAPR32 DMAPR42 DMAPR52 WTNPR2 KRPR2 1 WDTPR1 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 WTNIPR1 TMPR001 TMPR011 TMPR101 TMPR111 TMPR21 TMPR31 TMPR41 TMPR51 TMPR61 TMPR71 CSPR01 SERPR01 CSPR11 STPR01 CSPR21 IICPR11 SERPR11 CSPR31 STPR11 CSPR41 IEBPR11 IEBPR21 ADPR1 DMAPR01 DMAPR11 DMAPR21 DMAPR31 DMAPR41 DMAPR51 WTNPR1 KRPR1 0 WDTPR0 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60 WTNIPR0 TMPR000 TMPR010 TMPR100 TMPR110 TMPR20 TMPR30 TMPR40 TMPR50 TMPR60 TMPR70 CSPR00 SERPR00 CSPR10 STPR00 CSPR20 IICPR10 SERPR10 CSPR30 STPR10 CSPR40 IEBPR10 IEBPR20 ADPR0 DMAPR00 DMAPR10 DMAPR20 DMAPR30 DMAPR40 DMAPR50 WTNPR0 KRPR0
Notes 1. 2.
Available only in the Y versions (products with on-chip I C). Available only in the V850/SB2.
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5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. processing or exception processing. This register is read-only in 8-bit or 1-bit units. Caution Read the ISPR register with interrupts disabled. When the ISPR register is read with interrupts enabled, a normal value may not be read if the interrupt acknowledgment timing and the bit read timing conflict.
After reset: 00H Symbol ISPR <7> ISPR7 R <6> ISPR6 <5> ISPR5 Address: FFFFF166H <4> ISPR4 <3> ISPR3 <2> ISPR2 <1> ISPR1 <0> ISPR0
However, it is not reset when execution is returned from non-maskable
ISPRn 0 1
Indicates priority of interrupt currently acknowledged Interrupt request with priority n not acknowledged Interrupt request with priority n acknowledged
Remark
n: 0 to 7 (priority level)
5.3.6 ID flag The interrupt disable status flag (ID) of the PSW controls the enabling and disabling of maskable interrupt requests. As a status flag, it also displays the current maskable interrupt acknowledgment status.
After reset: 00000020H Symbol PSW 31 0 8 7 6 5 4 3 2 1 S 0 Z
NP EP ID SAT CY OV
ID 0 1
Specifies maskable interrupt servicingNote Maskable interrupt acknowledgment enabled Maskable interrupt acknowledgment disabled (pending)
Note Interrupt disable flag (ID) function It is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. maskable interrupt is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request generated during the acknowledgment disabled period (ID = 1) can be acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag is reset to 0. Remark xx: Identification name of each peripheral unit (refer to Table 5-2) n: Number of each peripheral unit (refer to Table 5-2)
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5.3.7 Watchdog timer mode register (WDTM) This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 9 WATCHDOG TIMER).
After reset: 00H Symbol WDTM <7> RUN R/W 6 0 5 0 Address: FFFFF384H 4 WDTM4 3 0 2 0 1 0 0 0
RUN 0 1 Count operation stopped Count start after clearing
Watchdog timer operation control
WDTM4 0 1
Timer mode selection/interrupt control by WDT Interval timer mode WDT mode
Caution
If the RUN or WDTM4 bit is set to 1, it cannot be cleared other than by reset input.
5.3.8 Noise elimination (1) Noise elimination of INTP0 to INTP3 pins The INTP0 to INTP3 pins incorporate a noise eliminator that functions using analog delay. Therefore, a signal input to each pin is not detected as an edge, unless it maintains its input level for a certain period. An edge is detected after a certain period has elapsed. (2) Noise elimination of INTP4 and INTP5 pins The INTP4 and INTP5 pins incorporate a digital noise eliminator. If the input level of the INTP pin is detected by the sampling clock (fXX) and the same level is not detected three successive times, the input pulse is eliminated as a noise. Note the following. * * * If the input pulse width is between 2 and 3 clocks, whether the input pulse is detected as a valid edge or eliminated as noise is undefined. To securely detect the valid edge, the same level input of 3 clocks or more is required. When noise is generated in synchronization with the sampling clock, this may not be recognized as noise. In this case, eliminate the noise by adding a filter to the input pin.
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(3) Noise elimination of INTP6 pin The INTP6 pin incorporates a digital noise eliminator. The sampling clock for digital sampling can be selected from among fXX, fXX/64, fXX/128, fXX/256, fXX/512, fXX/1024, and fXT. Sampling is performed 3 times. (a) Noise elimination control register (NCC) The noise elimination control register (NCC) selects the clock to be used. Remote control signals can be received effectively with this function. fXT can be used for the noise elimination clock. In this case, the INTP6 external interrupt function is enabled in the IDLE/STOP mode. This register can be read/written in 8-bit or 1-bit units. Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the noise eliminator. For that reason, if an INTP6 valid edge was input within these 3 clocks, an interrupt request may occur. Therefore, be careful of the following when using the interrupt and DMA functions. * * When using the interrupt function, after 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (bit 7 of PIC6) has been cleared. When using the DMA function, after 3 sampling clocks have elapsed, enable DMA by setting bit 0 of DCHCn.
After reset: 00H 7 NCC 0 R/W 6 0 5 0 Address: FFFFF3D4H 4 0 3 0 2 NCS2 1 NCS1 0 NCS0
NCS2
NCS1
NCS0
Noise elimination clock fXX fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 Setting prohibited fXT
Reliably eliminated noise widthNote 1 fXX = 20 MHzNote 2 100 ns 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s fXX = 12.58 MHz 158 ns 10.1 s 20.3 s 40.6 s 81.3 s 162.7 s
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
61 s
Notes 1. 2.
Since sampling is preformed three times, the reliably eliminated noise width is 2 x noise elimination clock. Only in the V850/SB1.
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5.3.9 Edge detection function The valid edges of the INTP0 to INTP6 pins can be selected for each pin from the following four types. * Rising edge * Falling edge * Both rising and falling edges * Neither edge The validity of the rising edge is controlled by rising edge specification register 0 (EGP0), and the validity of the falling edge is controlled by falling edge specification register 0 (EGN0). Refer to 5.2.5 Edge detection function of NMI pin for details of EGP0 and EGN0. After reset, the valid edge of the NMI pin is set to the "detect neither rising nor falling edge" state. Therefore, the NMI pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the EGP0 and EGN0 registers. When using P01 to P07 as output ports, set the valid edges of INTP0 to INTP6 to "detect neither rising nor falling edge" or mask the interrupt request.
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5.4 Software Exceptions
A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. * TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Series Architecture User's Manual. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). (4) Sets the EP and ID bits of the PSW. (5) Loads the handler address (00000040H or 00000050H) of the software exception routine in the PC, and transfers control. How a software exception is processed is shown below. Figure 5-8. Software Exception Processing
TRAP instruction CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address
Exception processing
Handler address: 00000040H (Vector = 0nH) 00000050H (Vector = 1nH)
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5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 5-9. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception process, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
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5.4.3 EP flag The EP flag in the PSW is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs, and interrupts are disabled.
After reset: 00000020H Symbol PSW 31 0 8 7 6 5 4 3 2 1 S 0 Z
NP EP ID SAT CY OV
EP 0 1
Exception processing Exception processing is not in progress Exception processing is in progress
5.5 Exception Trap
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850/SB1 or V850/SB2, an illegal opcode exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap. * Illegal opcode exception: Occurs if the sub opcode field of the instruction to be executed next is not a valid opcode. 5.5.1 Illegal opcode definition An illegal opcode is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to 1111B. Figure 5-10. Illegal Opcode
15 13 12 11 10 54 0 31 27 26 23 22 21 20 17 16
0011 to xxxxx111111xxxxxxxxxx xxxxxxx 1111
x: don't care 5.5.2 Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR. (4) Sets the EP and ID bits of the PSW. (5) Loads the handler address (00000060H) for the exception trap routine to the PC, and transfers control.
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How the exception trap is processed is shown below. Figure 5-11. Exception Trap Processing
Exception trap (ILGOP) occurs CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 00000060H
Exception processing
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5.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 5-12. RETI Instruction Processing
RETI instruction
1 PSW. EP 0 1
PSW. NP 0
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Jump to PC
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the exception trap process, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
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5.6 Priority Control
5.6.1 Priorities of interrupts and exceptions Table 5-3. Priorities of Interrupts and Exceptions
RESET RESET NMI INT TRAP ILGOP x x x x NMI * INT * TRAP * ILGOP *
RESET: Reset NMI: INT: TRAP: *: x: : : Non-maskable interrupt Maskable interrupt Software exception The item on the left ignores the item above. The item on the left is ignored by the item above. The item above is higher than the item on the left in priority. The item on the left is higher than the item above in priority.
ILGOP: Illegal opcode exception
5.6.2 Multiple interrupt servicing Multiple interrupt servicing is a function that allows the nesting of interrupts. the original routine will resume once the higher priority interrupt routine is completed. If an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. Multiple interrupt servicing control is performed in the interrupt enabled state (ID = 0). Even in an interrupt servicing routine, this control must be set in the interrupt enabled state (ID = 0). EIPSW must be saved. The following example shows the procedure of interrupt nesting. If a maskable interrupt is acknowledged or exception is generated during a service program of a maskable interrupt or exception, EIPC and If a higher priority interrupt is generated and acknowledged, it will be allowed to stop a current interrupt service routine in progress. Execution of
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(1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception ... ... * Save EIPC to memory or register * Save EIPSW to memory or register * EI instruction (enables interrupt acknowledgment) ... ... * DI instruction (disables interrupt acknowledgment) * Restore saved value to EIPSW * Restore saved value to EIPC * RETI instruction Acknowledgment interrupt such as INTP input.
(2) To generate exception in service program Service program of maskable interrupt or exception
... ... * Save EIPC to memory or register * Save EIPSW to memory or register * EI instruction (enables interrupt acknowledgment) ... * TRAP instruction * Illegal opcode ... * Restore saved value to EIPSW * Restore saved value to EIPC * RETI instruction Acknowledgment exception such as TRAP instruction. Acknowledgment exception such as illegal opcode.
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Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt servicing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request. At reset, the interrupt request is masked by the xxMKn bit, and the priority level is set to 7 by the xxPRn0 to xxPRn2 bits. Remark xx: Identification name of each peripheral unit (refer to Table 5-2) n: Number of each peripheral unit (refer to Table 5-2) Priorities of maskable interrupts (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low)
Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed. A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In the non-maskable interrupt servicing routine (time until the RETI instruction is executed), maskable interrupts are not acknowledged but are suspended.
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5.7 Interrupt Latency Time
The following table describes the interrupt latency time (from interrupt request generation to start of interrupt servicing). Figure 5-13. Pipeline Operation at Interrupt Request Acknowledgment
7 to 14 system clocks System clock Interrupt request Instruction 1 Instruction 2 Instruction 3 Interrupt acknowledgment operation Instruction (start instruction of interrupt servicing routine) IF ID EX MEM WB IFX INT1 INT2 INT3 INT4 IF ID EX MEM WB IFX IDX 4 system clocks
INT1 to INT4: Interrupt acknowledgment processing IFX: IDX: Invalid instruction fetch Invalid instruction decode
Interrupt Latency Time (System Clock) Internal interrupt Minimum Maximum 11 18 External interrupt 13 20 Time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: * In IDLE/STOP mode * External bus is accessed * Two or more interrupt request non-sample instructions are executed in succession * An interrupt control register is accessed Condition
5.8 Periods in Which Interrupt Is Not Acknowledged
An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. Interrupt request non-sample instruction * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (vs. PSW)
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5.8.1 Interrupt request valid timing after EI instruction When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed (interrupts disabled) and interrupts are not masked (MK flag = 0), seven system clocks are required from the execution of the EI instruction (interrupts enabled) to the interrupt request acknowledgment by the CPU. The CPU does not acknowledge interrupt requests if the DI instruction (interrupts disabled) is executed during the seven system clocks. Therefore, seven system clocks worth of instruction execution clocks must be inserted after the EI instruction (interrupts enabled). However, under the following conditions, interrupt requests cannot be acknowledged even if the seven system clocks are secured, so securing under the following conditions is prohibited. * In IDLE/STOP mode * An interrupt request non-sampling instruction (instruction to manipulate the PSW.ID bit) is executed * An interrupt request control register (xxICn) is accessed The following shows an example of program processing. [Program processing example] DI : : EI NOP NOP NOP NOP JR : LP1 : DI ; LPI routine ; After EI instruction execution, NOP instruction is executed four times, and DI instruction is executed at the eighth clock by JR instruction LP1 ; (MK flag = 0) ; Interrupt request occurs (IF flag = 1) ; EI instruction executed ; 1 system clock ; 1 system clock ; 1 system clock ; 1 system clock ; 3 system clocks (branch to LP1 routine)
Note
Note Do not execute the DI instruction (PSW.ID = 1) during this period. Remarks 1. In this example, the DI instruction is executed at the eighth clock after execution of the EI instruction, so the CPU acknowledges an interrupt request signal and performs interrupt servicing. 2. The interrupt servicing routine instructions are not executed at the eighth clock after the EI instruction execution. The interrupt servicing routine instructions are executed four system clocks after the CPU acknowledges the interrupt request signal. 3. This example shows the case in which an interrupt request signal is generated (IF flag = 1) before the EI instruction is executed. If an interrupt request signal is generated after the EI instruction is executed, the CPU does not acknowledge the interrupt request signal if interrupts are disabled (PSW.ID = 1) for seven clocks after the IF flag is set (1).
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Figure 5-14. Pipeline Flow and Interrupt Request Signal Generation Timing
(a) When DI instruction is executed at eighth clock after EI instruction execution (interrupt request is acknowledged)
EI IF NOP ID IF NOP EX ID IF NOP MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF DI ei signal intrq signal WB MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB
intrq signal is generated
(b) When DI instruction is executed at seventh clock after EI instruction execution (interrupt request is not acknowledged)
EI IF NOP ID IF NOP EX ID IF NOP MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF DI ei signal intrq signal WB MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB
intrq signal is not generated
5.9
Interrupt Control Register Bit Manipulation Instructions During DMA Transfer
To manipulate the bits of the interrupt control register (xxICn) in the EI state when using the DMA function, execute the DI instruction before manipulation and EI instruction after manipulation. Alternatively, clear (0) the xxIF bit at the start of the interrupt servicing routine. When not using the DMA function, these manipulations are not necessary. Remark xx: Peripheral unit identification name (see Table 5-2) N: Peripheral unit number (see Table 5-2)
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5.10 Key Interrupt Function
Key interrupts can be generated by inputting a falling edge to the key input pins (KR0 to KR7) by setting the key return mode register (KRM). The key return mode register (KRM) includes 5 bits. The KRM0 bit controls the KR0 to KR3 signals in 4-bit units and the KRM4 to KRM7 bits control corresponding signals from KR4 to KR7 (arbitrary setting from 4 to 8 bits is possible). This register can be read/written in 8-bit or 1-bit units. (1) Key return mode register (KRM)
After reset:
00H
<7>
R/W <6> KRM6 <5> KRM5
Address: FFFFF3D0H <4> KRM4 3 0 2 0 1 0 <0> KRM0
KRM
KRM7
KRMn 0 1 Do not detect key return signal Detect key return signal
Key return mode control
Caution
If the key return mode register (KRM) is changed, an interrupt request flag may be set. To avoid setting this flag, change the KRM register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag. Table 5-4. Description of Key Return Detection Pin
Flag KRM0 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 to KR3 signals in 4-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units
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Figure 5-15. Key Return Block Diagram
KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 INTKR
KRM7 KRM6 KRM5 KRM4
0
0
0
KRM0
Key return mode register (KRM)
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6.1 Outline
The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of clock oscillators. (1) Main clock oscillator The oscillator of V850/SB1 has an oscillation frequency of 2 to 20 MHz. The oscillator of the A and B versions of the V850/SB2 has an oscillation frequency of 2 to 12.58 MHz and the oscillator of the H version of the V850/SB2 has an oscillation frequency of 2 to 19 MHz. Oscillation can be stopped by executing a STOP instruction or by setting the processor clock control register (PCC). Oscillation is also stopped during a reset. In IDLE mode, supplying the peripheral clock to the clock timer only is possible. Therefore, in IDLE mode, it is possible to operate the clock timer without using the subclock oscillator. Cautions 1. When the main oscillator is stopped by inputting a reset or executing a STOP instruction, the oscillation stabilization time is secured after the stop mode is released. This oscillation stabilization time is set via the oscillation stabilization time selection register (OSTS). The watchdog timer is used as the timer that counts the oscillation stabilization time. 2. If the main clock halt is released by clearing MCK to 0 after the main clock is stopped by setting the MCK bit in the PCC register to 1, the oscillation stabilization time is not secured. (2) Subclock oscillator This circuit has an oscillation frequency of 32.768 kHz. Its oscillation is not stopped when the STOP instruction is executed, neither is it stopped when a reset is input. When the subclock oscillator is not used, the FRC bit in the processor clock control register (PCC) can be set to disable use of the internal feedback resistor. This enables the current consumption to be kept low in the STOP mode.
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6.2 Configuration
Figure 6-1. Clock Generator
FRC XT1 XT2 Subclock oscillator fXT IDLE X1 X2 Main clock oscillator IDLE control IDLE control Prescaler fXT fXX/2 fXX/4 fXX/8 STP, MCK Selector HALT control CPU clock (fCPU) Clock supplied to watch timer, etc. CK2 to CK0 HALT
fXX
Prescaler
Clock supplied to peripheral hardware
CLKOUT
6.3 Clock Output Function
This function outputs the CPU clock via the CLKOUT pin. When clock output is enabled, the CPU clock is output via the CLKOUT pin. When it is disabled, a low-level signal is output via the CLKOUT pin. Output is stopped in the IDLE or STOP mode (fixed to low level). This function is controlled via the DCLK1 and DCLK0 bits in the power save control register (PSC). The high-impedance status is set during the reset period. After reset is released, a low level is output. Caution While CLKOUT is being output, do not change the CPU clock (CK2 to CK0 bits of processor clock control register (PCC)).
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6.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8-bit or 1-bit units.
After reset: 03H <7> PCC FRC R/W <6> MCK Address: FFFFF074H 5 0 4 0 3 0 <2> CK2 1 CK1 0 CK0
FRC 0 1 Use Do not use
Selection of internal feedback resistor for subclock
MCK 0 1 Operating Stopped
Operation of main clock (main clock)
CK2Notes 1, 2 0 0 0 0 1
CK1 0 0 1 1 X
CK0 0 1 0 1 X fXX fXX/2 fXX/4 fXX/8 fXT (subclock)
Selection of CPU clock
Notes 1. If manipulating CK2, do so in 1-bit units. In the case of 8-bit manipulation, do not change the values of CK1 and CK0. 2. When the CPU operates on the subclock (CK2 = 1), do not set the HALT or software STOP mode. Cautions 1. While CLKOUT is being output, do not change the CPU clock (the value of the CK2 to CK0 in the PCC register). 2. Even if the MCK bit is set to 1 during main clock operation, the main clock is not stopped. The CPU clock stops after the subclock is selected. 3. Be sure to set bits 3 to 5 to 0. Remark X: don't care
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(a) Example of main clock operation subclock operation setup <1> CK2 1: <2> Subclock operation: Bit manipulation instructions are recommended. Do not change CK1 and CK0. The maximum number of the following instructions is required before subclock operation after the CK2 bit is set. (CPU clock frequency before setting / subclock frequency) x 2 Therefore, insert the wait described above using a program. <3> MCK 1: Only when the main clock is stopped.
(b) Example of subclock operation main clock operation setup <1> MCK 0: <3> CK2 0: Main clock oscillation start Bit manipulation instructions are recommended. Do not change CK1 and CK0. bit is set. <2> Insert a wait using a program and wait until the main clock oscillation stabilization time elapses. <4> Main clock operation: At most two instructions are required before main clock operation after the CK2
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(2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8-bit or 1-bit units.
After reset: C0H 7 PSC DCLK1 R/W 6 DCLK0 Address: FFFFF070H 5 0 4 0 3 0 <2> IDLE <1> STP 0 0
DCLK1 0 0 1 1
DCLK0 0 1 0 1 Output enabled Setting prohibited Setting prohibited
Specification of CLKOUT pin's operation
Output disabled (when reset)
IDLE 0 1 Normal mode IDLE modeNote 1
IDLE mode setting
STP 0 1 Normal mode STOP modeNote 2
STOP mode setting
Notes 1. 2.
When IDLE mode is released, this bit is automatically reset to 0. When STOP mode is released, this bit is automatically reset to 0.
Caution The DCLK0 and DCLK1 bits should be manipulated in 8-bit units.
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(3) Oscillation stabilization time selection register (OSTS) This register can be read/written in 8-bit units.
After reset: 04H 7 OSTS 0 R/W 6 0 Address: FFFFF380H 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2
OSTS1
OSTS0 Clock
Selection of oscillation stabilization time fXX 20 MHz
Note
12.58 MHz 1.3 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms
0 0 0 0 1 Other than above
0 0 1 1 0
0 1 0 1 0
2 /fxx 216/fXX 2 /fXX 2 /fXX 2 /fXX Setting prohibited
19 18 17
14
819.2 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms
Note Only in the V850/SB1.
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6.4 Power Save Functions
6.4.1 Outline This product provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. (1) HALT mode When in this mode, the clock's oscillator continues to operate but the CPU's operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. This enables the system's total power consumption to be reduced. A dedicated instruction (the HALT instruction) is used to switch to HALT mode. (2) IDLE mode This mode stops the entire system by stopping the CPU's operating clock as well as the operating clock for onchip peripheral functions while the clock oscillator is still operating. However, the subclock continues to operate and supplies a clock to the on-chip peripheral functions. When this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. When the IDLE bit of the power saving control register (PSC) is set to 1, the system switches to IDLE mode. (3) Software STOP mode This mode stops the entire system by stopping the main clock oscillator. The subclock continues to be supplied to keep on-chip peripheral functions operating. If a subclock is not used, ultra low power consumption mode (leak current only) is set. STOP mode setting is prohibited if the CPU is operating via the subclock. If the STP bit of the PSC register is set to 1, the system enters STOP mode. (4) Subclock operation In this mode, the CPU clock is set to operate using the subclock and the MCK bit of the PCC register is set to 1 to set low power consumption mode in which the entire system operates using only the subclock. When IDLE mode is set, the CPU's operating clock and some peripheral functions (DMAC and BCU) are stopped, so that power consumption can be reduced even more than in HALT mode.
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6.4.2 HALT mode (1) Settings and operating states In this mode, the clock's oscillator continues to operate but the CPU's operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When HALT mode is set while the CPU is idle, it enables the system's total power consumption to be reduced. In HALT mode, execution of programs is stopped but the contents of all registers and on-chip RAM are retained as they were just before HALT mode was set. In addition, all on-chip peripheral functions that do not depend on instruction processing by the CPU continue operating. HALT mode can be set by executing the HALT instruction. It can be set when the CPU is operating on the main clock. The operating statuses in the HALT mode are listed in Table 6-1. (2) Release of HALT mode HALT mode can be released by an NMI request, an unmasked maskable interrupt request, or RESET input. (a) Release by interrupt request HALT mode is released regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs. However, the following occurs if HALT mode was set as part of an interrupt servicing routine. (i) Only HALT mode is released when an interrupt request that has a lower priority level than the interrupt currently being serviced occurs, and the lower-priority interrupt request is not acknowledged. interrupt request itself is retained. (ii) When an interrupt request (including NMI request) that has a higher priority level than the interrupt currently being serviced occurs, HALT mode is canceled and the interrupt request is acknowledged. (b) Release by RESET pin input This is the same as for normal reset operations. The
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Table 6-1. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting Item CPU ROM correction Clock generator When CPU Operates with Main Clock When Subclock Does Not Exist Stopped Stopped Oscillation for main clock and subclock Clock supply to CPU is stopped Operating Operating Operating Operating Operating Operating Operating Operating Operates when main clock is selected for count clock Operating (interval timer only) CSI0 to CSI3 I2C0Note, I2C1Note UART0, UART1 CSI4 IEBus (V850/SB2 only) A/D converter DMA0 to DMA5 Real-time output Operating Operating When Subclock Exists
16-bit timer (TM0) 16-bit timer (TM1) 8-bit timer (TM2) 8-bit timer (TM3) 8-bit timer (TM4) 8-bit timer (TM5) 8-bit timer (TM6) 8-bit timer (TM7) Watch timer
Watchdog timer Serial interface
Operating
Operating
Operating Operating Operating Operating Operating
2
Note Available only in the Y versions (products with on-chip I C).
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Table 6-1. Operating Statuses in HALT Mode (2/2)
HALT Mode Setting Item Port function External bus interface External interrupt request NMI INTP0 to INTP3 INTP4 and INTP5 INTP6 Key return function In external expansion mode AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB, WRL, WRH, RD ASTB HLDAK Operating Held Only bus hold function operates Operating Operating Operating Operating Operating High impedanceNote HeldNote (high impedance when HLDAK = 0) HeldNote (high impedance when HLDAK = 0) High level outputNote (high impedance when HLDAK = 0) When CPU Operates with Main Clock When Subclock Does Not Exist When Subclock Exists
Note Even when the HALT instruction has been executed, the instruction fetch operation continues until the on-chip instruction prefetch queue becomes full. Once it is full, operation stops according to the status shown in Table 6-1.
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6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the subclock continues. When this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. In IDLE mode, program execution is stopped and the contents of all registers and internal RAM are retained as they were just before IDLE mode was set. In addition, on-chip peripheral functions are stopped (except for peripheral functions that are operating with the subclock). acknowledged. When the IDLE bit of the power saving control register (PSC) is set to 1, the system switches to IDLE mode. The operating statuses in IDLE mode are listed in Table 6-2. (2) Release of IDLE mode IDLE mode can be released by a non-maskable interrupt, an unmasked interrupt request, or RESET input. Table 6-2. Operating Statuses in IDLE Mode (1/2)
IDLE Mode Settings Item CPU ROM correction Clock generator 16-bit timer (TM0) 16-bit timer (TM1) 8-bit timer (TM2) 8-bit timer (TM3) 8-bit timer (TM4) 8-bit timer (TM5) 8-bit timer (TM6) 8-bit timer (TM7) Watch timer Watchdog timer Serial interface CSI0 to CSI3 I C0
2 Note
External bus hold requests (HLDRQ) are not
When Subclock Exists
When Subclock Does Not Exist
Stopped Stopped Both main clock and subclock oscillator Clock supply to CPU and on-chip peripheral functions is stopped Operates when INTWTNI is selected as count clock (fXT is selected for watch timer) Stopped Stopped Stopped Operates when fXT is selected for count clock Operates when fXT is selected for count clock Stopped Stopped Stopped
Operates when TO0 is selected as count clock (however, only when TM0 is operating) Operates when TO0 is selected as count clock (however, only when TM0 is operating) Operating Stopped Operates when an external clock is selected as the serial clock Stopped Operates when an external clock is selected as the baud-rate clock (transmit only) Operates when an external clock is selected as the serial clock Stopped Stopped Stopped Operates when INTTM4 or INTTM5 is selected (when TM4 or TM5 is operating) Held
2
, I C1
2
Note
UART0, UART1 CSI4 IEBus (V850/SB2 only) A/D converter DMA0 to DMA5 Real-time output Port function
Stopped
Note Available only in the Y versions (products with on-chip I C).
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Table 6-2. Operating Statuses in IDLE Mode (2/2)
IDLE Mode Settings Item External bus interface External interrupt request NMI INTP0 to INTP3 Stopped Operating Operating When Subclock Exists When Subclock Does Not Exist
INTP4 and INTP5 Stopped INTP6 Operates when fXT is selected for sampling clock Operating AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB, WRL, WRH, RD ASTB HLDAK High impedance Stopped
Key return In external expansion mode
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6.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock. The subclock oscillator continues operating and the on-chip subclock supply is continued. When the FRC bit in the processor clock control register (PCC) is set to 1, the subclock oscillator's on-chip feedback resistor is cut. This sets ultra low power consumption mode in which the only current is the device's leak current. In this mode, program execution is stopped and the contents of all registers and internal RAM are retained as they were just before software STOP mode was set. On-chip peripheral functions also stop operating (peripheral functions operating on the subclock are not stopped). External bus hold requests (HLDRQ) are not acknowledged. This mode can be set only when the main clock is being used as the CPU clock. This mode is set when the STP bit in the power save control register (PSC) has been set to 1. Do not set this mode when the subclock has been selected as the CPU clock. The operating statuses for software STOP mode are listed in Table 6-3. (2) Release of software STOP mode Software STOP mode can be released by an non-maskable interrupt, an unmasked interrupt request, or RESET input. When the STOP mode is released, the oscillation stabilization time is secured. Table 6-3. Operating Statuses in Software STOP Mode (1/2)
STOP Mode Settings Stopped Stopped Oscillation for main clock is stopped and oscillation for subclock continues Clock supply to CPU and on-chip peripheral functions is stopped Operates when INTWTNI is selected for count clock (fXT is selected as count clock for watch timer) Stopped Stopped Stopped Operates when fXT is selected for count clock Operates when fXT is selected for count clock Stopped Stopped (operation disabled) Stopped When Subclock Exists When Subclock Does Not Exist
Item CPU ROM correction Clock generator
16-bit timer (TM0)
16-bit timer (TM1) 8-bit timer (TM2) 8-bit timer (TM3) 8-bit timer (TM4) 8-bit timer (TM5) 8-bit timer (TM6) 8-bit timer (TM7) Watch timer Watchdog timer Serial interface CSI0 to CSI3 I C0
2 Note
Operates when TO0 is selected as count clock (however, only when TM0 is operating) Operates when TO0 is selected as count clock (however, only when TM0 is operating) Operates when fXT is selected for count clock Stopped Operates when an external clock is selected as the serial clock Stopped Operates when an external clock is selected as the baud-rate clock (transmit only) Operates when an external clock is selected as the serial clock Stopped Stopped
2
Stopped
, I C1
2
Note
UART0, UART1 CSI4 IEBus (V850/SB2 only) A/D converter
Note Available only in the Y versions (products with on-chip I C).
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Table 6-3. Operating Statuses in Software STOP Mode (2/2)
Mode Settings Item DMA0 to DMA5 Real-time output Stopped Operates when INTTM4 or INTTM5 has been selected (when TM4 or TM5 is operating) Held Stopped Operating Operating Stopped Operates when fXT is selected for the noise eliminator Operating AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB, WRL, WRH, RD ASTB HLDAK High impedance Stopped Stopped When Subclock Exists When Subclock Does Not Exist
Port function External bus interface External interrupt request NMI INTP0 to INTP3 INTP4 and INTP5 INTP6
Key return In external expansion mode
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6.5 Oscillation Stabilization Time
The following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following release of STOP mode. (1) Release by non-maskable interrupt or by unmasked interrupt request STOP mode is released by a non-maskable interrupt or an unmasked interrupt request. When an interrupt is input, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse for stabilization of the oscillator's clock output. The oscillation stabilization time is set by the oscillation stabilization time select register (OSTS). Oscillation stabilization time WDT count time
After the specified amount of time has elapsed, system clock output starts and processing branches to the interrupt handler address. Figure 6-2. Oscillation Stabilization Time
STOP mode is set Oscillation wave
Main clock
STOP status
Interrupt input Oscillation stabilization time count
Oscillator is stopped
(2) Use of RESET pin to secure time (RESET pin input) For securing time with the RESET pin, refer to CHAPTER 15 RESET FUNCTION. The oscillation stabilization time is 2 /fXX according to the value of the OSTS register after reset.
19
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6.6
Notes on Power Save Function
(1) While an instruction is being executed on internal ROM To set the power save mode (IDLE mode or STOP mode) while an instruction is being executed on the internal ROM, insert a NOP instruction as a dummy instruction to correctly execute the routine after releasing the power save mode. The following shows the sequence of setting the power save mode. <1> <2> <3> <4> Disable DMA operation. Disable interrupts (set NP bit of PSW register to 1). Write 8-bit data to the command register (PRCMD). Write setting data to the power save control register (PSC) (using the following instructions). * * <5> <6> <7> Store instruction (ST/SST instruction) Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
Clear the interrupt disabled state (re-set the NP bit of the PSW register to 0). Insert NOP instructions (2 or 5 instructions). If DMA operation is necessary, enable DMA operation.
Cautions 1. Insert two NOP instructions if the ID bit value of the PSW is not changed by the execution of the instruction that clears the NP bit to 0 (<5>), and insert five NOP instructions (<6>) if it is changed. The following shows a description example. [Description example] : When using PSC register LDSR rX.5 ST.B r0, PRCMD[r0] ST.B rD, RSC[r0] LDSR rY, 5 NOP : NOP (next instruction) : Remark The above example assumes that rD (PSC set value), rX (value to be written to PSW), and rY (value rewritten to PSW) are already set. When saving the PSW value, transfer the PSW value before setting the NP bit to the rY register. 2. The instructions (<5> interrupt disable clear, <6> NOP instruction) following the store instruction (<4>) to the PSC register for setting the IDLE mode and STOP mode are executed before entering the power save mode. ; Execution routine after releasing IDLE/STOP mode ; NP bit = 1 ; Write to PRCMD ; PSC register setting ; NP bit = 0 ; Dummy instructions (2 or 5 instructions)
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(2) While an instruction is being executed on external ROM If the V850/SB1 or V850/SB2 is used under the following conditions, the address indicated by the program counter (PC) differs from the address that actually reads an instruction after the power save mode has been released. Of the instructions 4 to 16 bytes after the instruction that writes data to the PSC register, the CPU may ignore 4 or 8 bytes of the instruction and execute wrong instructions. Caution A PC discrepancy occurs only when all the conditions (i) to (iii) in [Conditions] below are met. It does not occur if even one condition is not met. [Conditions] (i) If the power save mode (IDLE or STOP mode) is set while an instruction is being executed on the external ROM (ii) If the power save mode is released by an interrupt request (iii) If the subsequent instruction is executed while an interrupt request is being held pending after the power save mode has been released Conditions in which an interrupt request is held pending: * If the NP flag of the PSW register is "1" (during NMI servicing/set by software) * If the ID flag of the PSW register is "1" (during interrupt request servicing/DI instruction/set by software) * If the power save mode is released by an interrupt request with a priority the same as or lower than the interrupt request being serviced even though interrupts are enabled (EI status) Therefore, use the V850/SB1 and V850/SB2 under the following conditions: [Conditions] (i) Do not use a power save mode (IDLE or STOP mode) while an instruction is being executed on the external ROM (ii) Take the following measures using software if a power save mode is used while an instruction is being executed on the external ROM: * Insert six NOP instructions 4 bytes after the instruction that writes data to the PSC register. * Insert the BR $+2 instruction to eliminate the discrepancy in the address of the PC after the NOP instructions.
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[Example of prevention program]
LDSR ST.B ST.B LDSR NOP NOP NOP NOP NOP BR $+2 ; Eliminates discrepancy of PC rx, 5 r0, PRCMD[r0] rD, PSC[r0] rY, 5 ; Sets value of rX to PSW. ; Writes data to PRCMD. ; Sets PSC register. ; Returns value of PSW. ; Six NOP instructions or more
Remark It is assumed that the following values have already been set: rD: PSC set value, rX: Value written to PSW, rY: Value written back to PSW
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7.1 16-Bit Timer (TM0, TM1)
7.1.1 Outline * 16-bit capture/compare registers: 2 (CRn0, CRn1) * Independent capture/trigger inputs: 2 (TIn0, TIn1) * Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) * Event input (shared with TIn0) via digital noise eliminator and support of edge specification * Timer output operated by match detection: 1 each (TOn) When using the P34/TO0 and P35/TO1 pins as TO0 and TO1 (timer outputs), set the value of port 3 (P3) to 0 (port mode output) and the port 3 mode register (PM3) to 0. The logical sum (ORed) value of the output of the port and the timer is output. Remark n = 0, 1
7.1.2 Function TM0 and TM1 have the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square wave output * One-shot pulse output Figure 7-1 shows the block diagram.
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Figure 7-1. Block Diagram of TM0 and TM1
Internal bus Capture/compare control register n (CRCn)
CRCn2 CRCn1 CRCn0 Selector
INTTMn0
TIn1
Noise eliminator
Selector
16-bit capture/compare register n0 (CRn0) Match
Count clockNote
Selector
16-bit timer register (TMn)
Clear
Output controller
TOn
fXX/2
Noise eliminator
Match 3
TIn0
Noise eliminator
16-bit capture/compare register n1 (CRn1) INTTMn1
Selector
CRCn2
Prescaler mode register n1 (PRMn1)
PRMn2 PRMn1 PRMn0 TMCn3 TMCn2 TMCn1 16-bit timer mode control register n (TMCn) OVFn OSPTn OSPEn TOCn4 LVSn
LVRn TOCn1 TOEn
Prescaler mode register n0 (PRMn0)
Timer output control register n (TOCn)
Internal bus
Note The count clock is set by the PRMn0 and PRMn1 registers. Remark n = 0, 1
(1) Interval timer Generates an interrupt at predetermined time intervals. (2) PPG output Can output a square wave whose frequency and output-pulse width can be changed arbitrarily. (3) Pulse width measurement Can measure the pulse width of a signal input from an external source. (4) External event counter Can measure the number of pulses of a signal input from an external source. (5) Square wave output Can output a square wave of any frequency. (6) One-shot pulse output Can output a one-shot pulse with any output pulse width.
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7.1.3 Configuration Timers 0 and 1 include the following hardware. Table 7-1. Configuration of Timers 0 and 1
Item Timer registers Registers Timer outputs Control registers 16 bits x 2 (TM0, TM1) 16-bit capture/compare registers: 16 bits x 2 each (CRn0, CRn1) 2 (TO0, TO1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Capture/compare control registers 0, 1 (CRC0, CRC1) 16-bit timer output control registers 0, 1 (TOC0, TOC1) Prescaler mode registers n0, n1 (PRMn0, PRMn1) Configuration
(1) 16-bit timer registers 0, 1 (TM0, TM1) TMn is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMCn3 and TMCn2 are cleared <3> If the valid edge of TIn0 is input in the clear & start mode entered by inputting the valid edge of TIn0 <4> If TMn and CRn0 match in the clear & start mode entered upon a match between TMn and CRn0 <5> If OSPTn is set or if the valid edge of TIn0 is input in the one-shot pulse output mode
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(2) 16-bit capture/compare registers n0 (CR00, CR10) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using the CRCn0 bit of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register. When the values of the two match, an interrupt request (INTTMn0) is generated. When TMn is used as an interval timer, CRn0 can also be used as a register that holds the interval time. (b) When using CRn0 as capture register The valid edge of the TIn0 or TIn1 pin can be selected as a capture trigger. The valid edge of TIn0 or TIn1 is set by using the PRMn0 register. When the valid edge of the TIn0 pin is specified as the capture trigger, refer to Table 7-2. When the valid edge of the TIn1 pin is specified as the capture trigger, refer to Table 7-3. Table 7-2. Valid Edge of TIn0 Pin and Capture Trigger of CRn0
ESn01 0 0 1 1 ESn00 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid Edge of TIn0 Pin Rising edge Falling edge Setting prohibited No capture operation CRn0 Capture Trigger
Remark n = 0, 1 Table 7-3. Valid Edge of TIn1 Pin and Capture Trigger of CRn0
ESn11 0 0 1 1 ESn10 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid Edge of TIn1 Pin Falling edge Rising edge Setting prohibited Both rising and falling edges CRn0 Capture Trigger
Remark n = 0, 1 CRn0 is set by using a 16-bit memory manipulation instruction. These registers can only be read by a 16-bit memory manipulation instruction when used as capture registers. RESET input clears CRn0 to 0000H. Caution Set CRn0 to a value other than 0000H in the clear & start mode entered upon a match between TMn and CRn0. In the free-running mode or the clear & start mode entered upon the TIn0 valid edge, however, an interrupt request (INTTMn0) is generated after an overflow (FFFFH) when CRn0 is set to 0000H.
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(3) 16-bit capture/compare register n1 (CR01, CR11) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by the CRCn2 bit of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn. When the values of the two match, an interrupt request (INTTMn1) is generated. (b) When using CRn1 as capture register The valid edge of the TIn1 pin can be selected as a capture trigger. The valid edge of TIn1 is specified by the PRMn0 register. When the capture trigger is specified as the valid edge of TIn0, the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows. Table 7-4. TIn0 Pin Valid Edge and CRn1 Capture Trigger
ESn01 0 0 1 1 ESn00 0 1 0 1 TIn0 Pin Valid Edge Falling edge Rising Edge Setting prohibited Both rising and falling edges CRn1 Capture Trigger Falling edge Rising Edge Setting prohibited Both rising and falling edges
Remark
n = 0, 1
CRn1 is set by using a 16-bit memory manipulation instruction. These registers can only be read by a 16-bit memory manipulation instruction when used as capture registers. RESET input clears CRn1 to 0000H. Caution Set CRn1 to a value other than 0000H in the clear & start mode entered upon a match between TMn and CRn0. In the free-running mode or the clear & start mode entered upon the TIn0 valid edge, however, an interrupt request (INTTMn1) is generated after an overflow (FFFFH) when CRn1 is set to 0000H.
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7.1.4 Timer 0, 1 control registers The registers to control timers 0 and 1 are shown below. * 16-bit timer mode control register n (TMCn) * Capture/compare control register n (CRCn) * 16-bit timer output control register n (TOCn) * Prescaler mode registers n0, n1 (PRMn0, PRMn1) The following registers are also used. * 16-bit timer register n (TMn) * 16-bit capture/compare registers n0, n1 (CRn0, CRn1) (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) TMCn specifies the operation mode of the 16-bit timer, and the clear mode, output timing, and overflow detection of 16-bit timer register n (TMn). TMCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears TMC0 and TMC1 to 00H. Caution 16-bit timer register n starts operating when the TMCn2 and TMCn3 bits are set to values other than 0, 0 (operation stop mode). To stop the operation, set the TMCn2 and TMCn3 bits to 0, 0.
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After reset: 00H 7 TMCn 0
R/W 6 0
Address: FFFFF208H, FFFFF218H 5 0 4 0 3 TMCn3 2 TMCn2 1 TMCn1 <0> OVFn
(n = 0, 1)
TMCn3 TMCn2 TMCn1 Operation mode and clear mode selector Operation stops (TMn is cleared to 0) TOn output timing selector Not affected Generation of interrupt
0
0
0
Not generated
0 0
0 1
1 0 Free-running mode Match between TMn and CRn0 or match between TMn and CRn1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 Clears and starts at valid edge of TIn0 Match between TMn and CRn0 or match between TMn and CRn1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 Clears and starts on match between TMn and CRn0 Match between TMn and CRn0 or match between TMn and CRn1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 Generated on match between TMn and CRn0 and match between TMn and CRn1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OVFn 0 1 Did not overflow Overflowed
Detection of overflow of 16-bit timer register n
Cautions 1. When a bit other than the OVFn bit is written, be sure to stop the timer operation. 2. The valid edge of the TIn0 pin is set by using prescaler mode register n0 (PRMn0). 3. When a mode in which the timer is cleared and started on a match between TMn and CRn0 is selected, the OVFn bit is set to 1 when the count value of TMn changes from FFFFH to 0000H with CRn0 set to FFFFH. 4. Be sure to set bits 4 to 7 to 0. Remark TOn: TIn0: TMn: Output pin of timer n Input pin of timer n 16-bit timer register n
CRn0: Compare register n0 CRn1: Compare register n1
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(2) Capture/compare control registers 0, 1 (CRC0, CRC1) CRCn controls the operation of 16-bit capture/compare register n (CRn0 and CRn1). CRCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0 and CRC1 to 00H.
After reset: 00H R/W 7 CRCn (n = 0, 1) CRCn2 0 1 Selection of operation mode of CRn1 Operates as compare register Operates as capture register 0 6 0 Address: FFFFF20AH, FFFFF21AH 5 0 4 0 3 0 2 CRCn2 1 CRCn1 0 CRCn0
CRCn1 0 1
Selection of capture trigger of CRn0 Captured at valid edge of TIn1 Captured in reverse phase of valid edge of TIn0
CRCn0 0 1
Selection of operation mode of CRn0 Operates as compare register Operates as capture register
Cautions 1. Before setting CRCn, be sure to stop the timer operation. 2. When the mode in which the timer is cleared and started on a match between TMn and CRn0 is selected by 16-bit timer mode control register n (TMCn), do not specify CRn0 as a capture register. 3. When both the rising edge and falling edge are specified for the TIn0 valid edge, the capture operation does not work for the CRn0 register. 4. For the capture trigger, a pulse longer than twice the count clock selected by prescaler mode registers 0n, 1n (PRM0n, PRM1n) is required in order that the signals from TIn0 and T2n1 perform the capture operation correctly. 5. Be sure to set bits 3 to 7 to 0.
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(3) 16-bit timer output control registers 0, 1 (TOC0, TOC1) TOCn controls the operation of the timer n output controller by setting or resetting the R-S flip-flop (LV0), enabling or disabling reverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting the output trigger for the one-shot pulse by software. TOCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears TOC0 and TOC1 to 00H.
After reset: 00H R/W 7 TOCn (n = 0, 1) OSPTn 0 1 Control of output trigger of one-shot pulse by software No one-shot pulse trigger Uses one-shot pulse trigger 0 <6> OSPTn Address: FFFFF20CH, FFFFF21CH <5> OSPEn 4 TOCn4 <3> LVSn <2> LVRn 1 TOCn1 <0> TOEn
OSPEn 0 1
Control of one-shot pulse output operation Successive pulse output One-shot pulse outputNote
TOCn4 0 1
Control of timer output F/F on match between CRn1 and TMn Reverse timer output F/F disabled Reverse timer output F/F disabled
LVSn 0 0 1 1
LVRn 0 1 0 1
Setting of status of timer output F/F of timer n Not affected Resets timer output F/F (0) Sets timer output F/F (1) Setting prohibited
TOCn1 0 1
Control of timer output F/F on match between CRn0 and TMn or TIn0 valid edge Reverse timer output F/F disabled Reverse timer output F/F enabled
TOEn 0 1
Controls output of timer n Output disabled (output is fixed to 0 level) Output enabled
Note The one-shot pulse output operates only in the free-running mode and in the clear & start mode set by the TIn0 valid edge. Cautions 1. Before setting TOCn, be sure to stop the timer operation. 2. LVSn and LVRn are 0 when read after data has been set to them. 3. OSPTn is 0 when read because it is automatically cleared after data has been set. 4. Do not set OSPTn (to 1) other than for one-shot pulse output (OSPEn bit = 0).
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(4) Prescaler mode registers 00, 01 (PRM00, PRM01) PRM0n selects the count clock of the 16-bit timer (TM0) and the valid edge of TI0n input. PRM00 and PRM01 are set by an 8-bit memory manipulation instruction. RESET input clears PRM00 and PRM01 to 00H.
After reset: 00H R/W 7 PRM00 ES011 6 ES010 Address: FFFFF206H 5 ES001 4 ES000 3 0 2 0 1 PRM01 0 PRM00
After reset: 00H R/W 7 PRM01 0 6 0
Address: FFFFF20EH 5 0 4 0 3 0 2 0 1 0 0 PRM02
ES011 0 0 1 1
ES010 0 1 0 1 Falling edge Rising edge Setting prohibited
Selection of valid edge of TI01
Both rising and falling edges
ES001 0 0 1 1
ES000 0 1 0 1 Falling edge Rising edge Setting prohibited
Selection of valid edge of TI00
Both rising and falling edges
PRM02
PRM01
PRM00
Count clock selection Count clock 20 MHz
Note 2
fXX 12.58 MHz 158 ns 1.3 s - - 318 ns 5.1 s 20.3 s -
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fXX/2 fXX/16 INTWTNI TI00 valid edge fXX/4 fXX/64 fXX/256 Setting prohibited
Note 1
100 ns 800 ns - - 200 ns 3.2 s 12.8 s -
Notes 1. The external clock requires a pulse longer than twice that of the internal clock (fXX/2). 2. Only in the V850/SB1. Cautions 1. When selecting the valid edge of TI00 as the count clock, do not specify the clear & start mode entered on the valid edge of TI00 or TI00 as a capture trigger. 2. Before setting data to PRM0n, always stop the timer operation. 3. If the 16-bit timer (TM0) operation is enabled by specifying the rising edge or both edges as the valid edge of the TI0n pin while the TI0n pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. Be careful when pulling up the TI0n pin. However, the rising edge is not detected when operation is enabled after it has been stopped.
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(5) Prescaler mode registers 10, 11 (PRM10, PRM11) PRM1n selects the count clock of the 16-bit timer (TM1) and the valid edge of TI1n input. PRM10 and PRM11 are set by an 8-bit memory manipulation instruction. RESET input clears PRM10 and PRM11 to 00H.
After reset: 00H R/W 7 PRM10 ES111 6 ES110 Address: FFFFF216H 5 ES101 4 ES100 3 0 2 0 1 PRM11 0 PRM10
After reset: 00H R/W 7 PRM11 0 6 0
Address: FFFFF21EH 5 0 4 0 3 0 2 0 1 0 0 PRM12
ES111 0 0 1 1
ES110 0 1 0 1 Falling edge Rising edge Setting prohibited
Selection of valid edge of TI11
Both rising and falling edges
ES101 0 0 1 1
ES100 0 1 0 1 Falling edge Rising edge Setting prohibited
Selection of valid edge of TI10
Both rising and falling edges
PRM12
PRM11
PRM10
Count clock selection Count clock 20 MHz
Note 2
fXX 12.58 MHz 158 ns 318 ns 1.3 s - 2.5 s 10.2 s 20.3 s - -
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fXX/2 fXX/4 fXX/16 TI10 valid edge fXX/32 fXX/128 fXX/256 Setting prohibited
Note 1
100 ns 200 ns 800 ns - 1.6 s 6.4 s 12.8 s
Notes 1. The external clock requires a pulse longer than twice that of the internal clock (fXX/2). 2. Only in the V850/SB1. Cautions 1. When selecting the valid edge of TI10 as the count clock, do not specify the clear & start mode entered on the valid edge of TI10 or TI10 as a capture trigger. 2. Before setting data to PRM1n, always stop the timer operation. 3. If the 16-bit timer (TM1) operation is enabled by specifying the rising edge or both edges as the valid edge of the TI1n pin while the TI1n pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. Be careful when pulling up the TI1n pin. However, the rising edge is not detected when operation is enabled after it has been stopped.
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7.2 16-Bit Timer Operation
7.2.1 Operation as interval timer (16 bits) TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 7-2 (n = 0, 1). In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0). When the count value of TMn matches with the set value of CRn0, the value of TMn is cleared to 0, and the timer continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. The count clock of the 16-bit timer/event counter can be selected by the PRMn0 and PRMn1 bits of prescaler mode register n0 (PRMn0) and by the PRMn2 bit of prescaler mode register n1 (PRMn1). Figure 7-2. Control Register Settings When TMn Operates as Interval Timer (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0/1 OVFn 0
Clears and starts on match between TMn and CRn0.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 0
CRn0 used as compare register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the interval timer function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1).
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Figure 7-3. Configuration of Interval Timer
16-bit capture/compare register n0 (CRn0)
INTTMn0
Count clockNote Selector TIn0 Noise eliminator Clear circuit fXX/2 16-bit timer register n (TMn) OVFn
Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0, 1 Figure 7-4. Timing of Interval Timer Operation
t Count clock TMn count value
0000H 0001H
N
0000H
0001H
N
0000H
0001H
N
Count start CRn0 INTTMn0 N
Clear N
Clear N N
Interrupt acknowledgment TOn Interval time Interval time
Interrupt acknowledgment
Interval time
Remarks 1. Interval time = (N + 1) x t: N = 0001H to FFFFH 2. n = 0,1
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7.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 7-5. The PPG output function outputs a square wave from the TOn pin with a cycle specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value set in advance to 16-bit capture/compare register n1 (CRn1). Figure 7-5. Control Register Settings in PPG Output Operation (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0 OVFn 0
Clears and starts on match between TMn and CRn0.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0 CRCn1 x CRCn0 0 x: don't care
CRn0 used as compare register CRn1 used as compare register
(c) 16-bit timer output control registers 0, 1 (TOC0, TOC1)
OSPTn TOCn 0 0 OSPEn 0 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1
Enables TOn output. Reverses output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Reverses output on match between TMn and CRn1. Disables one-shot pulse output.
Cautions 1. Make sure that CRn0 and CRn1 are set to 0000H < CRn1 < CRn0 FFFFH. 2. PPG output sets the pulse cycle to (CRn0 set value + 1). The duty factor is (CRn1 set value + 1)/(CRn0 set value + 1).
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Figure 7-6. Configuration of PPG Output
16-bit capture/compare register n0 (CRn0)
Selector
Count clockNote TIn0 Noise eliminator fxx/2
16-bit timer register n (TMn)
Clear circuit
Output controller
TOn
16-bit capture/compare register n1 (CRn1)
Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0, 1 Figure 7-7. PPG Output Operation Timing
t
Count clock TMn count value 0000H 0001H Count starts Value loaded to CRn0 Value loaded to CRn1 TOn Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H
Clear
Remarks 1. 0000H M < N FFFFH 2. n = 0, 1
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7.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin. (1) Pulse width measurement with free-running counter and one capture register If the edge specified by prescaler mode register n0 (PRMn0) is input to the TIn0 pin when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-8), the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set. The edge is specified by using bits 6 and 7 (ESn10 and ESn11) of prescaler mode register n0 (PRMn0). The rising edge, falling edge, or both the rising and falling edges can be selected. The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n0, n1 (PRMn0, PRMn1), and a capture operation is not performed until the valid level is detected two times. Therefore, noise with a short pulse width can be eliminated. Figure 7-8. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0
Free-running mode
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 1 CRCn1 0/1 CRCn0 0
CRn0 used as compare register CRn1 used as capture register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1).
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Figure 7-9. Configuration for Pulse Width Measurement with Free-Running Counter
Count clockNote
Selector
16-bit timer register n (TMn)
OVFn
TIn0
16-bit capture/compare register n1 (CRn1) INTTMn1 Internal bus
Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0, 1 Figure 7-10. Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified)
t Count clock TMn count value TIn0 pin input Value loaded to CRn1 INTTMn1
OVFn
D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
Remark
n = 0, 1
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(2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-11). When the edge specified by the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of the TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set. When the edge specified by the ESn10 and ESn11 bits in PRMn0 is input to the TIn1 pin, the value of TMn is loaded to 16-bit capture/compare register n0 (CRn0), and an external interrupt request signal (INTTMn0) is set. The edges of the TIn0 and TIn1 pins are specified by the ESn00 and ESn01 bits and the ESn10 and ESn11 bits of PRMn0, respectively. The rising, falling, or both rising and falling edges can be specified. The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n0, n1 (PRMn0, PRMn1), and a capture operation is not performed until the valid level is detected two times. Therefore, noise with a short pulse width can be eliminated. Figure 7-11. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0
Free-running mode
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 1 CRCn1 0 CRCn0 1
CRn0 used as capture register Captures valid edge of TIn1 pin to CRn0. CRn1 used as capture register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. CRC1). For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0,
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* Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-12. CRn1 Capture Operation with Rising Edge Specified
Count clock TMn TIn0 Rising edge detection CRn1 INTTMn1 N N-3 N-2 N-1 N N+1
Remark n = 0, 1 Figure 7-13. Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified)
t Count clock TMn count value TIn0 pin input Value loaded to CRn1 INTTMn1 TIn1 pin input Value loaded to CRn0 INTTMn0 OVFn (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1) x t (D3 - D2) x t
D1 D2 + 1 D0 D1 D2
0000H 0001H
D0
D0 + 1
D1 D1 + 1
FFFFH 0000H
D2
D2 + 1 D2 + 2
D3
Remark n = 0, 1
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(3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 7-14), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set. The value of TMn is also loaded to 16-bit capture/compare register n0 (CRn0) when an edge reverse to the one that triggers capturing to CRn1 is input. The edge of the TIn0 pin is specified by the ESn00 and ESn01 bits of prescaler mode register n (PRMn0). The rising or falling edge can be specified. The valid edge of TIn0 is detected by sampling at the count clock cycle selected by prescaler mode register n0, n1 (PRMn0, PRMn1), and a capture operation is not performed until the valid level is detected two times. Therefore, noise with a short pulse width can be eliminated. Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges, capture/compare register n0 (CRn0) cannot perform its capture operation. Figure 7-14. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0
Free-running mode
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 1 CRCn1 1 CRCn0 1
CRn0 used as capture register Captures to CRn0 at edge reverse to valid edge of TIn0 pin. CRn1 used as capture register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. CRC1). For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0,
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Figure 7-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
t Count clock TMn count value TIn0 pin input Value loaded to CRn1 Value loaded to CRn0 INTTMn1 OVFn (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t
D0 D2
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1
D3
D1
D3
Remark n = 0, 1 (4) Pulse width measurement by restarting When the valid edge of the TIn0 pin is detected, the pulse width of the signal input to the TIn0 pin can be measured by clearing 16-bit timer register n (TMn) once and then resuming counting after loading the count value of TMn to 16-bit capture/compare register n1 (CRn1). (See Figure 7-17) The edge is specified by the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0). The rising or falling edge can be specified. The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n0, n1 (PRMn0, PRMn1) and a capture operation is not performed until the valid level is detected two times. Therefore, noise with a short pulse width can be eliminated. Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges, 16-bit capture/compare register n0 (CRn0) cannot perform its capture operation.
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Figure 7-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 0 TMCn1 0/1 OVFn 0
Clears and starts at valid edge of TIn0 pin.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 1 CRCn1 1 CRCn0 1
CRn0 used as capture register Captures to CRn0 at edge reverse to valid edge of TIn0. CRn1 used as capture register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1).
Figure 7-17. Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified)
t Count clock TMn count value TI0n0 pin input Value loaded to CRn1 Value loaded to CRn0 INTTM0n1 (D1 + 1) x t (D2 + 1) x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H
Remark n = 0, 1
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7.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n0 (PRMn0) has been input, TMn is incremented. When the count value of TMn matches with the value of 16-bit capture/compare register n0 (CRn0), TMn is cleared to 0, and an interrupt request signal (INTTMn0) is generated. The edge is specified by ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0). The rising, falling, or both the rising and falling edges can be specified. The valid edge is detected through sampling at a count clock cycle of fXX/2, and the capture operation is not performed until the valid level is detected two times. Therefore, noise with a short pulse width can be removed. Figure 7-18. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0/1 OVFn 0
Clears and starts on match between TMn and CRn0.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 0
CRn0 as compare register
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1).
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Figure 7-19. Configuration of External Event Counter
16-bit capture/compare register n (CRn0) Match Clear Count clockNote Selector 16-bit timer/counter n (TMn) OVFn INTTMn0
fXX/2 Valid edge of TIn0
Noise eliminator 16-bit capture/compare register n1 (CRn1)
Internal bus
Note The count clock is set by the PRMn0 and PRMn1 registers. Remarks 1. " " indicates a signal that can be directly connected to a port.
2. n = 0, 1 Figure 7-20. Timing of External Event Counter Operation (with Rising Edge Specified)
TIn0 pin input TMn count value CRn0 INTTMn0
0000H 0001H 0002H 0003H 0004H 0005H
N-1
N
0000H 0001H 0002H 0003H
N
Caution Remark
Read TMn when reading the count value of the external event counter. n = 0, 1
7.2.5 Operation to output square wave TMn can be used to output a square wave with any frequency at the interval specified by the count value set in advance to 16-bit capture/compare register n0 (CRn0). By setting the TOEn and TOCn1 bits of 16-bit timer output control register n (TOCn) to 1, the output status of the TOn pin is reversed at the interval specified by the count value set in advance to CRn1. In this way, a square wave of any frequency can be output.
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Figure 7-21. Control Register Settings in Square Wave Output Mode (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0 OVFn 0
Clears and starts on match between TMn and CRn0.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 1
CRn0 used as compare register
(c) 16-bit timer output control registers 0, 1 (TOC0, TOC1)
OSPTn TOCn 0 0 OSPEn 0 TOCn4 0 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1
Enables TOn output. Reverses output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Does not reverse output on match between TMn and CRn1. Disables one-shot pulse output.
Remark
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the square wave output function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1), 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1), and 7.1.4 (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1).
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Figure 7-22. Timing of Square Wave Output Operation
Count clock TMn count value CRn0 INTTMn0 TOn pin output
0000H 0001H 0002H
N-1
N
0000H 0001H 0002H
N-1
N
0000H
N
Remark
n = 0, 1
7.2.6 Operation to output one-shot pulse TMn can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TOn pin by setting 16-bit timer mode control register n (TMCn), capture/compare control register n (CRCn), and 16-bit timer output control register n (TOCn) as shown in Figure 7-23, and by setting the OSPTn bit of TOCn by software. By setting OSPTn to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted at the count value (N) set in advance to 16-bit capture/compare register n1 (CRn1). After that, the output is deasserted at the count value (M) set in advance to 16-bit capture/compare register n0 (CRn0) to 00H. Note This is an example when N < M. When N > M, the output is asserted by CRn0 and deasserted by CRn1. Caution Do not set OSPTn to 1 while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is complete.
Note
.
Even after the one-shot pulse has been output, TMn continues its operation. To stop TMn, TMCn must be reset
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Figure 7-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0 OVFn 0
Free-running mode
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0 CRCn1 0/1 CRCn0 0
CRn0 used as compare register CRn1 used as compare register
(c) 16-bit timer output control registers 0, 1 (TOC0, TOC1)
OSPTn TOCn 0 0 OSPEn 1 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1
Enables TOn output. Reverses output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Reverses output on match between TMn and CRn1. Sets one-shot pulse output mode. Set to 1 for output.
Caution Remark
Do not set CRn0 and CRn1 to 0000H. 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the one-shot pulse output function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1), 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1), and 7.1.4 (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1).
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Figure 7-24. Timing of One-Shot Pulse Output Operation with Software Trigger
Sets 0CH to TMCn (TMn count starts) Count clock TMn count value
CRn1 set value
0000H 0001H N N+1
0000H
N-1
N
M-1
M
M+1
M+2
N M
N M
N M
N M
CRn0 set value OSPTn INTTMn1
INTTMn0
TOn pin output
Caution 16-bit timer register n starts operating as soon as TMCn2 and TMCn3 have been set to values other than 0, 0 (operation stop mode). Remark n = 0, 1 NNote
.
Note This is an example when N < M. When N > M, the output is asserted by CRn0 and deasserted by CRn1. Caution If an external trigger occurs while a one-shot pulse is being output, the 16-bit timer/event counter is cleared and started and a one-shot pulse is output again.
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Figure 7-25. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
TMCn3 TMCn 0 0 0 0 1 TMCn2 0 TMCn1 0 OVFn 0
Clears and starts at valid edge of TIn0 pin.
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
CRCn2 CRCn 0 0 0 0 0 0 CRCn1 0/1 CRCn0 0
CRn0 used as compare register CRn1 used as compare register
(c) 16-bit timer output control registers 0, 1 (TOC0, TOC1)
OSPTn TOCn 0 0 OSPEn 1 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1
Enables TOn output. Reverses output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Reverses output on match between TMn and CRn1. Sets one-shot pulse output mode.
Caution Do not set CRn0 and CRn1 to 0000H. Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the one-shot pulse output function. For details, refer to 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1), 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1), and 7.1.4 (3) 16-bit timer output control registers 0, 1 (TOC0, TOC1).
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Figure 7-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
Sets 08H to TMCn (TMn count starts) Count clock TMn count value Value to set CRn1 Value to set CRn0 TIn0 pin input INTTMn1 INTTMn0 TOn pin output
0000H 0001H 0000H
N
N+1
N+2
M-2
M-1
M
M+1 M+2
N
N
N
N
M
M
M
M
Caution 16-bit timer register n starts operating as soon as TMCn2 and TMCn3 have been set to values other than 0, 0 (operation stop mode). Remark n = 0, 1 NUser's Manual U13850EJ6V0UD
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7.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 7-27. Start Timing of 16-Bit Timer Register n
Count pulse TMn count value 0000H Timer starts 0001H 0002H 0003H 0004H
Remark n = 0, 1 (2) 16-bit capture/compare register setting (clear & start mode on match between TMn and CRn0) Set 16-bit capture/compare registers n0, n1 (CRn0, CRn1) to a value other than 0000H (the 1-pulse count operation is disabled when these registers are used as event counters). (3) Setting compare register during timer count operation If the value to which the current value of 16-bit capture/compare register n0 (CRn0) has been changed is less than the value of 16-bit timer register n (TMn), TMn continues counting, overflows, and starts counting again from 0. If the new value of CRn0 (M) is less than the old value (N), the timer must be reset and then restarted after the value of CRn0 has been changed. Figure 7-28. Timing After Changing Compare Register During Timer Count Operation
Count pulse CRn0 TMn count value N X-1 X M FFFFH 0000H 0001H 0002H
Remarks 1. N > X > M 2. n = 0, 1
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(4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1 performs the capture operation, but this read value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge. Figure 7-29. Data Hold Timing of Capture Register
Count pulse TMn count value Edge input N N+1 N+2 M M+1 M+2
INTTMn1 Capture read signal CRn1 interrupt value X Capture operation N+1
A capture operation is performed but the read value is not guaranteed.
Remark n = 0, 1 (5) Setting valid edge Before setting the valid edge of the TIn0 pin, stop the timer operation by resetting the TMCn2 and TMCn3 bits of 16-bit timer mode control register n to 0, 0. Set the valid edge by using the ESn00 and ESn01 bits of prescaler mode register n0 (PRMn0). (6) Re-triggering one-shot pulse (a) One-shot pulse output by software When a one-shot pulse is being output, do not set OSPTn to 1. Do not output the one-shot pulse again until the current one-shot pulse output ends. (b) One-shot pulse output with external trigger If an external trigger occurs while a one-shot pulse is being output, the 16-bit timer/event counter is cleared and started and a one-shot pulse is output again. (c) One-shot pulse output function When using the one-shot pulse output function of timer 0 or 1 by software trigger, do not change the level of the TIn0 pin or the pin multiplexed with it. Even in this case, the external trigger remains valid. Consequently, the timer is cleared and started by the level of the TIn0 pin or the pin multiplexed with it, and a pulse is output when it is not expected.
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(7) Operation of OVFn bit (a) OVFn bit set The OVFn bit is set to 1 in the following case in addition to when the TMn register overflows: Select the mode in which the timer is cleared and started on a match between TMn and CRn0 or the mode in which it is cleared and started by the valid edge of TIn0. Set CRn0 to FFFFH. When TMn is cleared from FFFFH to 0000H on a match with the CRn0 register Figure 7-30. Operation Timing of OVFn Bit
Count pulse CRn0 TMn OVFn INTTMn0 FFFFH FFFEH FFFFH 0000H 0001H
Remark n = 0, 1 (b) Clear OVFn bit Even if the OVFn bit is cleared before the next count clock is counted (before TMn become 0001H) after TMn has overflowed, the OVFn flag is set again and the clear becomes invalid. (8) Conflict operation (a) If the read period and capture trigger input conflict When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, if the read period and capture trigger input conflict, the capture trigger has priority. The read data of CRn0 and CRn1 is undefined. (b) If the match timings of the write period and TMn conflict When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, because match detection cannot be performed correctly if the match timings of the write period and 16-bit timer register n (TMn) conflict, do not write to CRn0 and CRn1 close to the match timing. (9) Timer operation (a) CRn1 capture Even if 16-bit timer register n (TMn) is read, a capture to 16-bit capture/compare register n1 (CRn1) is not performed. (b) Acknowledgment of TIn0 and TIn1 pins When the timer is stopped, input signals to the TIn0 and TIn1 pins are not acknowledged, regardless of the CPU operation.
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(c) One-shot pulse output The one-shot pulse output operates correctly only in free-running mode or in clear & start mode at the valid edge of the TIn0 pin. The one-shot pulse cannot be output in the clear & start mode on a match of TMn and CRn0 because an overflow does not occur. (10) Capture operation (a) If the valid edge of TIn0 is specified for the count clock When the valid edge of TIn0 is specified for the count clock, the capture register with TIn0 specified as a trigger will not operate correctly. (b) If both rising and falling edges are selected as valid edge of TIn0 If the CRn0 register capture trigger is set to the inverse phase of the valid edge of TIn0 and both the rising and falling edges are selected as the valid edge of TIn0, a capture operation is not performed. (c) To capture the signals correctly from TIn0 and TIn1 The capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 (PRMn0, PRMn1) in order to correctly capture the signals from TIn1 and TIn0. (d) Interrupt request input Although a capture operation is performed a the falling edge of the count clock, interrupt request inputs (INTTMn0, INTTMn1) are generated at the rising edge of the next count clock. (11) Compare operation (a) When rewriting CRn0 and CRn1 during timer operation When rewriting 16-bit timer capture/compare registers n0 and n1 (CRn0, CRn1), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) When CRn0 and CRn1 are set to compare mode When CRn0 and CRn1 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. (12) Edge detection (a) When the TIn0 or TIn1 pin is high level immediately after a system reset When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (TMn) is then enabled, the rising edge will be detected immediately. Care is therefore needed when the TIn0 or TIn1 pin is pulled up. However, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the TIn0 valid edge is used as a count clock or a capture trigger. The former is sampled by fXX/2, and the latter is sampled by the count clock selected using prescaler mode registers n0 or n1 (PRMn0, PRMn1). Detecting the valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice.
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7.3 8-Bit Timer (TM2 to TM7)
7.3.1 Outline * 8-bit compare registers: 8 (CRn0) Can be used as 16-bit compare registers by connecting in cascade (2 max.). * Compare match/overflow interrupt request signal (INTTMn) output enabled * Event input (TIm) count enabled * Timer outputs that operate on match detection: 1 each (TOm) If using the P26/TI2/TO2, P27/TI3/TO3, P36/TI4/TO4, and P37/TI5/TO5 pins as the TO2 to TO5 pins (timer outputs), set the value of ports 2 and 3 (P2, P3) to 0 (low-level output) and the value of the port 2 and 3 mode registers (PM2, PM3) to 0 (port output mode). The logical sum (OR) of the output value of the port and the timer is output. Since the TOn pin and TIn pin share a pin, one or other of these functions (but not both) can be used. Remark n = 2 to 7, m = 2 to 5 7.3.2 Functions 8-bit timer n has the following two modes (n = 2 to 7). * Mode using timer alone (individual mode) * Mode using cascade connection (16-bit resolution: cascade connection mode) Caution Do not access following registers when not using the cascade connection. * 16-bit counters (TM23, TM45, TM67) * 16-bit compare registers (CR23, CR45, CR67) The two modes are described next. (1) Mode using timer alone (individual mode) The timer operates as an 8-bit timer/event counter. It can have the following functions. * Interval timer * External event counter * Square wave output * PWM output (2) Mode using cascade connection (16-bit resolution: cascade connection mode) The timer operates as a 16-bit timer/event counter by connecting TM2 and TM3 or TM4 and TM5 in cascade. It can have the following functions. * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square wave output with 16-bit resolution The timer operates as a 16-bit timer/event counter by connecting TM6 and TM7 in cascade. * Interval timer with 16-bit resolution
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Figure 7-31. Block Diagram of TM2 to TM7
Internal bus
8-bit compare register n (CRn0) Match TIm Count clockNote 1
Selector
Selector Mask circuit
S Q INV R
INTTMn Note 2
Selector
8-bit counter n OVF (TMn) Clear
TOm
/4
S Selector R
Q
Invert level
TCLn3
TCLn2 TCLn1 Timer clock selection register n0, n1 (TCLn0, TCLn1)
TCLn0
TCEn
TMCn6 TMCn4 LVSm
LVRm TMCm1 TOEm
Timer mode control n0, n1 (TCLn0, TCLn1)
Internal bus
Notes 1. The count clock is set by the TCLn register. 2. Clock of serial interface (TM2 and TM3 only) Remarks 1. " ]" is a signal that can be directly connected to a port.
2. n = 2 to 7, m = 2 to 5 7.3.3 Configuration Timer n includes the following hardware. Table 7-5. Configuration of Timers 2 to 7
Item Timer registers Configuration 8-bit counters 2 to 7 (TM2 to TM7) 16-bit counters 23, 45, 67 (TM23, TM45, TM67): Only when connecting in cascade 8-bit compare registers 2 to 7 (CR20 to CR70) 16-bit compare registers 23, 45, 67 (CR23, CR45, CR67): Only when connecting in cascade TO2 to TO5 Timer clock selection registers 20 to 70 and 21 to 71 (TCL20 to TCL70 and TCL21 to TCL71) 8-bit timer mode control registers 2 to 7 (TMC2 to TMC7)
Registers
Timer outputs Control registers
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(1) 8-bit counters 2 to 7 (TM2 to TM7) TMn is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. TM2 and TM3 or TM5 and TM6 can be connected in cascade and used as 16-bit timers. When TMm and TMm+1 are connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. However, since they are connected via the internal 8-bit bus, TMm and TMm+1 are read separately. Consequently, they should be read twice and compared to allow for count variation. When the count is read out during operation, the count clock input temporarily stops and the count is read at that time. In the following cases, the count becomes 00H. (1) RESET is input. (2) TCEn is cleared. (3) TMn and CRn0 match in the clear and start mode that occurs when TMn and CRn0 match. Caution When connected in cascade, these registers become 00H even when TCEn in the lower timers (TM2, TM4, TM6) is cleared. Remark n = 2 to 7 m = 2, 4, 6 (2) 8-bit compare registers 2 to 7 (CR20 to CR70) The CRn0 register is set by an 8-bit memory manipulation instruction. The value set in CRn0 is always compared to the count in 8-bit counter n (TMn). If the two values match, an interrupt request (INTTMn) is generated (except in the PWM mode). The value of CRn0 can be set in the range of 00H to FFH, and can be written during counting. When TMm and TMm+1 are connected in cascade and used as a 16-bit timer, CRm0 and CR (m+1) 0 operate as a 16-bit compare register that is set by a 16-bit memory manipulation instruction. This register generates an interrupt request (INTTMm) when the counter value and register value are compared as 16 bits and match. Since the INTTMm+1 interrupt request is also generated at that time, mask the INTTMm+1 interrupt request when TMm and TMm+1 are used connected in cascade. RESET input sets these registers to 00H. Caution If data is set in a cascade connection, always set after stopping the timer. Remark n = 2 to 7 m = 2, 4, 6 7.3.4 Timer n control register The following two types of registers control timer n. * Timer clock selection registers n0, n1 (TCLn0, TCLn1) * 8-bit timer mode control register n (TMCn)
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(1) Timer clock selection registers 20 to 71 and 21 to 71 (TCL20 to TCL70 and TCL21 to TCL71) These registers set the count clock of timer n. TCLn0 and TCLn1 are set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
After reset: 00H 7 TCLn0 (n = 2, 3) 0 R/W 6 0 Address: FFFFF244H, FFFFF254H 5 0 4 0 3 0 2 TCLn2 1 TCLn1 0 TCLn0
After reset: 00H 7 TCLn1 (n = 2, 3) 0
R/W 6 0
Address: FFFFF24EH, FFFFF25EH 5 0 4 0 3 0 2 0 1 0 0 TCLn3
TCLn3
TCLn2
TCLn1
TCLn0
Count clock selection Count clock 20 MHzNote fXX 12.58 MHz - - 318 ns 636 ns 1.3 s 2.5 s 10.2 s 40.7 s - - 5.1 s 20.3 s - - - - - - - - - - 3.2 s 12.8 s
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TIn falling edge TIn rising edge fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXX/512 Setting prohibited Setting prohibited fXX/64 fXX/256 Setting prohibited Setting prohibited Setting prohibited Setting prohibited
- - 200 ns 400 ns 800 ns 1.6 s 6.4 s 25.6 s
Note
Only in the V850/SB1.
Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 to in TCLn0 to 0, and bits 1 to 7 in TCLn1 to 0. Remark When connected in cascade, the settings of TCL33 to TCL30 of TM3 are invalid.
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After reset: 00H 7 TCLn0 (n = 4, 5) 0
R/W 6 0
Address: FFFFF264H, FFFFF274H 5 0 4 0 3 0 2 TCLn2 1 TCLn1 0 TCLn0
After reset: 00H 7 TCLn1 (n = 4, 5) 0
R/W 6 0
Address: FFFFF26EH, FFFFF27EH 5 0 4 0 3 0 2 0 1 0 0 TCLn3
TCLn3
TCLn2
TCLn1
TCLn0
Count clock selection Count clock 20 MHzNote fXX 12.58 MHz - - 318 ns 636 ns 1.3 s 2.5 s 10.2 s 30.5 s - - 5.1 s 20.3 s - - - - - - - - - - 3.2 s 12.8 s
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TIn falling edge TIn rising edge fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXT (Subclock) Setting prohibited Setting prohibited fXX/64 fXX/256 Setting prohibited Setting prohibited Setting prohibited Setting prohibited
- - 200 ns 400 ns 800 ns 1.6 s 6.4 s 30.5 s
Note
Only in the V850/SB1.
Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 of TCLn0 and bits 1 to 7 of TCLn1 to 0. Remark When connected in cascade, the settings of TCL53 to TCL50 of TM5 are invalid.
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After reset: 00H 7 TCLn0 (n = 6, 7) 0
R/W 6 0
Address: FFFFF284H, FFFFF294H 5 0 4 0 3 0 2 TCLn2 1 TCLn1 0 TCLn0
After reset: 00H 7 TCLn1 (n = 6, 7) 0
R/W 6 0
Address: FFFFF28EH, FFFFF29EH 5 0 4 0 3 0 2 0 1 0 0 TCLn3
TCLn3
TCLn2
TCLn1
TCLn0
Count clock selection Count clock 20 MHz
Note
fXX 12.58 MHz - - 318 ns 636 ns 1.3 s 2.5 s 5.1 s 10.2 s - - 12.8 s 25.6 s - - - - - - 20.3 s 40.7 s - - - -
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Setting prohibited Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Setting prohibited Setting prohibited fXX/256 fXX/512 Setting prohibited Setting prohibited Setting prohibited TM0 overflow signal
- - 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s
Note
Only in the V850/SB1.
Cautions 1. When TCLn0 and TCLn1 are overwritten by different data, write after temporarily stopping the timer. 2. Always set bits 3 to 7 of TCLn0 and bits 1 to 7 of TCLn1 to 0. Remark When connected in cascade, the settings of TCL73 to TCL70 of TM7 are invalid.
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(2) 8-bit timer mode control registers 2 to 7 (TMC2 to TMC7) The TMCn register makes the following six settings. (1) Controls counting by 8-bit counter n (TMn) (2) Selects the operating mode of 8-bit counter n (TMn) (3) Selects the individual mode or cascade connection mode (4) Sets the state of the timer output flip-flop (5) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode (6) Controls timer output TMCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 04H (although the state of hardware is initialized to 04H, 00H is read when reading).
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After reset:
04H
R/W
Address:
TMC2 TMC3 TMC4
FFFFF246H FFFFF256H FFFFF266H 4 TMCn4 <3> LVSm
TMC5 TMC6 TMC7
FFFFF276H FFFFF286H FFFFF296H <2> LVRm 1 TMCm1 <0> TOEm
<7> TMCn TCEn
6 TMCn6
5 0
(n = 2 to 7, m = 2 to 5) TCEn 0 1 TMn count operation control Counting is disabled after the counter is cleared to 0 (prescaler disabled) Start count operation
TMCn6 0 1
TMn operating mode selection Clear & Start mode when TMn and CRn0 match PWM (free-running) mode
TMCn4 0 1
Individual mode or cascade connection mode selection Individual mode (fixed to 0 when n = 2, 4, 6) Cascade connection mode (connection to lower timer)
LVSm 0 0 1 1
LVRm 0 1 0 1 Not change
Setting state of timer output flip-flop
Reset timer output flip-flop to 0 Set timer output flip-flop to 1 Setting prohibited
TMCm1
Other than PWM (free-running) mode (TMCn6 = 0) Control of timer F/F
PWM (free-running) mode (TMCn6 = 1) Selection of active level Active high Active low
0 1
Disable inversion operation Enable inversion operation
TOEm 0 1 Disable output (port mode) Enable output
Timer output control
Cautions 1. When using as the timer output pin (TOm), set the port value to 0 (port mode output). An ORed value of the timer output value is output. 2. Since TOm and TIm share the same pin, only one of the functions can be used. Remarks 1. 2. In the PWM mode, the PWM output is set to the inactive level by TCEm = 0. If LVSm and LVRm are read after setting data, 0 is read.
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7.4 8-Bit Timer Operation
7.4.1 Operation as interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupts at the interval of the count preset by 8bit compare register n (CRn0). If the count in 8-bit counter n (TMn) matches the value set in CRn0, the value of TMn is cleared to 0 and TMn continues counting. At the same time, an interrupt request signal (INTTMn) is generated. The TMn count clock can be selected by the TCLn0 to TCLn2 bits of timer clock selection register n0 (TCLn0) and by the TCLn3 bit of timer clock selection register n1 (TCLn1) (n = 2 to 7). Setting method (1) Set each register. * TCLn0, TCLn1: * CRn0: * TMCn: Select the count clock. Compare value Selects the clear and start mode when TMn and CRn0 match. (TMCn = 0000xx11B, x is don't care) (2) When TCEn = 1 is set, counting starts. (3) When the values of TMn and CRn0 match, INTTMn is generated (TMn is cleared to 00H). (4) Then, INTTMn is repeatedly generated at the same interval. When counting stops, set TCEn = 0. Figure 7-32. Timing of Interval Timer Operation (1/3) Basic operation
t Count clock TMn count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N
Count start CRn0 TCEn INTTMn N
Interrupt acknowledgment TOm Interval time Interval time
Interrupt acknowledgment Interval time
Remarks 1. Interval time = (N + 1) x t; N = 00H to FFH 2. n = 2 to 7, m = 2 to 5
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Figure 7-32. Timing of Interval Timer Operation (2/3) When CRn0 = 00H
t
Count clock TMn 00H CRn0 TCEn INTTMn TOm 00H 00H 00H 00H
Interval time
Remark
n = 2 to 7, m = 2 to 5
When CRn0 = FFH
t Count clock TMn CRn0 TCEn INTTMn Interrupt acknowledgment TOm Interval time Interrupt acknowledgment FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H
Remark
n = 2 to 7, m = 2 to 5
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Figure 7-32. Timing of Interval Timer Operation (3/3) Operated by CRn0 transition (M < N)
Count clock TMn CRn0 TCEn INTTMn TOm CRn0 transition TMn overflows since M < N 00H M N N FFH 00H M M 00H
Remark
n = 2 to 7, m = 2 to 5
Operated by CRn0 transition (M > N)
Count clock TMn CRn0 TCEn INTTMn TOm CRn0 transition N-1 N N 00H 01H N M-1 M M 00H 01H
Remark
n = 2 to 7, m = 2 to 5
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7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIn. Each time a valid edge specified by timer clock selection register n0, n1 (TCLn0, TCLn1) is input, TMn is incremented. The edge setting can be selected as either the rising or falling edge. If the total of TMn and the value of 8-bit compare register n (CRn0) match, TMn is cleared to 0 and an interrupt request signal (INTTMn) is generated. INTTMn is generated each time the TMn value matches the CRn0 value. Remark n = 2 to 5 Figure 7-33. Timing of External Event Counter Operation (with Rising Edge Specified)
TIn TMn count value CRn0 INTTMn
0000 0001 0002 0003 0004 0005
N-1 N
N
0000
0001
0002
0003
Remark
n = 2 to 5
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7.4.3 Operation as square wave output (8-bit resolution) A square wave with any frequency is output at the interval preset by 8-bit compare register n (CRn0). By setting bit 0 (TOEn) of 8-bit timer mode control register n (TMCn) to 1, the output state of TOn is inverted with the count preset in CRn0 as the interval. Therefore, a square wave output with any frequency (duty factor = 50%) is possible. Setting method (1) Set the registers. * Set the port latch and port mode register to 0 * TCLn0, TCLn1: * CRn0: * TMCn: Select the count clock Compare value Clear and start mode when TMn and CRn0 match
LVSn 1 0 LVRn 0 1 Setting State of Timer Output Flip-Flop High level output Low level output
Inversion of timer output flip-flop enabled Timer output enabled TOEn = 1 (2) When TCEn = 1 is set, the counter starts operating. (3) If the values of TMn and CRn0 match, the timer output flip-flop inverts. Also, INTTMn is generated and TMn is cleared to 00H. (4) Then, the timer output flip-flop is inverted at the same interval to output a square wave from TOn. Remark n = 2 to 5 Figure 7-34. Square Wave Output Operation Timing
Count clock TMn count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H
Count start CRn0 TOn N
Note The initial value of TOn output can be set by the LVSn and LVRn bits of the TMCn register. Remarks 1. Square-wave output frequency = 1/2 (N + 1) 2. n = 2 to 5
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7.4.4 Operation as 8-bit PWM output By setting the TMCn6 bit of 8-bit timer mode control register n (TMCn) to 1, the timer operates as a PWM output. Pulses with the duty factor determined by the value set to 8-bit compare register n (CRn0) are output from TOn. Set the width of the active level of the PWM pulse to CRn0. The active level can be selected by the TMCn1 bit in TMCn. The count clock can be selected by the TCLn0 to TCLn2 bits of timer clock selection register n0 (TCLn0) and by the TCLn3 bit of timer clock selection register n1 (TCLn1). The PWM output can be enabled and disabled by the TOEn bit of TMCn. Caution Remark CRn0 can be rewritten only once in one cycle while in the PWM mode. n = 2 to 5
(1) Basic operation of the PWM output Setting method (1) Set the port latch and port mode register n to 0. (2) Set the active level width in 8-bit compare register n (CRn0). (3) Select the count clock using timer clock selection register n0, n1 (TCLn0, TCLn1). (4) Set the active level in TMCn1 bit of TMCn. (5) If TCEn bit of TMCn is set to 1, counting starts. When counting stops, set TCEn to 0. PWM output operation (1) When counting starts, the PWM output (output from TOn) outputs the inactive level until an overflow occurs. (2) When the overflow occurs, the active level specified in step (1) in the setting method is output. The active level is output until CRn0 and the count of 8-bit counter n (TMn) match. (3) The PWM output after CRn0 and the count match is the inactive level until an overflow occurs again. (4) Steps (2) and (3) repeat until counting stops. (5) If counting is stopped by TCEn = 0, the PWM output goes to the inactive level. Remark n = 2 to 5
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(a)
Basic operation of PWM output Figure 7-35. Timing of PWM Output
Basic operation (active level = H)
t Count clock TMn CRn0 TCEn INTTMn TOn Active level Inactive level Active level
00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H
When CRn0 = 00H
t Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level
00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H
When CRn0 = FFH
t Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Active level Active level Inactive level
00H 01H FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H
Inactive level
Remarks 1. PWM frequency = 2 t Duty = N/256 (N: CRn0 set value) 2. n = 2 to 5
8
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(b)
Operation based on CRn0 transitions Figure 7-36. Timing of Operation Based on CRn0 Transitions
When the CRn0 value changes from N to M before TMn overflows Count clock TMn CRn0 TCEn INTTMn TOn
H
N N+ 1 N+ 2 FFH 00H 01H 02H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2
N
M
CRn0 transition (N M)
When the CRn0 value changes from N to M after TMn overflows Count clock TMn CRn0 TCEn INTTMn TOn
H N N+1 N+2 N FFH 00H 01H 02H 03H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
CRn0 transition (N M)
When the CRn0 value changes from N to M within two clocks (00H, 01H) immediately after TMn overflows Count clock TMn CRn0 TCEn INTTMn TOn
H N N+1 N+2 N FFH 00H 01H 02H 03H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
CRn0 transition (N M) Remark n = 2 to 5
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7.4.5 Operation as interval timer (16 bits) (1) Cascade connection (16-bit timer) mode The V850/SB1 and V850/SB2 provide 16-bit registers that can be used only when connected in cascade. The following registers are available. TM2, TM3 cascade connection: TM4, TM5 cascade connection: TM6, TM7 cascade connection: 16-bit counter TM23 (Address: FFFFF24AH) 16-bit compare register CR23 (Address: FFFFF24CH) 16-bit counter TM45 (Address: FFFFF26AH) 16-bit compare register CR45 (Address: FFFFF26CH) 16-bit counter TM67 (Address: FFFFF28AH) 16-bit compare register CR67 (Address: FFFFF28CH) By setting the TMCm4 bit of 8-bit timer mode control register m (TMCm) to 1, the timer enters the timer/counter mode with 16-bit resolution (m = 3, 5, 7). With the count preset in 8-bit compare register n (CRn0) as the interval, the timer operates as an interval timer by repeatedly generating interrupts (n = 2 to 7). The following shows a setting method when using TM2 and TM3. When using TM4 and TM5 or TM6 and TM7, substitute them for TM2 and TM3. Setting method (TM2, TM3 cascade connection) (1) Setting registers * TCL20, TCL21: * CR20, CR30: * TMC2: Select the count clock for TM2 (setting not necessary for TM3 because of cascade connection). Compare value (00H to FFH can be set for compare values) Selects clear & start mode on a match of TM2 and CR2 (x: don't care) [TM2 TMC2 = 0000xxx0B, TM3 TMC3 = 0001xxx0B] (2) Set the TCE3 bit of TMC3 to 1. After that, set the TCE2 bit of TMC2 to 1 to start the count operation. (3) When the TM23 and CR23 values of the timer connected in cascade match, an interrupt request signal (INTTM2) is generated (TM2 and TM3 are cleared to 00H). (4) IMTTM2 is then repeatedly generated at the same interval. Cautions 1. The count operation can be started or stopped just by setting the TCE2 bit of TMC2. 2. When 8-bit timers (TM2, TM3) are connected in cascade and used as a 16-bit timer (TM23), change the setting value of the compare register (CR23) after stopping the count operation of the 8-bit timers connected in cascade. If the value of CR23 is changed without stopping the timers, the values of the higher 8 bits (TM3) become undefined. 3. Even during cascade connection, the interrupt request signal (INTTM3) of higher timer 3 (TM3) is generated when the count value of higher timer 3 (TM3) matches CR30. Be sure to mask TM3 to disable this interrupt.
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A timing example of the cascade connection mode with 16-bit resolution is shown below. Figure 7-37. Cascade Connection Mode with 16-Bit Resolution
Count clock TMn TMn + 1 CRn0 CR(n+1)0 TCEn TCEn + 1 INTTMn TOm Interval time
00H 00H N M 01H N N+1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M- 1 M N 00H 01H 00H A 00H B 00H
Enable operation starting count
Interrupt generation Level inverted Counter cleared
Operation stopped
Remark
n = 2, 4, 6, m = 2, 4
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7.4.6 Cautions (1) Error when the timer starts An error of up to 1 clock occurs in the time until the match signal is generated after the timer starts. The reason is that 8-bit counter n (TMn) starts asynchronous to the count pulse. Figure 7-38. Start Timing of Timer n
Count pulse TMn count value 00H Timer starts 01H 02H 03H 04H
Remark
n = 2 to 7
(2) Operation after compare register is changed while timer is counting If the value after 8-bit compare register n (CRn0) changes is less than the value of the 8-bit timer register (TMn), counting continues, overflows, and counting starts again from 0. Consequently, when the value after CRn0 changes (M) is less than the value before the change (N) and less than the count value of the TMn register, the timer must restart after CRn0 changes (n = 2 to 5). Figure 7-39. Timing After Compare Register Changes During Timer Count Operation
Count pulse CRn0 TMn count value N X-1 X M FFH 00H 01H 02H
Remarks 1. N > X > M 2. n = 2 to 7 Caution Except when the TIm input is selected, always set TCEn = 0 before setting the stop state (m = 2 to 5). (3) TMn read out during timer operation Since reading out TMn during operation occurs while the selected clock is temporarily stopped, select a high-or low-level waveform that is longer than the selected clock (n = 2 to 7).
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8.1 Function
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and interval timer functions can be used at the same time. Figure 8-1. Block Diagram of Watch Timer
Selector
Clear
Selector
5-bit counter
Selector
INTWTN
fXX fXT
fW
11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29
Clear
Selector
INTWTNI
4
WTNCS1 WTNCS0 Watch timer clock selection register (WTNCS)
WTNCS2
WTNM7 WTNM6 WTNM5 WTNM4 WTNM3 WTNM2 WTNM1 WTNM0 Watch timer mode control register (WTNM)
Watch timer high-speed clock selection register (WTNHC) Internal bus
Caution The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. Remark fXX: Main clock frequency fXT: Subclock frequency fW: Watch timer clock frequency
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(1) Watch timer The watch timer generates an interrupt request (INTWTN) at time intervals of 0.5 seconds or 0.25 seconds by using the main clock or subclock. (2) Interval timer The watch timer generates an interrupt request (INTWTNI) at time intervals specified in advance. Table 8-1. Interval Time of Interval Timer
Interval Time 2 x 1/fW
4
fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms
2 x 1/fW
5
2 x 1/fW
6
2 x 1/fW
7
28 x 1/fW 2 x 1/fW
9
2 x 1/fW
10
2 x 1/fW
11
Remark
fW: Watch timer clock frequency
8.2 Configuration
The watch timer includes the following hardware. Table 8-2. Configuration of Watch Timer
Item Counter Prescaler Control registers 5 bits x 1 11 bits x 1 Watch timer mode control register (WTNM) Watch timer high-speed clock selection register (WTNHC)Note Watch timer clock selection register (WTNCS) Configuration
Note
The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY.
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8.3 Watch Timer Control Registers
The watch timer mode control register (WTNM), watch timer high-speed clock selection register (WTNHC) setting the count clock and interval time. Caution The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. (1) Watch timer mode control register (WTNM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. WTNM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WTNM to 00H.
After reset: 00H 7 WTNM WTNM7 R/W 6 WTNM6 Address: FFFFF360H 5 WTNM5 4 WTNM4 3 WTNM3 2 WTNM2 <1> WTNM1 <0> WTNM0
Note
, and
watch timer clock selection register (WTNCS) control the watch timer. The watch timer should be operated after
WTNM6 0 0 0 0 1 1 1 1
WTNM5 0 0 1 1 0 0 1 1
WTNM4 0 1 0 1 0 1 0 1
4
Selection interval time of prescaler 2 /fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) 210/fW (31.2 ms) 211/fW (62.4 ms)
WTNM3 0 0 1 1
WTNM2 0 1 0 1 214/fW (0.5 s) 213/fW (0.25 s) 25/fW (977 s) 24/fW (488 s)
Watch timer interrupt
WTM1 0 1
Control of operation of 5-bit counter Clears after operation stops Starts
WTNM0 0 1
Watch timer operation enable Operation stopped (clears both prescaler and 5-bit counter) Operation enabled
Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply when fW = 32.768 kHz. 3. For the settings of WTNM7, refer to (3) Watch timer clock selection register (WTNCS).
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(2) Watch timer high-speed clock selection register (WTNHC) This register selects the count clock of the watch timer. The count clock is determined in combination with the WTNM7 bit of the WTNM register and the WTNCS1 and WTNCS0 bits of the watch timer clock selection register (WTNCS). WTNHC is set using an 8-bit memory manipulation instruction. RESET input clears WTNHC to 00H.
After reset: 00H R/W Address: FFFFF366H
WTNHC
0
0
0
0
0
0
0
WTNCS2
Caution
The WTNHC register is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY.
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(3) Watch timer clock selection register (WTNCS) This register selects the count clock of the watch timer. WTNCS is set using an 8-bit memory manipulation instruction. RESET input clears WTNCS to 00H. Caution Do not change the contents of the WTNM, WTNHC, and WTNCS registers (interval time, watch timer interrupt time, count clock) during a watch timer operation.
After reset: 00H R/W Address: FFFFF364H
WTNCS
0
0
0
0
0
0
WTNCS1 WTNCS0
WTNCS2Note WTNCS1 WTNCS0 WTNM7 Selection of count clock Main clock frequency 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 fXX/27 fXT (subclock) fXX/3 x 2 fXX/2
8 6
4.194 MHz - 6.291 MHz 8.388 MHz - - 12.582 MHz 16.777 MHz 18.874 MHz -
Setting prohibited Setting prohibited fXX/3 x 2 fXX/2
9 7
fXX/32 x 26 Setting prohibited
Other than above
Note The WTNCS2 bit is available only in the B versions of the V850/SB1, PD703036H, 703036HY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY. Remark WTNM7 is bit 7 of the WTNM register.
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8.4 Operation
8.4.1 Operation as watch timer The watch timer operates at time intervals of 0.5 seconds with the subclock (32.768 kHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTNM0) and 1 (WTNM1) of the watch timer mode control register (WTNM) are set to 1. When these bits are cleared to 0, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. The watch timer clears the 5-bit counter by setting the WTNM1 bit to 0. At this time, an error of up to 15.6 ms may occur. The interval timer can be cleared by setting the WTNM0 bit to 0. However, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (INTWTN). 8.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. The interval time can be selected by bits 4 to 6 (WTNM4 to WTNM6) of the watch timer mode control register (WTNM). Table 8-3. Interval Time of Interval Timer
WTNM6 0 0 0 0 1 1 1 1 WTNM5 0 0 1 1 0 0 1 1 WTNM4 0 1 0 1 0 1 0 1 Interval Time 2 x 1/fW
4
fW = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms
2 x 1/fW
5
2 x 1/fW
6
27 x 1/fW 2 x 1/fW
8
2 x 1/fW
9
2 x 1/fW
10
2 x 1/fW
11
Remark
fW: Watch timer clock frequency
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Figure 8-2. Operation Timing of Watch Timer/Interval Timer
5-bit counter 0H Start Count clock fW or fW/29 Watch timer interrupt INTWTN Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTNI Interval time (T) nT Interval time (T) nT Overflow Overflow
Remark
fW: Watch timer clock frequency ( ): fW = 32.768 kHz n: Interval timer operation count
8.4.3 Cautions It takes some time to generate the first watch timer interrupt request (INTWTN) after operation is enabled (WRNM1 and WTNM0 bits of WTNM register = 1). Figure 8-3. Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s) It takes 0.515625 s to generate the first INTWTN (2 x 1/32.768 = 0.015625 s longer). INTWTN is then
9
generated every 0.5 s.
WTNM0, WTNM1 0.515625 s 0.5 s 0.5 s
INTWTN
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9.1 Functions
The watchdog timer has the following functions. * Watchdog timer * Interval timer * Selecting the oscillation stabilization time Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode.
Figure 9-1. Block Diagram of Watchdog Timer
RUN Clear fXX/210 Prescaler fXX/222 fXX/220 fXX/219 fXX/218 fXX/217 fXX/216 fXX/215 fXX/214 INTWDTNote 1 Output controller INTWDTMNote 2
Selector
Selector
OSC
3
3
WDCS WDCS2 WDCS1 WDCS0
OSTS OSTS2 OSTS1 OSTS0
WDTM
RUN
WDTM4
Internal bus
Notes 1. 2. Remark
In watchdog timer mode In interval timer mode fXX: Main clock frequency
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(1) Watchdog timer mode This mode detects an inadvertent program loop. When an inadvertent program loop is detected, a non-maskable interrupt can be generated. Table 9-1. Inadvertent Program Loop Detection Time of Watchdog Timer
Clock Inadvertent Program Loop Detection Time fXX = 20 MHzNote 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX
22 20 19 18 17 16 15 14
fXX = 12.58 MHz 1.3 ms 2.6 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms 83.3 ms 333.4 ms
819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 209.7 ms
Note Only in the V850/SB1. (2) Interval timer mode Interrupts are generated at a preset time interval. Table 9-2. Interval Time of Interval Timer
Clock fXX = 20 MHz 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX
22 20 19 18 17 16 15 14
Interval Time
Note
fXX = 12.58 MHz 1.3 ms 2.6 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms 83.3 ms 333.4 ms
819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 209.7 ms
Note Only in the V850/SB1.
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9.2 Configuration
The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer
Item Control registers
Configuration Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM)
9.3 Watchdog Timer Control Register
The registers to control the watchdog timer are shown below. * Oscillation stabilization time selection register (OSTS) * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register (WDTM) (1) Oscillation stabilization time selection register (OSTS) This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable. OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
After reset: 04H 7 OSTS 0 R/W 6 0 5 0 Address: FFFFF380H 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection Clock 20 MHz
Note
fXX 12.58 MHz 1.3 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX (after reset) Setting prohibited
19 18 17 16
14
819.2 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms
Other than above
Note Only in the V850/SB1.
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(2) Watchdog timer clock selection register (WDCS) This register selects the overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input clears WDCS to 00H.
After reset: 00H R/W Address: FFFFF382H
7 WDCS 0
6 0
5 0
4 0
3 0
2 WDCS2
1 WDCS1
0 WDCS0
WDCS2
WDCS1
WDCS0
Watchdog timer/interval timer overflow time Clock 20 MHz
Note
fXX 12.58 MHz 1.3 ms 2.6 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms 83.3 ms 333.4 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 219/fXX 2 /fXX 2 /fXX
22 20 18 17 16 15
14
819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 209.7 ms
Note Only in the V850/SB1. Caution Be sure to set bits 3 to 7 to 0.
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(3) Watchdog timer mode register (WDTM) This register sets the operating mode of the watchdog timer, and enables and disables counting. WDTM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDTM to 00H.
After reset: 00H <7> WDTM RUN R/W 6 0 Address: FFFFF384H 5 0 4 WDTM4 3 0 2 0 1 0 0 0
RUN 0 1 Disable count
Operating mode selection for the watchdog timerNote 1
Clear count and start counting
WDTM4 0
Operating mode selection for the watchdog timerNote 2 Interval timer mode (If an overflow occurs, the maskable interrupt INTWDTM is generated.)
1
Watchdog timer mode 1 (If an overflow occurs, the non-maskable interrupt INTWDT is generated.)
Notes 1. 2. Caution
Once RUN is set (1), the register cannot be cleared (0) by software. Therefore, when counting starts, counting cannot be stopped except by RESET input. Once WDTM4 is set (1), the register cannot be cleared (0) by software. If RUN is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 2 /fXX seconds shorter than the set time.
10
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9.4 Operation
9.4.1 Operation as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect an inadvertent program loop. Setting bit 7 (RUN) of WDTM to 1 starts the count operation. After counting starts, if RUN is set to 1 again within the set time interval for inadvertent program loop detection, the watchdog timer is cleared and counting starts again. If RUN is not set to 1 and the inadvertent program loop detection time has elapsed, a non-maskable interrupt (INTWDT) is generated (no reset functions). The watchdog timer stops running in the IDLE mode and STOP mode. Consequently, set RUN to 1 and clear the watchdog timer before entering the IDLE mode or STOP mode. Do not set the watchdog timer when operating the HALT mode since the watchdog timer running in HALT mode. Cautions 1. The actual inadvertent program loop detection time may be up to 2 /fXX seconds less than the set time. 2. When the subclock is selected for the CPU clock, the watchdog timer stops (retains) counting. Table 9-4. Inadvertent Program Loop Detection Time of Watchdog Timer
Clock Inadvertent Program Loop Detection Time fXX = 20 MHzNote 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 219/fXX 220/fXX 2 /fXX
22 18 17 16 15 14
10
fXX = 12.58 MHz 1.3 ms 2.6 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms 83.3 ms 333.4 ms
819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 209.7 ms
Note Only in the V850/SB1.
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9.4.2 Operation as interval timer Set bit 4 (WDTM4) to 0 in the watchdog timer mode register (WDTM) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flag (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated. The default priority of INTWDTM has the highest priority setting of the maskable interrupts. The interval timer continues operating in the HALT mode and stops in the IDLE mode and STOP mode. Therefore, before entering the IDLE mode/STOP mode, set the RUN bit of the WDTM register to 1 and clear the interval timer. Then set the IDLE mode/STOP mode. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as RESET is not input. 2. The interval time immediately after being set by WDTM may be up to 2 /fXX seconds less than the set time. 3. When the subclock is selected for the CPU clock, the watchdog timer stops (retains) counting. Table 9-5. Interval Time of Interval Timer
Clock fXX = 20 MHz 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX
22 20 19 18 17 16 15 14
10
Interval Time
Note
fXX = 12.58 MHz 1.3 ms 2.6 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms 83.3 ms 333.4 ms
819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 209.7 ms
Note Only in the V850/SB1.
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9.5 Standby Function Control Register
(1) Oscillation stabilization time selection register (OSTS) The wait time from releasing the stop mode until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
After reset: 04H R/W Address: FFFFF380H
7 OSTS 0
6 0
5 0
4 0
3 0
2 OSTS2
1 OSTS1
0 OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection Clock 20 MHz
Note
fXX 12.58 MHz 1.3 ms 5.2 ms 10.4 ms 20.8 ms 41.6 ms
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX (after reset) Setting prohibited
19 18 17 16
14
819.2 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms
Other than above
Note Only in the V850/SB1. Caution The wait time at the release of the STOP mode does not include the time ("a" in the figure below) until clock oscillation starts after releasing the STOP mode when RESET is input or an interrupt is generated.
STOP mode release Voltage waveform at X1 pin Vss
a
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10.1 Overview
The V850/SB1 and V850/SB2 incorporate the following serial interfaces. * * * * * Channel 0: 3-wire serial I/O (CSI0)/I C0 Channel 2: 3-wire serial I/O (CSI2)/I C1
2 2 Note
Channel 1: 3-wire serial I/O (CSI1)/Asynchronous serial interface (UART0)
Note
Channel 3: 3-wire serial I/O (CSI3)/Asynchronous serial interface (UART1) Channel 4: 8 to 16-bit variable-length 3-wire serial I/O (CSI4)
2 2 2
Note I C0 and I C1 support multimasters (Y versions (products with on-chip I C) only). Either 3-wire serial I/O or I C can be used as a serial interface.
2
10.2 3-Wire Serial I/O (CSI0 to CSI3)
CSIn (n = 0 to 3) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed.
(2) 3-wire serial I/O mode (fixed to MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCKn), serial output line (SOn), and serial input line (SIn). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in the 8-bit data in serial transfers is fixed to the MSB. The SCK0 to SCK3 pins are set to normal output or N-ch open-drain output by setting the port 1 function register (PF1) and port 2 function register (PF2). 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clocked serial interface, a display controller, etc.
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10.2.1 Configuration CSIn includes the following hardware. Table 10-1. Configuration of CSIn
Item Registers Control registers Configuration Serial I/O shift registers 0 to 3 (SIO0 to SIO3) Serial operation mode registers 0 to 3 (CSIM0 to CSIM3) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3)
Figure 10-1. Block Diagram of 3-Wire Serial I/O
Internal bus
8
SIn
Serial I/O shift register n (SIOn)
SOn SCKn Serial clock counter Interrupt generator INTCSIn
Serial clock controller
Selector
TMx output Clock selection
Remarks 1. n = 0 to 3 2. TMx output is as follows: When n = 0 or 3: TM2 When n = 1 or 2: TM3 (1) Serial I/O shift registers 0 to 3 (SIO0 to SIO3) SIOn is an 8-bit register that performs parallel-serial conversion and serial transmission/reception (shift operations) synchronized with the serial clock. SIOn is set by an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIEn) of serial operation mode register n (CSIMn), a serial operation can be started by writing data to or reading data from SIOn. When transmitting, data written to SIOn is output via the serial output (SOn). When receiving, data is read from the serial input (SIn) and written to SIOn. RESET input clears these registers to 00H. Caution Do not execute SIOn accesses except for accesses that become the transfer start trigger during a transfer operation (read is disabled when MODE = 0 and write is disabled when MODE = 1).
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10.2.2 CSIn control registers CSIn is controlled by the following registers. * * Serial operation mode register n (CSIMn) Serial clock selection register n (CSISn)
(1) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) and serial operation mode registers 0 to 3 (CSIM0 to CSIM3) The CSISn register is used to set serial interface channel n's serial clock. The CSISn register can be set by an 8-bit memory manipulation instruction. RESET input clears the CSISn register to 00H. The CSIMn register is used to enable or disable serial interface channel n's serial clock, operation modes, and specific operations. The CSIMn register can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears the CSIMn register to 00H.
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After reset : 00H
R/W
Address: CSIS0 CSIS1 6 0 5 0 4 0
FFFFF2A4H FFFFF2B4H 3 0 2 0
CSIS2 CSIS3
FFFFF2C4H FFFFF2D4H 1 0 0 SCLn2
7 CSISn (n = 0 to 3) After reset: 00H R/W 0
Address: CSIM0 CSIM1 6 0 5 0 4 0
FFFFF2A2H FFFFF2B2H 3 0 2
CSIM2 CSIM3
FFFFF2C2H FFFFF2D2H 1 SCLn1 0 SCLn0
<7> CSIMn (n = 0 to 3) CSIEn CSIEn
MODEn
SIOn operation enable/disable specification Shift register operation Serial counter Clear Count operation enable Port function Port
Note 1
0 1
Operation disable Operation enable
Serial function + port functionNote 2
MODEn Operation mode 0 1 Transmit/receive mode Receive-only mode
Transfer operation mode flag Transfer start trigger SIOn write SIOn read SOn output Normal output Port function
SCLn2 0 0
SCLn1 0 0
SCLn0 0 1
Clock selection External clock input (SCKn) at n = 0, 3: Output of TO2 at n = 1, 2: Output of TO3 fXX/8 fXX/16 Setting prohibited Setting prohibited fXX/32 fXX/64
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
Notes 1. 2.
The SIn, SOn, and SCKn pins are used as port function pins when CSIEn = 0 (SIOn operation stop status). When CSIEn = 1 (SIOn operation enable status), the port function is available for the SIn pin when only using the transmit function and SOn pin when only using the receive function.
Cautions 1. Do not perform bit manipulation of SCLn1 and SCLn0. 2. Be sure to set bits 6 to 3 of the CSIMn register to 0. Remark When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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10.2.3 Operations CSIn has the following two operation modes. * * Operation stop mode 3-wire serial I/O mode
(1) Operation stop mode Serial transfers are not performed in this mode, enabling a reduction in power consumption. In operation stop mode, if SIn, SOn, and SCKn pin are also used as I/O ports, they can be used as normal I/O ports as well. (a) Register settings Operation stop mode is set via the CSIEn bit of serial operation mode register n (CSIMn). Figure 10-2. CSIMn Setting (Operation Stop Mode)
After reset : 00H R/W Address: CSIM0 CSIM1 CSIM2 CSIM3 6 0 5 0 4 0 FFFFF2A2H FFFFF2B2H FFFFF2C2H FFFFF2D2H 3 0 2 MODEn 1 SCLn1 0 SCLn0
7 CSIMn (n = 0 to 3) CSIEn CSIEn
SIOn operation enable/disable specification Shift register operation Serial counter Clear Port function Port
0
Operation disable
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(2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCKn), serial output line (SOn), and serial input line (SIn). (a) Register settings 3-wire serial I/O mode is set via serial operation mode register n (CSIMn). Figure 10-3. CSIMn Setting (3-Wire Serial I/O Mode)
After reset : 00H R/W Address: CSIM0 CSIM1 CSIM2 CSIM3 6 0 5 0 4 0 FFFFF2A2H FFFFF2B2H FFFFF2C2H FFFFF2D2H 3 0 2 MODEn 1 SCLn1 0 SCLn0
7 CSIMn (n = 0 to 3) CSIEn CSIEn
SIOn operation enable/disable specification Shift register operation Serial counter Count operation enable Port Serial function + port function
1
Operation enable
MODEn Operation mode 0 1 Transmit/receive mode Receive-only mode
Transfer operation mode flag Transfer start trigger Write to SIOn Read from SIOn SOn output Normal output Port function
SCLn2 0 0
SCLn1 0 0
SCLn0 0 1
Clock selection External clock input (SCKn) When n = 0, 3: TO2 When n = 1, 2: TO3 fXX/8 fXX/16 Setting prohibited Setting prohibited fXX/32 fXX/64
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
Remark
Refer to 10.2.2 (1) Serial clock selection registers 0 to 3 (CSIS0 to CSIS3) and serial operation mode registers 0 to 3 (CSIM0 to CSIM3) for the SCLn2 bit.
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(b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SOn latch and is output from the SOn pin. Data that is received via the SIn pin in synchronization with the rising edge of the serial clock is latched to SIOn. Completion of an 8-bit transfer automatically stops operation of SIOn and sets the interrupt request flag (INTCSIn). Figure 10-4. Timing of 3-Wire Serial I/O Mode
Serial clock SI0 SO0 INTCSIn Transfer completion Transfer starts in synchronization with the serial clock's falling edge 1 DI7 DO7 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0
(c) Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I/O shift register n (SIOn). * The SIOn operation control bit (CSIEn) = 1 * After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. Transfer data is set to SIOn as follows. * Transmit/receive mode When CSIEn = 1 and MODEn = 0, transfer starts when writing to SIOn. * Receive-only mode When CSIEn = 1 and MODEn = 1, transfer starts when reading from SIOn. Caution After data has been written to SIOn, transfer will not start even if the CSIEn bit value is set to "1". Completion of an 8-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (INTCSIn).
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10.3 I C Bus (A Versions)
To use the I C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open drain output. The products with an on-chip I C bus are shown below. * V850/SB1: PD703031AY, 703032AY, 703033AY, 70F3032AY, 70F3033AY * V850/SB2: PD703034AY, 703035AY, 703037AY, 70F3035AY, 70F3037AY The I C0 and I C1 have the following two modes. * Operation stop mode * I C (Inter IC) bus mode (multimasters supported)
2 2 2 2 2
2
(1) Operation stop mode This mode is used when serial transfers are not performed. consumption. (2) I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLn) line and a serial data bus (SDAn) line. This mode complies with the I C bus format and the master device can output "start condition", "data", and "stop condition" data to the slave device, via the serial data bus. bus. Since SCLn and SDAn are open drain outputs, the I Cn requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 0, 1
2 2 2
It can therefore be used to reduce power
The slave device automatically detects these
2
received data by hardware. This function can simplify the part of an application program that controls the I C
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Figure 10-5. Block Diagram of I C
Internal bus IIC status register n (IICSn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
2
IIC control register n (IICCn) SDAn Noise eliminator Slave address register n (SVAn) Match signal
IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
CLEAR SET SO latch DQ CL1, CL0
IIC shift register n (IICn)
N-ch opendrain output
Data hold time correction circuit
ACK detector
Wakeup controller ACK detector
Start condition detector
SCLn Noise eliminator
Stop condition detector Interrupt request signal generator
Serial clock counter
INTIICn
Serial clock controller N-ch opendrain output fXX TMx output Prescaler
Serial clock wait controller
CLDn DADn SMCn DFCn CLn1 CLn0 IIC clock selection register n (IICCLn)
CLXn
IICCEn1 IICCEn0 IIC clock expansion register n (IICCEn)
IIC function expansion register n (IICXn)
Internal bus
Remarks 1. n = 0, 1 2. TMx output n = 0: TM2 output n = 1: TM3 output
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A serial bus configuration example is shown below. Figure 10-6. Serial Bus Configuration Example Using I C Bus
+VDD +VDD
2
Master CPU1 Slave CPU1 Address 1
SDA SCL
Serial data bus Serial clock
SDA SCL
Master CPU2 Slave CPU2 Address 2
SDA SCL
Slave CPU3 Address 3
SDA SCL
Slave IC Address 4
SDA SCL
Slave IC Address N
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10.3.1 Configuration I Cn includes the following hardware (n = 0, 1). Table 10-2. Configuration of I Cn
Item Registers Configuration IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) IIC clock selection registers 0 and 1 (IICCL0, IICCL1) IIC clock expansion registers 0 and 1 (IICCE0, IICCE1) IICC function expansion registers 0 and 1 (IICX0, IICX1)
2 2
Control registers
(1)
IIC shift registers 0 and 1 (IIC0, IIC1) IICn is used to convert 8-bit serial data into 8-bit parallel data and vice versa. IICn can be used for both transmission and reception (n = 0, 1). Write and read operations to IICn are used to control the actual transmit and receive operations. IICn is set by an 8-bit memory manipulation instruction. RESET input clears IIC0 and IIC1 to 00H.
(2)
Slave address registers 0 and 1 (SVA0, SVA1) SVAn sets local addresses when in slave mode. SVAn is set by an 8-bit memory manipulation instruction (n = 0, 1). RESET input clears SVA0 and SVA1 to 00H.
(3)
SO latch The SO latch is used to retain the SDAn pin's output level (n = 0, 1).
(4)
Wakeup controller This circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (SVAn) or when an extension code is received (n = 0, 1).
(5)
Clock selector This selects the sampling clock to be used.
(6)
Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received.
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(7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. * Eighth or ninth clock of the serial clock (set by WTIMn bit) * Interrupt request generated when a stop condition is detected (set by SPIEn bit) Remarks 1. n = 0, 1 2. WTIMn bit: Bit 3 of IIC control register n (IICCn) SPIEn bit: Bit 4 of IIC control register n (IICCn)
2
(8) Serial clock controller In master mode, this circuit generates the clock output via the SCLn pin from a sampling clock (n = 0, 1). (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK output circuit, stop condition detector, start condition detector, and ACK detector These circuits are used to output and detect various control signals. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
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10.3.2 I C control registers I C0 and I C1 are controlled by the following registers. * IIC control registers 0, 1 (IICC0, IICC1) * IIC status registers 0, 1 (IICS0, IICS1) * IIC clock selection registers 0, 1 (IICCL0, IICCL1) * IIC clock expansion registers 0, 1 (IICCE0, IICCE1) * IIC function expansion registers 0, 1 (IICX0, IICX1) The following registers are also used. * IIC shift registers 0, 1 (IIC0, IIC1) * Slave address registers 0, 1 (SVA0, SVA1) (1) IIC control registers 0, 1 (IICC0, IICC1) IICCn is used to enable/disable I C operations, set wait timing, and set other I C operations. IICCn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0, 1). RESET input clears IICCn to 00H. Caution In I C0, I C1 bus mode, set the port 1 mode register (PM1), port 2 mode register (PM2), port 1 function register (PF1), and port 2 function register (PF2) as follows. In addition, set each output latch to 0.
Pin P10/SI0/SDA0 P12/SCK0/SCL0 P20/SI2/SDA1 P22/SCK2/SCL1 Port Mode Register PM10 of PM1 register = 0 PM12 of PM1 register = 0 PM20 of PM2 register = 0 PM22 of PM2 register = 0 Port Function Register PF10 of PF1 register = 1 PF12 of PF1 register = 1 PF20 of PF2 register = 1 PF22 of PF2 register = 1
2 2 2 2 2 2
2
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(1/4)
After reset: 00H <7> IICCn (n = 0, 1) IICEn 0 1 I2Cn operation enable/disable specification Operation stopped. IIC status register n (IICSn) preset. Internal operation stopped. Enables operation. Condition for setting (IICEn = 1) * Set by instruction IICEn R/W <6> LRELn <5> WRELn Address: FFFFF340H, FFFFF350H <4> SPIEn <3> WTIMn <2> ACKEn <1> STTn <0> SPTn
Condition for clearing (IICEn = 0) * Cleared by instruction * When RESET is input
LRELn 0 1 Normal operation
Exit from communications
This exits from the current communications operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLn and SDAn lines are set to high impedance. The following flags are cleared. * STDn * ACKDn * TRCn * COIn * EXCn * MSTSn * STTn * SPTn
The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LRELn = 0)
Note
Condition for setting (LRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
Note This flag's signal is invalid when IICEn = 0. Remark STDn: ACKDn: TRCn: COIn: EXCn: MSTSn: Bit 1 of IIC state register n (IICSn) Bit 2 of IIC state register n (IICSn) Bit 3 of IIC state register n (IICSn) Bit 4 of IIC state register n (IICSn) Bit 5 of IIC state register n (IICSn) Bit 7 of IIC state register n (IICSn)
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(2/4)
WRELn 0 1 Do not cancel wait Cancel wait. This setting is automatically cleared after wait is canceled.
Note
Wait cancellation control
Condition for clearing (WRELn = 0)
Condition for setting (WRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
SPIEn 0 1 Disabled Enabled
Enable/disable generation of interrupt request when stop condition is detected
Condition for clearing (SPIEn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (SPIEn = 1) * Set by instruction
WTIMn 0
Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for the master device. Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for the master device.
1
This bit's setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (WTIMn = 1) * Set by instruction
Note
This flag's signal is invalid when IICEn = 0. n = 0, 1
Remark
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ACKEn 0 1 Disable acknowledgment. Enable acknowledgment. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1.
Note
Acknowledge control
Condition for clearing (ACKEn = 0) * Cleared by instruction * When RESET is input
Condition for setting (ACKEn = 1) * Set by instruction
STTn 0 1 Do not generate a start condition.
Start condition trigger
When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCLn is changed to low level. When bus is not used: This trigger functions as a start condition reserve flag. When set, it releases the bus and then automatically generates a start condition. In the wait state (when master device) Generate a restart condition after releasing the wait.
Cautions concerning set timing * For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the ACKn period. Set during the wait period. * Cannot be set at the same time as SPTn Condition for clearing (STTn = 0) * Cleared by instruction * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (STTn = 1) * Set by instruction
Note This flag's signal is invalid when IICEn = 0. Remark Bit 1 (STTn) is 0 if it is read immediately after data setting.
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SPTn 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDAn line is changed from low level to high level and a stop condition is generated. Cautions concerning setting timing * For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and during the wait period after slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the ACKn period. Set during the wait period. * Cannot be set at the same time as STTn. * SPTn can be set only when in master modeNote * When WTIMn has been set to 0, if SPTn is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. When a ninth clock must be output, WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks, and SPTn should be set during the wait period that follows output of the ninth clock. Condition for clearing (SPTn = 0) * Cleared by instruction * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (SPTn = 1) * Set by instruction Stop condition trigger
Note Set SPTn only in master mode. However, SPTn must be set and a stop condition generated before the first stop condition is detected following the switch to operation enable status. For details, see 10.3.13 Cautions. Caution When bit 3 (TRCn) of IIC status register n (IICSn) is set to 1, WRELn is set during the ninth clock and wait is canceled, after which TRCn is cleared and the SDAn line is set to high impedance. Remarks 1. Bit 0 (SPTn) is 0 if it is read immediately after data setting. 2. n = 0, 1
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(2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H. (1/3)
After reset: 00H <7> IICSn (n = 0, 1) MSTSn R <6> ALDn <5> EXCn Address: FFFFF342H, FFFFF352H <4> COIn <3> TRCn <2> ACKDn <1> STDn <0> SPDn
2
MSTSn 0 1
Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTSn = 1) * When a start condition is generated
Condition for clearing (MSTSn = 0) * When a stop condition is detected * When ALDn = 1 * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
ALDn 0 1
Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". MSTSn is cleared. Condition for setting (ALDn = 1)
Note
Condition for clearing (ALDn = 0) * Automatically cleared after IICSn is read * When IICEn changes from 1 to 0 * When RESET is input
* When the arbitration result is a "loss".
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICSn. Remark LRELn: Bit 6 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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EXCn 0 1 Extension code was not received. Extension code was received. Condition for setting (EXCn = 1) * When the higher four bits of the received address data are either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of extension code reception
Condition for clearing (EXCn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
COIn 0 1 Addresses do not match. Addresses match.
Detection of matching addresses
Condition for clearing (COIn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
Condition for setting (COIn = 1) * When the received address matches the local address (SVAn) (set at the rising edge of the eighth clock).
TRCn 0 1
Detection of transmit/receive status Receive status (other than transmit status). The SDAn line is set to high impedance. Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at the falling edge of the first byte's ninth clock). Condition for setting (TRCn = 1) Master * When a start condition is generated Slave * When "1" is input by the first byte's LSB (transfer direction specification bit)
Condition for clearing (TRCn = 0) * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * Cleared by WRELn = 1Note * When ALDn changes from 0 to 1 * When RESET is input Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication
Note TRCn is cleared and SDAn line become high impedance when bit 5 (WRELn) of IIC control register n (IICCn) is set and the wait state is released at the ninth clock with bit 3 (TRCn) of IIC status register n (IICSn) = 1. Remarks 1. WRELn: Bit 5 of IIC control register n (IICCn) LRELn: IICEn: 2. n = 0, 1 Bit 6 of IIC control register n (IICCn) Bit 7 of IIC control register n (IICCn)
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ACKDn 0 1 ACK was not detected. ACK was detected. Condition for setting (ACKD = 1) * After the SDAn line is set to low level at the rising edge of the SCLn's ninth clock Detection of ACK
Condition for clearing (ACKDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
STDn 0 1 Start condition was not detected.
Detection of start condition
Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STDn = 1) When a start condition is detected
Condition for clearing (STDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
SPDn 0 1 Stop condition was not detected.
Detection of stop condition
Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPDn = 1) When a stop condition is detected
Condition for clearing (SPDn = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When IICEn changes from 1 to 0 * When RESET is input
Remarks 1. LRELn: Bit 6 of IIC control register n (IICCn) IICEn: 2. n = 0, 1 Bit 7 of IIC control register n (IICCn)
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(3) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set using the CLXn bit of IIC function expansion register n (IICXn) in combination with bits IICCEn1 and IICCEn0 of IIC clock expansion register n (IICCEn) (n = 0, 1) (see 10.3.2 (6) I Cn transfer clock setting method). RESET input clears IICCLn to 00H.
After reset: 00H 7 IICCLn (n = 0, 1) 0 R/W
Note 2 2
Address: FFFFF344H, FFFFF354H <5> CLDn <4> DADn 3 SMCn 2 DFCn 1 CLn1 0 CLn0
6 0
CLDn 0 1
Detection of SCLn line level (valid only when IICEn = 1) SCLn line was detected at low level. SCLn line was detected at high level. Condition for setting (CLDn = 1) * When the SCLn line is at high level
Condition for clearing (CLDn = 0) * When the SCLn line is at low level * When IICEn = 0 * When RESET is input
DADn 0 1
Detection of SDAn line level (valid only when IICEn = 1) SDAn line was detected at low level. SDAn line was detected at high level. Condition for setting (DADn = 1) * When the SDAn line is at high level
Condition for clearing (DADn = 0) * When the SDAn line is at low level * When IICEn = 0 * When RESET is input
SMCn 0 1 Operates in standard mode. Operates in high-speed mode.
Operation mode switching
DFCn 0 1 Digital filter off. Digital filter on.
Digital filter operation control
A digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFCn switching (on/off).
Note Bits 4 and 5 are read only bits. Caution Be sure to set bits 7 and 6 to 0. Remark IICEn: Bit 7 of IIC control register n (IICCn)
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(4) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set with a 1-bit or 8-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0 bits of IIC clock expansion register n (IICCEn) (see 10.3.2 (6) I Cn transfer clock setting method) (n = 0, 1). RESET input clears these registers to 00H.
2 2
After reset: 00H 7 IICXn (n = 0, 1) 0
R/W 6 0
Address: FFFFF34AH, FFFFF35AH 5 0 4 0 3 0 2 0 1 0 <0> CLXn
(5) IIC clock expansion registers 0, 1 (IICCE0, IICCE1) These registers set the transfer clock expansion of I Cn. IICCEn is set with an 8-bit memory manipulation instruction. Set the IICCEn1 and IICCEn0 bits in combination with the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) and the CLXn bit of IIC function expansion register n (IICXn) (see 10.3.2 (6) I Cn transfer clock setting method) (n = 0, 1). RESET input clears these registers to 00H.
2 2
After reset: 00H 7 IICCEn (n = 0, 1) 0
R/W 6 0
Address: FFFFF34CH, FFFFF35CH 5 0 4 0 3 0 2 0 1 IICCEn1 0 IICCEn0
(6) I Cn transfer clock setting method The I Cn transfer clock frequency (fSCL) is calculated using the following expression (n = 0, 1). fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see Table 10-3 Selection Clock Setting.) T: tR: tF: 1/fXX SCLn rise time SCLn fall time
2 2
2
For example, the I Cn transfer clock frequency (fSCL) when fXX = 20 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(198 x 50 ns + 200 ns + 50 ns) 98.5 kHz
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m x T + tR + tF tR m/2 x T tF m/2 x T
SCLn
SCLn inversion
SCLn inversion
SCLn inversion
The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn), the CLXn bit of IIC function expansion register n (IICXn), and IICCEn1 and the IICCEn0 bits of IIC clock expansion register n (IICCEn) (n = 0, 1). Table 10-3. Selection Clock Setting
IICCEn Bit 1 Bit 0
IICXn Bit 0
CLXn
IICCLn Bit 3
SMCn
Bit 1
CLn1
Bit 0
CLn0
Selection Clock (fXX/m)
Settable Main Clock Frequency (fXX) Range
Operation Mode
IICCEn1 IICCEn0
x x x 0 1 0
x x x 1 0 0
1 0 0 0 0 0
1 1 1 1 1 1
0 0 1 1 1 1
x x 0 1 1 1
fXX/12 fXX/24 fXX/48 fXX/36 fXX/54 n=0 n=1
TM2 output/18 TM3 output/18
4.0 MHz to 4.19 MHz 4.0 MHz to 8.38 MHz 8.0 MHz to 16.67 MHz 12.0 MHz to 13.4 MHz 16.0 MHz to 20.0 MHzNote TM2 setting TM3 setting 2.0 MHz to 4.19 MHz 4.19 MHz to 8.38 MHz 8.38 MHz to 16.67 MHz 12.0 MHz to 13.4 MHz 16.0 MHz to 20.0 MHzNote
TM2 output/66 TM3 output/66
High-speed mode (SMCn = 1)
x x x 0 1 0
x x x 1 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 1 1 1
fXX/44 fXX/86 fXX/172 fXX/132 fXX/198 n=0 n=1
Normal mode (SMCn = 0)
TM2 setting TM3 setting
Other than above
Setting prohibited
Note Only in the V850/SB1 and the H versions of the V850/SB2. Remarks 1. n = 0, 1 2. x: don't care 3. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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(7) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1).
After reset: 00H 7 IICn (n = 0, 1)
R/W 6
Address: FFFFF348H, FFFFF358H 5 4 3 2 1 <0>
(8) Slave address registers 0, 1 (SVA0, SVA1) SVAn holds the I C bus's slave addresses. It can be read from or written to in 8-bit units, but bit 0 should be fixed to 0.
2
After reset: 00H 7 SVAn (n = 0, 1)
R/W 6
Address: FFFFF346H, FFFFF356H 5 4 3 2 1 0 0
10.3.3 (1)
I C bus mode functions
2
Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0, 1). SCLn .............. This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDAn .............. This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-
up resistor is required.
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Figure 10-7. Pin Configuration Diagram
VDD Slave device
Master device SCL Clock output VDD (Clock input) SDA Data output SDA Data output Clock input SCL (Clock output)
Data input
Data input
10.3.4 I C bus definitions and control methods The following section describes the I C bus's serial data communication format and the signals used by the I C bus. The transfer timing for the "start condition", "data", and "stop condition" output via the I C bus's serial data bus is shown below. Figure 10-8. I C Bus's Serial Data Transfer Timing
2 2 2 2
2
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDA Start Address condition R/W ACK Data ACK Data ACK Stop condition
The master device outputs the start condition, slave address, and stop condition. The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLn) is continuously output by the master device. However, in the slave device, the SCLn's low-level period can be extended and a wait can be inserted (n = 0, 1).
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(1)
Start condition The start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. The slave device includes hardware for detecting start conditions (n = 0, 1). Figure 10-9. Start Condition
H SCL
SDA
A start condition is output when bit 1 (STTn) of IIC control register n (IICCn) is set to 1 after a stop condition has been detected (SPDn: Bit 0 = 1 in the IIC status register n (IICSn)). When a start condition is detected, bit 1 (STDn) of IICSn is set to 1 (n = 0, 1). (2) Address The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (SVAn). If the address data matches the SVAn values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0, 1). Figure 10-10. Address
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3 Address
AD2
AD1
AD0
R/W
Note
INTIICn
Note INTIICn is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1
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The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are written together to the IIC shift register (IICn) and are then output. Received addresses are written to IICn (n = 0, 1). The slave address is assigned to the higher 7 bits of IICn. (3) Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 10-11. Transfer Direction Specification
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
Transfer direction specification Note INTIICn
Note INTIICn is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1
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(4)
Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for every 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device, it does not output an ACK signal after receiving the final data to be transmitted. The transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does not return an ACK signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an ACK signal may be caused by the following two factors. (a) Reception was not performed normally. (b) The final data was received. When the receiving device sets the SDAn line to low level during the ninth clock, the ACK signal becomes active (normal receive response). When bit 2 (ACKEn) of IIC control register n (IICCn) is set to 1, automatic ACK signal generation is enabled (n = 0, 1). Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRCn) of IIC status register n (IICSn) to be set. When this TRCn bit's value is 0, it indicates receive mode. Therefore, ACKEn should be set to 1 (n = 0, 1). When the slave device is receiving (when TRCn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting ACKEn to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting ACKEn to 0 will prevent the ACK signal from being returned. This prevents the MSB data from being output via the SDAn line (i.e., stops transmission) during transmission from the slave device. Figure 10-12. ACK Signal
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W ACK
Remark
n = 0, 1
When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn's eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0, 1). The ACK signal output method during data reception is based on the wait timing setting, as described below. When 8-clock wait is selected: ACK signal is output at the falling edge of the SCLn's eighth clock if ACKEn is set to 1 before wait cancellation. When 9-clock wait is selected: ACK signal is automatically output at the falling edge of the SCLn's eighth clock if ACKEn has already been set to 1.
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(5)
Stop condition When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0, 1). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. The slave device includes hardware that detects stop conditions. Figure 10-13. Stop Condition
H SCL
SDA
Remark
n = 0, 1
A stop condition is generated when bit 0 (SPTn) of IIC control register n (IICCn) is set to 1. When the stop condition is detected, bit 0 (SPDn) of IIC status register n (IICSn) is set to 1 and INTIICn is generated when bit 4 (SPIEn) of IICCn is set to 1 (n = 0, 1).
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(6)
Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). Figure 10-14. Wait Signal (1/2)
(a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master Master returns to high impedance but slave is in wait state (low level) IIC0 Wait after output of ninth clock IIC0 data write (cancel wait)
SCL
6
7
8
9
1
2
3
Slave Wait after output of eighth clock FFH is written to IIC0 or WREL is set to 1 IIC0 SCL
ACKE
H
Transfer lines
SCL
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
Remark
n = 0, 1
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Figure 10-14. Wait Signal (2/2)
(b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master IIC0
Master and slave both wait after output of ninth clock IIC0 data write (cancel wait)
SCL Slave IIC0 SCL
6
7
8
9
1
2
3
FFH is written to IIC0 or WREL is set to 1
ACKE Transfer lines SCL
H
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
Output according to previously set ACKE value
Remarks 1. ACKEn: WRELn: 2. n = 0, 1
Bit 2 of IIC control register n (IICCn) Bit 5 of IIC control register n (IICCn)
A wait may be automatically generated depending on the setting for bit 3 (WTIMn) of IIC control register n (IICCn) (n = 0, 1). Normally, when bit 5 (WRELn) of IICCn is set to 1 or when FFH is written to IIC shift register n (IICn), the wait status is canceled and the transmitting side writes data to IICn to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting bit 1 (STTn) of IICCn to 1 * By setting bit 0 (SPTn) of IICCn to 1
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10.3.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B L3: IICSn = 10XXX000B (WTIMn = 0) L4: IICSn = 10XXXX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
2
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX100B L3: IICSn = 10XXXX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 L5 SPTn = 1 AK L6 SP 7
L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B (WTIMn = 1) L3: IICSn = 10XXXX00B (WTIMn = 0) L4: IICSn = 10XXX110B (WTIMn = 0) L5: IICSn = 10XXX000B (WTIMn = 1) L6: IICSn = 10XXXX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 SPTn = 1 AK L4 SP 5
L1: IICSn = 10XXX110B L2: IICSn = 10XXXX00B L3: IICSn = 10XXX110B L4: IICSn = 10XXXX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X100B L3: IICSn = 1010XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(2) Slave device operation (when receiving slave address data (match with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0001X110B L4: IICSn = 0001XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW L3 AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0010X010B L4: IICSn = 0010X110B L5: IICSn = 0010XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0001X110B L5: IICSn = 0001XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW L4 AK L5 D7 to D0 AK L6 SP 7
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0010X010B L5: IICSn = 0010X110B L6: IICSn = 0010XX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 00000X10B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 1: IICSn = 00000001B
Remark
:
Generated only when SPIEn = 1
n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data
ST AD6 to AD0 RW AK L1 D7 to D0 AK D7 to D0 AK SP 2
L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
(b) When arbitration loss occurs during transmission of extension code
ST AD6 to AD0 RW L1 AK D7 to D0 AK D7 to D0 AK SP 2
L1:
IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing)
IICCn's LRELn is set to 1 by software 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) When arbitration loss occurs during data transfer <1> When WTIMn = 0
ST
AD6 to AD0
RW
AK L1
D7 to D0 L2
AK
D7 to D0
AK
SP 3
L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK SP 3
L1: IICSn = 10001110B L2: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
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(d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn)
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW AK L2 D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
<2> Extension code
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW L2 AK D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) IICCn's LRELn is set to 1 by software 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
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(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B 2: IICSn = 01000001B D7 to Dn SP 2
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B 3: IICSn = 01000001B D7 to D0 AK L2 SP 3
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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10.3.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) of IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 10-4. INTIICn Generation Timing and Wait Control
WTIMn During Slave Device Operation Address 0 1 9 9
Notes 1, 2 Notes 1, 2
During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9
Data Reception 8 9
Note 2 Note 2
Data Transmission 8 9
Note 2 Note 2
Notes 1.
The slave device's INTIICn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (SVAn). At this point, ACK is output regardless of the value set to bit 2 (ACKEn) of IICCn. For a slave device that has received an extension code, INTIICn occurs at the falling edge of the eighth clock.
2.
If the received address does not match the contents of slave address register n (SVAn), neither INTIICn nor a wait occurs.
Remarks 1. The numbers in the table indicate the number of the serial clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0, 1
(1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined regardless of the WTIMn bit. the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting bit 5 (WRELn) of IIC control register n (IICCn) to 1 * By writing to IIC shift register n (IICn) * By start condition setting (bit 1 (STTn) of IIC control register n (IICCn) = 1) * By step condition setting (bit 0 (SPTn) of IIC control register n (IICCn) = 1) When an 8-clock wait has been selected (WTIMn = 0), the output level of ACK must be determined prior to wait cancellation. Remark n = 0, 1 * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
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(5)
Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0, 1
10.3.7 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIICn) occurs when a local address has been set to slave address register n (SVAn) and when the address set to SVAn matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 10.3.8 Error detection In I C bus mode, the status of the serial data bus (SDAn) during data transmission is captured by IIC shift register n (IICn) of the transmitting device, so the IICn data prior to transmission can be compared with the transmitted IICn data to enable detection of transmission errors. compared data values do not match (n = 0, 1). 10.3.9 Extension code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXCn) is set for extension code reception and an interrupt request (INTIICn) is issued at the falling edge of the eighth clock (n = 0, 1). The local address stored in slave address register n (SVAn) is not affected. (2) If 11110xx0 is set to SVAn by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that INTIICn occurs at the falling edge of the eighth clock (n = 0, 1). * Higher 4 bits of data match: EXCn = 1 * 7 bits of data match: COIn = 1
Note Note 2 2
A transmission error is judged as having occurred when the
Note EXCn: Bit 5 of IIC status register n (IICSn) COIn: Bit 4 of IIC status register n (IICSn) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LRELn) of IIC control register n (IICCn) to 1 and the CPU will enter the next communication wait state.
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Table 10-5. Extension Code Bit Definitions
Slave Address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W Bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for a different bus format 10-bit slave address specification Description
10.3.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to 1
Note
), communication among the master devices is performed as the number of clocks is adjusted until the data
differs. This kind of operation is called arbitration (n = 0, 1). When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in IIC status register n (IICSn) is set at the timing by which the arbitration loss occurred, and the SCLn and SDAn lines are both set for high impedance, which releases the bus (n = 0, 1). The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALDn = 1 setting that has been made by software (n = 0, 1). For details of interrupt request timing, see 10.3.5 I C interrupt requests (INTIICn). Note STDn: Bit 1 of IIC status register n (IICSn) STTn: Bit 1 of IIC control register n (IICCn) Figure 10-15. Arbitration Timing Example
Master 1 SCL Hi-Z
2
SDA Master 2 SCL
Hi-Z Master 1 loses arbitration
SDA Transfer lines SCL
SDA
Remark
n = 0, 1
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Table 10-6. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When data is at low level while attempting to output a restart condition When stop condition is detected while attempting to output a restart condition When data is at low level while attempting to output a stop condition When SCLn is at low level while attempting to output a restart condition
Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer
Note 1
When stop condition is output (when SPIEn = 1)
Note 2 Note 1
At falling edge of eighth or ninth clock following byte transfer
Note 2
When stop condition is output (when SPIEn = 1)
At falling edge of eighth or ninth clock following byte transfer
Note 1
Notes 1.
When WTIMn (bit 3 of the IIC control register n (IICCn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1).
2.
When there is a possibility that arbitration will occur, set SPIEn = 1 for master device operation (n = 0, 1).
Remark
SPIEn: Bit 5 of IIC control register n (IICCn)
10.3.11 Wakeup function The I C bus slave function is a function that generates an interrupt request (INTIICn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. However, when a stop condition is detected, bit 5 (SPIEn) of IIC control register n (IICCn) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1).
2
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10.3.12 Communication reservation To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LRELn) of IIC control register n (IICCn) was set to 1) (n = 0, 1). If bit 1 (STTn) of IICCn is set while the bus is not used, a start condition is automatically generated and a wait status is set after the bus is released (after a stop condition is detected). When the bus release is detected (when a stop condition is detected), writing to IIC shift register n (IICn) causes the master's address transfer to start. At this point, bit 4 (SPIEn) of IICCn should be set (n = 0, 1). When STTn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0, 1). If the bus has been released ............................................. a start condition is generated If the bus has not been released (standby mode) ............. communication reservation To detect which operation mode has been determined for STTn, set STTn, wait for the wait period, then check the MSTSn (bit 7 of IIC status register n (IICSn)) (n = 0, 1). Wait periods, which should be set via software, are listed in Table 10-7. These wait periods can be set via the settings for bits 3, 1, and 0 (SMCn, CLn1, and CLn0) of IIC clock selection register n (IICCLn) (n = 0, 1). Table 10-7. Wait Periods
SMCn 0 0 0 0 1 1 1 1
CLn1 0 0 1 1 0 0 1 1
CLn0 0 1 0 1 0 1 0 1
Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks
32 clocks 13 clocks
Remark
n = 0, 1
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The communication reservation timing is shown below. Figure 10-16. Communication Reservation Timing
Program processing
STT =1
Write to IIC0
Hardware processing
Communication reservation
Set SPD and INTIIC0
Set STD
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SDA
Output by master with bus mastership
IICn: STTn: STDn: SPDn: Remark
IIC shift register n Bit 1 of IIC control register n (IICCn) Bit 1 of IIC status register n (IICSn) Bit 0 of IIC status register n (IICSn) n = 0, 1
Communication reservations are acknowledged at the following timing. After bit 1 (STDn) of IIC status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IIC control register n (IICCn) to 1 before a stop condition is detected (n = 0, 1). Figure 10-17. Timing for Acknowledging Communication Reservations
SCL
SDA
STD
SPD
Standby mode
Remark
n = 0, 1
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The communication reservation flowchart is illustrated below. Figure 10-18. Communication Reservation Flowchart
DI
SET1 STTn
; Sets STT flag (communication reservation).
Define communication reservation
; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM).
Wait
; Gets wait period set by software (see Table 10-7).
Note
(Communication reservation) Yes MSTSn = 0?
; Confirmation of communication reservation
No (Generate start condition) Cancel communication reservation ; Clear user flag.
IICn xxH
; IICn write operation
EI
Note The communication reservation operation executes a write to IIC shift register n (IICn) when a stop condition interrupt request occurs. Remark n = 0, 1
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10.3.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. (a) Set IIC clock selection register n (IICCLn). (b) Set bit 7 (IICEn) of IIC control register n (IICCn). (c) Set bit 0 of IICCn. Remark n = 0, 1
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10.3.14 Communication operations (1) Master operations The following is a flowchart of the master operations. Figure 10-19. Master Operation Flowchart
START
IICCLn xxH Select transfer clock.
IICCn xxH IICEn = SPIEn = WTIMn = 1
INTIICn = 1? Yes Start IICn write transfer.
No
; Stop condition detection
INTIICn = 1? Yes ACKDn = 1? Yes TRCn = 1? Yes (transmit) Start IICn write transfer.
No
No Generate stop condition. (no slave with matching address) No (receive) ; Address transfer completion WTIMn = 0 ACKEn = 1
WRELn = 1 Start reception. INTIICn = 1? No No
INTIICn = 1? Data processing Yes Data processing ACKDn = 1? No Yes
Transfer completed? Yes ACKEn = 0
No
Generate restart condition or stop condition.
Remark
n = 0, 1
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(2)
Slave operation An example of slave operation is shown below. Figure 10-20. Slave Operation Flowchart
START
IICCn xxH IICEn = 1
INTIICn = 1? Yes EXCn = 1? No No COIn = 1? Yes TRCn = 1? Yes (transmit) WTIMn = 1 Start IICn write transfer.
No
Yes
Communicate? Yes
No
LRELn = 1
No (receive)
WTIMn = 0 ACKEn = 1
WRELn = 1 Start reception. INTIICn = 1? Yes Data processing No INTIICn = 1? Yes Data processing ACKDn = 1? No START or STOP STOP (stop condition detection) End Yes Transfer completed? Yes ACKEn = 0 No No
Remark
n = 0, 1
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10.3.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device. The shift operation of IIC bus shift register n (IICn) is synchronized with the falling edge of the serial clock (SCLn). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAn pin. Data input via the SDAn pin is captured by IICn at the rising edge of SCLn. The data communication timing is shown below. Remark n = 0, 1
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Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H IICn address IICn data
Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When EXC = 1) TRCn L Receive H H L L L Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H H L L L IICn data IICn data
Transfer lines SCLn SDAn 8 D0 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H L L L Note Note IICn FFH Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H Transmit L H H IICn data IICn address
Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Stop condition IICn FFH Note 9 1 2
AD6 AD5 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn H H L L L Note IICn FFH Note
Note
(When SPIEn = 1) TRCn L Receive
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 R 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note H H IICn address IICn FFH Note
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H H L L L L IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H H L L Note Note IICn FFH Note IICn FFH Note
Transfer lines SCLn SDAn 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H L L L L IICn data IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 N-ACK Stop condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H H L L L IICn data 1 2 Note H H IICn FFH Note IICn address
AD6 AD5 Start condition
Note
To cancel master wait, write FFH to IICn or set WRELn. n = 0, 1
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10.4 I C Bus (B and H Versions)
To use the I C bus function, set the P10/SDA0, P12/SCL0, P20/SDA1, and P22/SCL1 pins to N-ch open drain output. The products with an on-chip I C bus are shown below. * V850/SB1: PD703030BY, 703031BY, 703032BY, 703033BY, 70F3030BY, 70F3032BY, 70F3033BY * V850/SB2: PD703034BY, 703035BY, 703036HY, 703037HY, 70F3035BY, 70F3036HY, 70F3037HY The I C0 and I C1 have the following two modes. * Operation stop mode * I C (Inter IC) bus mode (multimaster supported)
2 2 2 2 2
2
(1)
Operation stop mode This mode is used when serial transfers are not performed. consumption. It can therefore be used to reduce power
(2)
I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLn) line and a serial data bus (SDAn) line. This mode complies with the I C bus format and the master device can output "start condition", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these
2 2
2
received data by hardware. This function can simplify the part of application program that controls the I C bus. Since SCLn and SDAn are open drain outputs, the I Cn requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 0, 1
2
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Figure 10-23. Block Diagram of I C
Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Set Slave address register n (SVAn) Noise eliminator Match signal Start condition generator
2
SDAn
Clear
IIC shift register n (IICn)
DQ
SO latch CLn1, CLn0
N-ch open-drain output
Data hold time correction circuit
ACK output circuit
Wakeup controller ACK detector Start condition detector Stop condition detector Noise eliminator Interrupt request signal generator INTIICn
SCLn
Serial clock counter
Serial clock controller N-ch open-drain output fxx TMx output Prescaler
Serial clock wait controller
Bus status detector
CLDn DADn SMCn DFCn CLn1 CLn0 IIC clock selection register n (IICCLn)
CLXn
IICCEn1 IICCEn0
STCFn IICBSYn STCENn IICRSVn IIC flag register n (IICFn)
IIC function expansion register n (IICXn)
IIC clock expansion register n (IICCEn)
Internal bus
Remarks 1. n = 0, 1 2. TMx output n = 0: TM2 output n = 1: TM3 output
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A serial bus configuration example is shown below. Figure 10-24. Serial Bus Configuration Example Using I C Bus
+VDD +VDD
2
Master CPU1 Slave CPU1 Address 1
SDA SCL
Serial data bus Serial clock
SDA SCL
Master CPU2 Slave CPU2 Address 2
SDA SCL
Slave CPU3 Address 3
SDA SCL
Slave IC Address 4
SDA SCL
Slave IC Address N
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10.4.1 Configuration I Cn includes the following hardware (n = 0, 1). Table 10-8. Configuration of I Cn
Item Registers Configuration IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) IIC flag registers 0 and 1 (IICF0, IICF1) IIC clock selection registers 0 and 1 (IICCL0, IICCL1) IIC clock expansion registers 0 and 1 (IICCE0, IICCE1) IICC function expansion registers 0 and 1 (IICX0, IICX1)
2 2
Control registers
(1) IIC shift registers 0 and 1 (IIC0, IIC1) IICn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. IICn can be used for both transmission and reception (n = 0, 1). Write and read operations to IICn are used to control the actual transmit and receive operations. IICn is set by an 8-bit memory manipulation instruction. RESET input clears IIC0 and IIC1 to 00H. (2) Slave address registers 0 and 1 (SVA0, SVA1) SVAn sets local addresses when in slave mode. SVAn is set by an 8-bit memory manipulation instruction (n = 0, 1). RESET input clears SVA0 and SVA1 to 00H. (3) SO latch The SO latch is used to retain the SDAn pin's output level (n = 0, 1). (4) Wakeup controller This circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (SVAn) or when an extension code is received (n = 0, 1). (5) Clock selector This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received.
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(7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. * Eighth or ninth clock of the serial clock (set by WTIMn bit) * Interrupt request generated when a stop condition is detected (set by SPIEn bit) Remarks 1. n = 0, 1 2. WTIMn bit: SPIEn bit: Bit 3 of IIC control register n (IICCn) Bit 4 of IIC control register n (IICCn)
2
(8) Serial clock controller In master mode, this circuit generates the clock output via the SCLn pin from a sampling clock (n = 0, 1). (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK output circuit, stop condition detector, start condition detector, and ACK detector These circuits are used to output and detect various control signals. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the STTn bit is set. However, in the communication reservation disabled status (IICRSVn = 1), when the bus is not released (IICBSYn = 1), start condition requests are ignored and the STCFn bit is set. Remark IICRSVn bit: Bit 0 of IIC flag register n (IICFn) IICBSYn bit: Bit 6 of IIC flag register n (IICFn) STCFn bit: (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCENn bit. Remark STCENn bit: Bit 1 of IIC flag register n (IICFn) Bit 7 of IIC flag register n (IICFn)
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10.4.2 I C control register I C0 and I C1 are controlled by the following registers. * IIC control registers 0, 1 (IICC0, IICC1) * IIC status registers 0, 1 (IICS0, IICS1) * IIC flag registers 0, 1 (IICF0, IICF1) * IIC clock selection registers 0, 1 (IICCL0, IICCL1) * IIC clock expansion registers 0, 1 (IICCE0, IICCE1) * IIC function expansion registers 0, 1 (IICX0, IICX1) The following registers are also used. * IIC shift registers 0, 1 (IIC0, IIC1) * Slave address registers 0, 1 (SVA0, SVA1) (1) IIC control registers 0, 1 (IICC0, IICC1) IICCn is used to enable/disable I C operations, set wait timing, and set other I C operations. IICCn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0, 1). RESET input clears IICCn to 00H. Caution In I C0, I C1 bus mode, set the port 1 mode register (PM1), port 2 mode register (PM2), port 1 function register (PF1), and port 2 function register (PF2) as follows. In addition, set each output latch to 0.
Pin P10/SI0/SDA0 P12/SCK0/SCL0 P20/SI2/SDA1 P22/SCK2/SCL1 Port Mode Register PM10 of PM1 register = 0 PM12 of PM1 register = 0 PM20 of PM2 register = 0 PM22 of PM2 register = 0 Port Function Register PF10 of PF1 register = 1 PF12 of PF1 register = 1 PF20 of PF2 register = 1 PF22 of PF2 register = 1
2 2 2 2 2 2
2
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(1/4)
After reset: 00H <7> IICCn (n = 0, 1) IICEn 0 1 I2Cn operation enable/disable specification Stops operation. Presets IIC status register n (IICSn). Stops internal operation. Enables operation. Condition for setting (IICEn = 1) * Set by instruction IICEn R/W <6> LRELn <5> WRELn Address: FFFFF340H, FFFFF350H <4> SPIEn <3> WTIMn <2> ACKEn <1> STTn <0> SPTn
Condition for clearing (IICEn = 0) * Cleared by instruction * When RESET is input
LRELn 0 1 Normal operation
Exit from communications
This exits from the current communications operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLn and SDAn lines are set to high impedance. The following flags are cleared. * STDn * ACKDn * TRCn * COIn * EXCn * MSTSn * STTn * SPTn
The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LRELn = 0)
Note
Condition for setting (LRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
Note This flag's signal is invalid when IICEn = 0. Remark STDn: ACKDn: TRCn: COIn: EXCn: MSTSn: Bit 1 of IIC state register n (IICSn) Bit 2 of IIC state register n (IICSn) Bit 3 of IIC state register n (IICSn) Bit 4 of IIC state register n (IICSn) Bit 5 of IIC state register n (IICSn) Bit 7 of IIC state register n (IICSn)
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WRELn 0 1 Does not cancel wait Cancels wait. This setting is automatically cleared after wait is canceled.
Note
Wait cancellation control
Condition for clearing (WRELn = 0)
Condition for setting (WRELn = 1) * Set by instruction
* Automatically cleared after execution * When RESET is input
SPIEn 0 1 Disable Enable
Enable/disable generation of interrupt request when stop condition is detected
Condition for clearing (SPIEn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (SPIEn = 1) * Set by instruction
WTIMn 0
Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
1
This bit's setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn = 0) * Cleared by instruction * When RESET is input
Note
Condition for setting (WTIMn = 1) * Set by instruction
Note
This flag's signal is invalid when IICEn = 0. n = 0, 1
Remark
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ACKEn 0 1 Disable acknowledge. Enable acknowledge. During the ninth clock period, the SDA line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1.
Note
Acknowledge control
Condition for clearing (ACKEn = 0) * Cleared by instruction * When RESET is input
Condition for setting (ACKEn = 1) * Set by instruction
STTn 0 1 Does not generate a start condition.
Start condition trigger
When bus is released (in STOP mode): Generates a start condition (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCLn is changed to low level. When bus is not used: * When communication reservation function is enabled (IICRSVn = 0) Functions as the start condition reservation flag. When set, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSVn = 1) The STCFn bit is set. No start condition is generated. In the wait state (when master device) Generates a restart condition after releasing the wait.
Cautions concerning set timing * For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the ACKn period. Set during the wait period. * For slave: The communication reserved status is entered even if the communication reservation function is disabled (IICRSVn = 1). * Cannot be set at the same time as SPTn Condition for clearing (STTn = 0) * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (STTn = 1) * Set by instruction
Note
This flag's signal is invalid when IICEn = 0.
Remarks 1. Bit 1 (STTn) is 0 if it is read immediately after data setting. 2. IICRSVn: Bit 0 of IIC flag register n (IICFn) STCFn: 3. n = 0, 1 Bit 7 of IIC flag register n (IICFn)
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SPTn 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDAn line is changed from low level to high level and a stop condition is generated. Stop condition trigger
Cautions concerning setting timing * For master reception: Cannot be set during transfer. Can be set only when ACKEn has been set to 0 and during the wait period after slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the ACKn period. Set during the wait period. * Cannot be set at the same time as STTn. * SPTn can be set only when in master modeNote * When WTIMn has been set to 0, if SPTn is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. When a ninth clock must be output, WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks, and SPTn should be set during the wait period that follows output of the ninth clock. Condition for clearing (SPTn = 0) * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When LRELn = 1 * When IICEn = 0 * Cleared when RESET is input Condition for setting (SPTn = 1) * Set by instruction
Note Set SPTn only in master mode. However, when the IICRSVn bit of IIC flag register n (IICFn) is 0, SPTn must be set and a stop condition generated before the first stop condition is detected following the switch to operation enable status. For details, see 10.4.13 Cautions. Caution When bit 3 (TRCn) of IIC status register n (IICSn) is set to 1, WRELn is set during the ninth clock and wait is canceled, after which TRCn is cleared and the SDAn line is set to high impedance. Remarks 1. 2. Bit 0 (SPTn) is 0 if it is read immediately after data setting. n = 0, 1
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(2) IIC status registers 0, 1 (IICS0, IICS1) IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0, 1). RESET input sets IICSn to 00H. (1/3)
After reset: 00H <7> IICSn (n = 0, 1) MSTSn R <6> ALDn <5> EXCn Address: FFFFF342H, FFFFF352H <4> COIn <3> TRCn <2> ACKDn <1> STDn <0> SPDn
2
MSTSn 0 1
Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTSn = 1) * When a start condition is generated
Condition for clearing (MSTSn = 0) * When a stop condition is detected * When ALDn = 1 * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
ALDn 0 1
Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". MSTSn is cleared. Condition for setting (ALDn = 1)
Note
Condition for clearing (ALDn = 0) * Automatically cleared after IICSn is read * When IICEn changes from 1 to 0 * When RESET is input
* When the arbitration result is a "loss".
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICSn. Remark LRELn: Bit 6 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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EXCn 0 1 Extension code was not received. Extension code was received. Condition for setting (EXCn = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of extension code reception
Condition for clearing (EXCn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
COIn 0 1 Addresses do not match. Addresses match.
Detection of matching addresses
Condition for clearing (COIn = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
Condition for setting (COIn = 1) * When the received address matches the local address (SVAn) (set at the rising edge of the eighth clock).
TRCn 0 1
Detection of transmit/receive status Receive status (other than transmit status). The SDAn line is set for high impedance. Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at the falling edge of the first byte's ninth clock). Condition for setting (TRCn = 1) Master * When a start condition is generated Slave * When "1" is input by the first byte's LSB (transfer direction specification bit)
Condition for clearing (TRCn = 0) * When a stop condition is detected * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * Cleared by WRELn = 1Note * When ALDn changes from 0 to 1 * When RESET is input Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication
Note TRCn is cleared and SDAn line become high impedance when bit 5 (WRELn) of IIC control register n (IICCn) is set and wait state is released at ninth clock with bit 3 (TRCn) of IIC status register n (IICSn) = 1. Remarks 1. WRELn: Bit 5 of IIC control register n (IICCn) LRELn: IICEn: 2. n = 0, 1
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Bit 6 of IIC control register n (IICCn) Bit 7 of IIC control register n (IICCn)
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ACKDn 0 1 ACK was not detected. ACK was detected. Condition for setting (ACKD = 1) * After the SDAn line is set to low level at the rising edge of the SCLn's ninth clock Detection of ACK
Condition for clearing (ACKDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
STDn 0 1 Start condition was not detected.
Detection of start condition
Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STDn = 1) When a start condition is detected
Condition for clearing (STDn = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn = 1 * When IICEn changes from 1 to 0 * When RESET is input
SPDn 0 1 Stop condition was not detected.
Detection of stop condition
Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPDn = 1) When a stop condition is detected
Condition for clearing (SPDn = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When IICEn changes from 1 to 0 * When RESET is input
Remarks 1. LRELn: Bit 6 of IIC control register n (IICCn) IICEn: 2. n = 0, 1 Bit 7 of IIC control register n (IICCn)
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(3) IIC flag registers 0, 1 (IICF0, IICF1) IICFn is used to set the I Cn operation mode and to indicate the I C bus status. IICFn can be set by an 8-bit or 1-bit memory manipulation instruction. The IICRSVn bit is used to enable/disable the communication reservation function (see 10.4.12 Communication reservation). The STCENn bit is used to set the initial value of the IICBSYn bit (see 10.4.13 Cautions). The IICRSVn and STCENn bits can be written only when the I Cn operation is disabled (IICEn bit of IIC control register n (IICCn) = 0). After operation is enabled, the IICFn register can be read (n = 0). RESET input clears IICFn to 00H. When IICFn = 00H, these registers operate in the same way as the A versions. (1/2)
After reset: 00H <7> IICFn (n = 0, 1) STCFn 0 1 Generate start condition Clear STTn bit Condition for setting (STCFn = 1) * Clearing of STTn when communication reservation is disabled (IICRSVn = 1). STTn bit clear STCFn R/WNote <6> IICBSYn Address: FFFFF33CH, FFFFF33EH 5 0 4 0 3 0 2 0 <1> <0>
2 2 2
STCENn IICRSVn
Condition for clearing (STCFn = 0) * Clearing by setting STTn = 1 * RESET input
IICBSYn 0 1 Bus release status Bus communication status
I2Cn bus status
Condition for clearing (IICBSYn = 0) * Detection of stop condition * RESET input
Setting conditions (IICBSYn = 1) * Detection of start condition * Setting of IICEn when STCENn = 0
Note Bits 6 and 7 are read-only bits. Remark STTn: Bit 1 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
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STCENn 0 1 Initial start enable trigger After operation is enabled (IICEn = 1), cannot generate a start condition until a stop condition is detected. After operation is enabled (IICEn = 1), can generates a start condition without detecting a stop condition. Condition for setting (STCENn = 1) * Setting by instruction
Condition for clearing (STCENn = 0) * Detection of start condition * RESET input
IICRSVn 0 1
Communication reservation function disable bit Enable communication reservation Disable communication reservation Condition for setting (IICRSVn = 1) * Setting by instruction
Condition for clearing (IICRSVn = 0) * Clearing by instruction * RESET input
Cautions 1. Write to the STCENn bit only when the operation is stopped (IICEn = 0). 2. As the bus release status (IICBSYn = 0) is recognized immediately after I C operation is enabled regardless of the actual bus status when STCENn = 1, when generating the first start condition (STTn = 1), it is necessary to verify that the bus has been released in order to prevent such communications from being destroyed. 3. Write to the IICRSVn bit only when the operation is stopped (IICEn = 0). Remark STTn: Bit 1 of IIC control register n (IICCn) IICEn: Bit 7 of IIC control register n (IICCn)
2
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(4) IIC clock selection registers 0, 1 (IICCL0, IICCL1) IICCLn is used to set the transfer clock for the I Cn bus. IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set using CLXn bit of IIC function expansion register n (IICXn) in combination with bits IICCEn1 and IICCEn0 of IIC clock expansion register n (IICCEn) (n = 0, 1) (see 10.4.2 (7) I Cn transfer clock setting method). RESET input clears IICCLn to 00H.
After reset: 00H 7 IICCLn (n = 0, 1) 0 R/W
Note 2 2
Address: FFFFF344H, FFFFF354H <5> CLDn <4> DADn 3 SMCn 2 DFCn 1 CLn1 0 CLn0
6 0
CLDn 0 1
Detection of SCLn line level (valid only when IICEn = 1) SCLn line was detected at low level. SCLn line was detected at high level. Condition for setting (CLDn = 1) * When the SCLn line is at high level
Condition for clearing (CLDn = 0) * When the SCLn line is at low level * When IICEn = 0 * When RESET is input
DADn 0 1
Detection of SDAn line level (valid only when IICEn = 1) SDAn line was detected at low level. SDAn line was detected at high level. Condition for setting (DADn = 1) * When the SDAn line is at high level
Condition for clearing (DADn = 0) * When the SDAn line is at low level * When IICEn = 0 * When RESET is input
SMCn 0 1 Operates in standard mode. Operates in high-speed mode.
Operation mode switching
DFCn 0 1 Digital filter off. Digital filter on.
Digital filter operation control
Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFCn switching (on/off).
Note Bits 4 and 5 are read only bits. Caution Remark Be sure to set bits 7 and 6 to 0. IICEn: Bit 7 of IIC control register n (IICCn)
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(5) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I Cn (valid only in high-speed mode). IICXn is set by an 8-bit or 1-bit memory manipulation instruction. Set the CLXn bit in combination with the SMCn, DFCn, CLn1, and the CLn0 bits of IIC clock selection register n (IICCLn) and the IICCEn1 and IICCEn0 bits of IIC clock expansion register n (IICCEn) (see 10.4.2 (7) I Cn transfer clock setting method) (n = 0, 1). RESET input clears these registers to 00H.
2 2
After reset: 00H 7 IICXn (n = 0, 1) 0
R/W 6 0
Address: FFFFF34AH, FFFFF35AH 5 0 4 0 3 0 2 0 1 0 <0> CLXn
(6) IIC clock expansion registers 0, 1 (IICCE0, IICCE1) These registers set the transfer clock expansion of I Cn. IICCEn is set by an 8-bit memory manipulation instruction. Set the IICCEn1 and IICCEn0 bits in combination with the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) and the CLXn bit of IIC function expansion register n (IICXn) (see 10.4.2 (7) I Cn transfer clock setting method) (n = 0, 1). RESET input clears these registers to 00H.
2 2
After reset: 00H 7 IICCEn (n = 0, 1) 0
R/W 6 0
Address: FFFFF34CH, FFFFF35CH 5 0 4 0 3 0 2 0 1 IICCEn1 0 IICCEn0
(7) I Cn transfer clock setting method The I Cn transfer clock frequency (fSCL) is calculated using the following expression (n = 0, 1). fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see Table 10-9 Selection Clock Setting.) T: tR: tF: 1/fXX SCLn rise time SCLn fall time
2 2
2
For example, the I Cn transfer clock frequency (fSCL) when fXX = 20 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(198 x 50 ns + 200 ns + 50 ns) 98.5 kHz
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m x T + tR + tF tR m/2 x T tF m/2 x T
SCLn
SCLn inversion
SCLn inversion
SCLn inversion
The selection clock is set using a combination of the SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn), the CLXn bit of IIC function expansion register n (IICXn), and IICCEn1 and the IICCEn0 bits of IIC clock expansion register n (IICCEn) (n = 0, 1). Table 10-9. Selection Clock Setting
IICCEn Bit 1 Bit 0
IICXn Bit 0
CLXn
IICCLn Bit 3
SMCn
Bit 1
CLn1
Bit 0
CLn0
Selection Clock (fXX/m)
Settable Main Clock Frequency (fXX) Range
Operation Mode
IICCEn1 IICCEn0
x x x 0 1 0
x x x 1 0 0
1 0 0 0 0 0
1 1 1 1 1 1
0 0 1 1 1 1
x x 0 1 1 1
fXX/12 fXX/24 fXX/48 fXX/36 fXX/54 n=0 n=1
TM2 output/18 TM3 output/18
4.0 MHz to 4.19 MHz 4.0 MHz to 8.38 MHz 8.0 MHz to 16.67 MHz 12.0 MHz to 13.4 MHz 16.0 MHz to 20.0 MHzNote TM2 setting TM3 setting 2.0 MHz to 4.19 MHz 4.19 MHz to 8.38 MHz 8.38 MHz to 16.67 MHz 12.0 MHz to 13.4 MHz 16.0 MHz to 20.0 MHzNote
TM2 output/66 TM3 output/66
High-speed mode (SMCn = 1)
x x x 0 1 0
x x x 1 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 1 1 1
fXX/44 fXX/86 fXX/172 fXX/132 fXX/198 n=0 n=1
Normal mode (SMCn = 0)
TM2 setting TM3 setting
Other than above
Setting prohibited
Note This cannot be set in the PD703034BY, 703035BY, and 70F3035BY. Remarks 1. n = 0, 1 2. x: don't care 3. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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(8) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0, 1).
After reset: 00H 7 IICn (n = 0, 1)
R/W 6
Address: FFFFF348H, FFFFF358H 5 4 3 2 1 <0>
(9) Slave address registers 0, 1 (SVA0, SVA1) SVAn holds the I C bus's slave addresses. It can be read from or written to in 8-bit units, but bit 0 should be fixed as 0.
2
After reset: 00H 7 SVAn (n = 0, 1)
R/W 6
Address: FFFFF346H, FFFFF356H 5 4 3 2 1 0 0
10.4.3 (1)
I C bus mode functions
2
Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0, 1). SCLn ...............This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDAn ..............This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-
up resistor is required.
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Figure 10-25. Pin Configuration Diagram
VDD Slave device
Master device SCL Clock output VDD (Clock input) SDA Data output SDA Data output Clock input SCL (Clock output)
Data input
Data input
10.4.4 I C bus definitions and control methods The following section describes the I C bus's serial data communication format and the signals used by the I C bus. The transfer timing for the "start condition", "data", and "stop condition" output via the I C bus's serial data bus is shown below. Figure 10-26. I C Bus's Serial Data Transfer Timing
2 2 2 2
2
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDA Start Address condition R/W ACK Data ACK Data ACK Stop condition
The master device outputs the start condition, slave address, and stop condition. The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLn) is continuously output by the master device. However, in the slave device, the SCLn's low-level period can be extended and a wait can be inserted (n = 0, 1).
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(1)
Start condition A start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. The slave device includes hardware for detecting start conditions (n = 0, 1). Figure 10-27. Start Conditions
H SCL
SDA
A start condition is output when IIC control register n (IICCn)'s bit 1 (STTn) is set to 1 after a stop condition has been detected (SPDn: Bit 0 = 1 in the IIC status register n (IICSn)). When a start condition is detected, IICSn's bit 1 (STDn) is set to 1 (n = 0, 1). (2) Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (SVAn). If the address data matches the SVAn values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0, 1). Figure 10-28. Address
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3 Address
AD2
AD1
AD0
R/W
Note
INTIICn
Note INTIICn is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1
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The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are together written to the IIC shift register (IICn) and are then output. Received addresses are written to IICn (n = 0, 1). The slave address is assigned to the higher 7 bits of IICn. (3) Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 10-29. Transfer Direction Specification
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
Transfer direction specification Note INTIICn
Note INTIICn is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1
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(4)
Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device The normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device, it does not output an ACK signal after receiving the final data to be transmitted. transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does not return an ACK signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an ACK signal may be caused by the following two factors. (a) Reception was not performed normally. (b) The final data was received. When the receiving device sets the SDAn line to low level during the ninth clock, the ACK signal becomes active (normal receive response). When bit 2 (ACKEn) of IIC control register n (IICCn) is set to 1, automatic ACK signal generation is enabled (n = 0, 1). Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRCn) of IIC status register n (IICSn) to be set. When this TRCn bit's value is 0, it indicates receive mode. Therefore, ACKEn should be set to 1 (n = 0, 1). When the slave device is receiving (when TRCn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting ACKEn to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting ACKEn to 0 will prevent the ACK signal from being returned. This prevents the MSB data from being output via the SDAn line (i.e., stops transmission) during transmission from the slave device. Figure 10-30. ACK Signal
SCLn 1 2 3 4 5 6 7 8 9
SDAn
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W ACK
Remark
n = 0, 1
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When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn's eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0, 1). The ACK signal output method during data reception is based on the wait timing setting, as described below. When 8-clock wait is selected: ACK signal is output at the falling edge of the SCLn's eighth clock if ACKEn is set to 1 before wait cancellation. When 9-clock wait is selected: ACK signal is automatically output at the falling edge of the SCLn's eighth clock if ACKEn has already been set to 1. (5) Stop condition When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0, 1). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. The slave device includes hardware that detects stop conditions. Figure 10-31. Stop Condition
H SCL
SDA
Remark
n = 0, 1
A stop condition is generated when bit 0 (SPTn) of IIC control register n (IICCn) is set to 1. When the stop condition is detected, bit 0 (SPDn) of IIC status register n (IICSn) is set to 1 and INTIICn is generated when bit 4 (SPIEn) of IICCn is set to 1 (n = 0, 1).
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(6)
Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). Figure 10-32. Wait Signal (1/2)
(a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IIC0 data write (cancel wait)
IIC0
SCL
6
7
8
9
1
2
3
Slave Wait after output of eighth clock. FFH is written to IIC0 or WREL is set to 1. IIC0 SCL
ACKE
H
Transfer lines
SCL
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
Remark
n = 0, 1
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Figure 10-32. Wait Signal (2/2)
(b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1)
Master IIC0
Master and slave both wait after output of ninth clock. IIC0 data write (cancel wait)
SCL Slave IIC0 SCL
6
7
8
9
1
2
3
FFH is written to IIC0 or WREL is set to 1.
ACKE Transfer lines SCL
H
6
7
8
9
1
2
3
SDA
D2
D1
D0
ACK
D7
D6
D5
Output according to previously set ACKE value
Remarks 1. ACKEn: WRELn: 2. n = 0, 1
Bit 2 of IIC control register n (IICCn) Bit 5 of IIC control register n (IICCn)
A wait may be automatically generated depending on the setting for bit 3 (WTIMn) of IIC control register n (IICCn) (n = 0, 1). Normally, when bit 5 (WRELn) of IICCn is set to 1 or when FFH is written to IIC shift register n (IICn), the wait status is canceled and the transmitting side writes data to IICn to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting bit 1 (STTn) of IICCn to 1 * By setting bit 0 (SPTn) of IICCn to 1
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10.4.5 I C interrupt requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0, 1). (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B L3: IICSn = 10XXX000B (WTIMn = 0) L4: IICSn = 10XXXX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
2
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 10XXX110B L2: IICSn = 10XXX100B L3: IICSn = 10XXXX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn = 0
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 L5 SPTn = 1 AK L6 SP 7
L1: IICSn = 10XXX110B L2: IICSn = 10XXX000B (WTIMn = 1) L3: IICSn = 10XXXX00B (WTIMn = 0) L4: IICSn = 10XXX110B (WTIMn = 0) L5: IICSn = 10XXX000B (WTIMn = 1) L6: IICSn = 10XXXX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 SPTn = 1 AK L4 SP 5
L1: IICSn = 10XXX110B L2: IICSn = 10XXXX00B L3: IICSn = 10XXX110B L4: IICSn = 10XXXX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn = 0
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X000B L3: IICSn = 1010X000B (WTIMn = 1) L4: IICSn = 1010XX00B 5: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1010X110B L2: IICSn = 1010X100B L3: IICSn = 1010XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(2) Slave device operation (when receiving slave address data (match with SVAn)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 L1: IICSn = 0001X110B L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B D7 to D0 AK L2 D7 to D0 AK L3 SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0001X110B L4: IICSn = 0001XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW L3 AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 0010X010B L4: IICSn = 0010X110B L5: IICSn = 0010XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0001X110B L2: IICSn = 0001XX00B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn = 0
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0001X110B L4: IICSn = 0001X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, match with SVAn)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK L5 SP 6
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0001X110B L5: IICSn = 0001XX00B 6: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn = 0 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW L3 AK D7 to D0 L4 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 0010X010B L4: IICSn = 0010X000B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, extension code reception)
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW L4 AK L5 D7 to D0 AK L6 SP 7
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 0010X010B L5: IICSn = 0010X110B L6: IICSn = 0010XX00B 7: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn = 0 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK ST AD6 to AD0 RW AK L3 D7 to D0 AK SP 4
L1: IICSn = 0010X010B L2: IICSn = 0010X000B L3: IICSn = 00000X10B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1 (after restart, mismatch with address (= not extension code))
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 ST AD6 to AD0 RW AK L4 D7 to D0 AK SP 5
L1: IICSn = 0010X010B L2: IICSn = 0010X110B L3: IICSn = 0010XX00B L4: IICSn = 00000X10B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 1: IICSn = 00000001B
Remark
:
Generated only when SPIEn = 1
n = 0, 1 (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1> When WTIMn = 0
ST AD6 to AD0 RW AK L1 D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X000B L3: IICSn = 0001X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 SP 4
L1: IICSn = 0101X110B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0001X100B L3: IICSn = 0001XX00B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(b) When arbitration loss occurs during transmission of extension code <1> When WTIMn = 0
ST AD6 to AD0 RW L1 AK D7 to D0 L2 AK D7 to D0 L3 AK SP 4
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X000B L3: IICSn = 0010X000B 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW L1 AK L2 D7 to D0 AK L3 D7 to D0 AK L4 SP 5
L1: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) L2: IICSn = 0010X110B L3: IICSn = 0010X100B L4: IICSn = 0010XX00B 5: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data
ST AD6 to AD0 RW AK L1 D7 to D0 AK D7 to D0 AK SP 2
L1: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
(b) When arbitration loss occurs during transmission of extension code
ST AD6 to AD0 RW L1 AK D7 to D0 AK D7 to D0 AK SP 2
L1:
IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing)
IICCn's LRELn is set to 1 by software 2: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(c) When arbitration loss occurs during data transfer <1> When WTIMn = 0
ST
AD6 to AD0
RW
AK L1
D7 to D0 L2
AK
D7 to D0
AK
SP 3
L1: IICSn = 10001110B L2: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
<2> When WTIMn = 1
ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK SP 3
L1: IICSn = 10001110B L2: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 n = 0, 1
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(d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVAn)
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW AK L2 D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 01000110B (Example: when ALDn is read during interrupt servicing) 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
<2> Extension code
ST AD6 to AD0 RW AK L1 D7 to Dn ST AD6 to AD0 RW L2 AK D7 to D0 AK SP 3
L1: IICSn = 1000X110B L2: IICSn = 0110X010B (Example: when ALDn is read during interrupt servicing) IICCn's LRELn is set to 1 by software 3: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
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(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B 2: IICSn = 01000001B D7 to Dn SP 2
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care Dn = D6 to D0 n = 0, 1
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000100B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn = 1
STTn = 1 ST AD6 to AD0 RW AK L1 L1: IICSn = 1000X110B L2: IICSn = 1000XX00B 3: IICSn = 01000001B D7 to D0 AK L2 SP 3
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn = 1
SPTn = 1 ST AD6 to AD0 RW AK L1 D7 to D0 AK L2 D7 to D0 AK L3 D7 to D0 AK SP 4
L1: IICSn = 1000X110B L2: IICSn = 1000XX00B L3: IICSn = 01000000B (Example: when ALDn is read during interrupt servicing) 4: IICSn = 00000001B
Remark
L: Always generated : Generated only when SPIEn = 1 X: don't care n = 0, 1
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10.4.6 Interrupt request (INTIICn) generation timing and wait control The setting of bit 3 (WTIMn) in IIC control register n (IICCn) determines the timing by which INTIICn is generated and the corresponding wait control, as shown below (n = 0, 1). Table 10-10. INTIICn Generation Timing and Wait Control
WTIMn During Slave Device Operation Address 0 1 9 9
Notes 1, 2 Notes 1, 2
During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9
Data Reception 8 9
Note 2 Note 2
Data Transmission 8 9
Note 2 Note 2
Notes 1.
The slave device's INTIICn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (SVAn). At this point, ACK is output regardless of the value set to IICCn's bit 2 (ACKEn). For a slave device that has received an extension code, INTIICn occurs at the falling edge of the eighth clock.
2.
If the received address does not match the contents of slave address register n (SVAn), neither INTIICn nor a wait occurs.
Remarks 1. The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0, 1
(1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined regardless of the WTIMn bit. the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting bit 5 (WRELn) of IIC control register n (IICCn) to 1 * By writing to IIC shift register n (IICn) * By start condition setting (bit 1 (STTn) of IIC control register n (IICCn) = 1) * By step condition setting (bit 0 (SPTn) of IIC control register n (IICCn) = 1) When an 8-clock wait has been selected (WTIMn = 0), the output level of ACK must be determined prior to wait cancellation. Remark n = 0, 1 * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
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(5)
Stop condition detection INTIICn is generated when a stop condition is detected. Remark n = 0, 1
10.4.7 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIICn) occurs when a local address has been set to slave address register n (SVAn) and when the address set to SVAn matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 10.4.8 Error detection In I C bus mode, the status of the serial data bus (SDAn) during data transmission is captured by IIC shift register n (IICn) of the transmitting device, so the IICn data prior to transmission can be compared with the transmitted IICn data to enable detection of transmission errors. compared data values do not match (n = 0, 1). 10.4.9 Extension code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXCn) is set for extension code reception and an interrupt request (INTIICn) is issued at the falling edge of the eighth clock (n = 0, 1). The local address stored in slave address register n (SVAn) is not affected. (2) If 11110xx0 is set to SVAn by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that INTIICn occurs at the falling edge of the eighth clock (n = 0, 1). * Higher 4 bits of data match: EXCn = 1 * 7 bits of data match: COIn = 1
Note Note 2 2
A transmission error is judged as having occurred when the
Note EXCn: Bit 5 of IIC status register n (IICSn) COIn: Bit 4 of IIC status register n (IICSn) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LRELn) of IIC control register n (IICCn) to 1 and the CPU will enter the next communication wait state.
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Table 10-11. Extension Code Bit Definitions
Slave Address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W Bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for different bus format 10-bit slave address specification Description
10.4.10 Arbitration When several master devices simultaneously output a start condition (when STTn is set to 1 before STDn is set to 1
Note
), communication among the master devices is performed as the number of clocks is adjusted until the data
differs. This kind of operation is called arbitration (n = 0, 1). When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in IIC status register n (IICSn) is set via the timing by which the arbitration loss occurred, and the SCLn and SDAn lines are both set for high impedance, which releases the bus (n = 0, 1). The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALDn = 1 setting that has been made by software (n = 0, 1). For details of interrupt request timing, see 10.4.5 I C interrupt requests (INTIICn). Note STDn: Bit 1 of IIC status register n (IICSn) STTn: Bit 1 of IIC control register n (IICCn)
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Figure 10-33. Arbitration Timing Example
Master 1 SCL Hi-Z
SDA Master 2 SCL
Hi-Z Master 1 loses arbitration
SDA Transfer lines SCL
SDA
Remark
n = 0, 1
Table 10-12. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When data is at low level while attempting to output a restart condition When stop condition is detected while attempting to output a restart condition When data is at low level while attempting to output a stop condition When SCLn is at low level while attempting to output a restart condition
Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer
Note 1
When stop condition is output (when SPIEn = 1)
Note 2 Note 1
At falling edge of eighth or ninth clock following byte transfer
Note 2
When stop condition is output (when SPIEn = 1)
At falling edge of eighth or ninth clock following byte transfer
Note 1
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Notes 1.
When WTIMn (bit 3 of the IIC control register n (IICCn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock (n = 0, 1).
2.
When there is a possibility that arbitration will occur, set SPIEn = 1 for master device operation (n = 0, 1).
Remark
SPIEn: Bit 5 of IIC control register n (IICCn)
10.4.11 Wakeup function The I C bus slave function is a function that generates an interrupt request (INTIICn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. However, when a stop condition is detected, bit 5 (SPIEn) of IIC control register n (IICCn) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1).
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10.4.12 Communication reservation (1) When communication reservation function is enabled (IICRSVn of IICFn register = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when LRELn of IIC control register n (IICCn) was set to "1") (n = 0, 1). If bit 1 (STTn) of IICCn is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). When the bus release is detected (when a stop condition is detected), writing to IIC shift register n (IICn) causes the master's address transfer to start. At this point, IICCn's bit 4 (SPIEn) should be set (n = 0, 1). When STTn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0, 1). If the bus has been released ............................................................a start condition is generated If the bus has not been released (standby mode) ............................communication reservation To detect which operation mode has been determined for STTn, set STTn, wait for the wait period, then check the MSTSn (bit 7 of IIC status register n (IICSn)) (n = 0, 1). Wait periods, which should be set via software, are listed in Table 10-13. These wait periods can be set via the settings for bits 3, 1, and 0 (SMCn, CLn1, and CLn0) in IIC clock selection register n (IICCLn) (n = 0, 1). Table 10-13. Wait Periods
SMCn 0 0 0 0 1 1 1 1
CLn1 0 0 1 1 0 0 1 1
CLn0 0 1 0 1 0 1 0 1
Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks
32 clocks 13 clocks
Remark
n = 0, 1
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The communication reservation timing is shown below. Figure 10-34. Communication Reservation Timing
Program processing
STT =1
Write to IIC0
Hardware processing
Communication reservation
Set SPD and INTIIC0
Set STD
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SDA
Output by master with bus access
IICn: STTn: STDn: SPDn: Remark
IIC shift register n Bit 1 of IIC control register n (IICCn) Bit 1 of IIC status register n (IICSn) Bit 0 of IIC status register n (IICSn) n = 0, 1
Communication reservations are accepted via the following timing. After bit 1 (STDn) of IIC status register n (IICSn) is set to "1", a communication reservation can be made by setting bit 1 (STTn) of IIC control register n (IICCn) to "1" before a stop condition is detected (n = 0, 1). Figure 10-35. Timing for Accepting Communication Reservations
SCL
SDA
STD
SPD
Standby mode
Remark
n = 0, 1
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The communication reservation flowchart is illustrated below. Figure 10-36. Communication Reservation Flowchart
DI
SET1 STTn
Sets STT bit (communication reservation).
Define communication reservation
Defines that communication reservation is in effect (defines and sets user flag to any part of RAM).
Wait
Secures wait period set by software (see Table 10-13).
Note
(Communication reservation) Yes MSTSn = 0?
Confirmation of communication reservation
No (Generate start condition) Cancel communication reservation Clear user flag.
IICn xxH
IICn write operation
EI
Note The communication reservation operation executes a write to IIC shift register n (IICn) when a stop condition interrupt request occurs. Remark n = 0, 1
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(2) When communication reservation function is disabled (IICRSVn of IICFn register = 1) If the STTn bit of the IICn register is set when the bus is not participating in the current communication while bus communication is in progress, this request is rejected and a start condition is not generated. There are two modes under which the bus is not participating in communication. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when LRELn of IIC control register n (IICCn) was set to "1") (n = 0, 1). To detect whether a start condition was generated or the request was rejected, check the STCFn flag of the IICFn register. Wait for the period shown in Table 10-14 using software since it takes the period to set the STCFn flag from when STTn = 1 is set. Table 10-14. Wait Time
IICCEn1 X X X 0 0 1 IICCEn0 X X X 0 1 0 CLn1 0 0 1 1 1 1 CLn0 0 1 0 1 1 1 Wait Time 3 clocks 3 clocks 6 clocks 3xN 6 clocks 9 clocks
Remarks 1. N: TM2, TM3 output X: Don't care 2. n = 0, 1
Caution
Do not set STTn = 1 if the slave status is entered on an address match or extension code reception (at the timing shown in Figure 10-37). If it is set, the communication reservation status is entered. Figure 10-37. Timing at Which STTn = 1 Cannot Be Set
SDAn SCLn IICBSYn
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK
D7 D6 D5
D2 D1 D0 ACK
When COIn = 1 or EXCn = 1, setting STTn = 1 is disabled Rising edge of address 8 clock Stop condition
Start condition
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Figure 10-38. Master Communication Start or Stop Flowchart
DI
IICBSYn = 0 ? Yes SET1 STTn
No
Sets STTn bit
EI
EI
Wait
Secures wait period by software (see Table 10-14)
STCFn = 0 ? Yes IICn XXH
No
Bus communication status Master communication stop
IICn write operation
Remark
n = 0, 1
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10.4.13 Cautions (a) When STCENn of IICFn register = 0 Immediately after the I C operation is enabled, the communication status (IICBSYn of IICFn register = 1) is recognized regardless of the actual bus status. To perform master communication in the status in which the stop condition is not detected, first generate a stop condition to release the bus and then perform master communication. Use the following sequence for generating a stop condition. <1> Set IIC clock selection register n (IICCLn) <2> Set the IICEn bit of IIC control register n (IICCn) <3> Set the SPTn bit of the IICCn register (b) When STCENn of IICFn register = 1 Immediately after the I C operation is enabled, the bus released status (IICBSYn = 0) is recognized regardless of the actual bus status. To issue the first start condition (STTn of IICCn register = 1), check that the bus is released in order to prevent disturbing other communications. Remark n = 0, 1
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10.4.14 Communication operations (1) Master operations The following shows an example of the master communication flowchart when the communication reservation function is enabled (IICRSVn = 0) and when communication is started after a stop condition is detected (STCENn = 0). Figure 10-39. Master Operation Flowchart (1)
START IICCLn XXH Select transfer clock. IICCn XXH IICEn = SPIEn = WTIMn = 1
INTIICn = 1?
No
Yes (stop condition detection)
STTn = 1
Wait
Wait period secured by software (see Table 10-13)
MSTSn = 1?
No
Communication reservation No
Yes (start condition generation)
INTIICn = 1? Yes
Start IICn write transfer
Stop condition detection, start condition generation due to communication reservation No
INTIICn = 1? Yes ACKDn = 1? Yes Address transfer completion TRCn = 1? Yes (transmit) Start IICn write transfer
No Generate stop condition (no slave with matching address) No (receive) End
WTIMn = 0 ACKEn = 1 INTIICn = 1? No WRELn = 1 Start reception Data processing No
ACKDn = 1? No
Yes
INTIICn = 1? Yes Data processing
No (restart)
Transfer complete? Transfer complete? Yes Generate stop condition SPTn = 1 Yes ACKEn = 0
No
End
Remark
n = 0, 1
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(2) Master operation The following shows an example of the master communication flowchart when the communication reservation function is disabled (IICRSVn = 1) and when communication is started without detecting a stop condition (STCENn = 1). Figure 10-40. Master Operation Flowchart (2)
START IICCLn XXH IICFn XXH IICCn XXH IICEn = SPIEn = WTIMn = 1 Transfer clock selection IICFn register setting
IICCn register initial setting
IICBSYn = 0? Yes STTn = 1
No
Insert wait
Wait period secured by software (see Table 10-13)
STCFn = 0? Yes Start IICn write transfer
No
Master communication is stopped Stop master communication because bus is occupied
INTIICn = 1?
No
Yes (address transfer complete) ACKDn = 1? Yes TRCn = 1? Yes (transmit) Start IICn write transfer WRELn = 1 Start reception INTIICn = 1? Yes Data processing No No No (receive) Generate stop condition (no slave with matching address) WTIMn = 0 ACKEn = 1 No
End
INTIICn = 1? Yes Data processing
ACKDn = 1? Yes
No No
Reception completed? Yes ACKEn = 0
No (restart)
Transfer completed? Yes SPTn = 1 Generate stop condition
End
Remark
n = 0, 1
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(3) Slave operation The following shows an example of the slave communication flowchart. Figure 10-41. Slave Operation Flowchart
START
IICCn XXH IICEn = 1
INTIICn = 1? Yes EXCn = 1? No No COIn = 1? Yes TRCn = 1? Yes (transmit) WTIMn = 1 Start IICn write transfer
No
Yes Bus participates in communication? Yes
No
LRELn = 1
No (receive) WTIMn = 0 ACKEn = 1
WRELn = 1 Start reception INTIICn = 1? Yes Data processing Yes Data processing ACKDn = 1? No Yes START (restart detection) START or STOP STOP (stop condition detection) End ACKEn = 0 Yes Transfer completed? No No INTIICn = 1? No
Remark
n = 0, 1
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10.4.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of IIC status register n (IICSn)) that specifies the data transfer direction and then starts serial communication with the slave device. IIC bus shift register n (IICn)'s shift operation is synchronized with the falling edge of the serial clock (SCLn). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAn pin. Data input via the SDAn pin is captured by IICn at the rising edge of SCLn. The data communication timing is shown below. Remark n = 0, 1
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Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H IICn address IICn data
Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When EXC = 1) TRCn L Receive H H L L L Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H H L L L IICn data IICn data
Transfer lines SCLn SDAn 8 D0 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H L L L Note Note IICn FFH Note IICn FFH Note
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-42. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H Transmit L H H IICn data IICn address
Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Stop condition IICn FFH Note 9 1 2
AD6 AD5 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn H H L L L Note IICn FFH Note
Note
(When SPIEn = 1) TRCn L Receive
Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 R 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note H H IICn address IICn FFH Note
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H H L L L L IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H H L L Note Note IICn FFH Note IICn FFH Note
Transfer lines SCLn SDAn 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5
Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H L L L L IICn data IICn data
Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1
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Figure 10-43. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition
Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 N-ACK Stop condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H H L L L IICn data 1 2 Note H H IICn FFH Note IICn address
AD6 AD5 Start condition
Note Remark
To cancel master wait, write FFH to IICn or set WRELn. n = 0, 1
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10.5 Asynchronous Serial Interface (UART0, UART1)
UARTn (n = 0, 1) has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. consumption. (2) Asynchronous serial interface mode This mode enables full-duplex operation which transmits and receives one byte of data after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates. In addition, a baud rate based on divided clock input to the ASCKn pin can also be defined. The UARTn baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 Kbps). 10.5.1 Configuration The UARTn includes the following hardware. Table 10-15. Configuration of UARTn
Item Registers Configuration Transmit shift registers 0, 1 (TXS0, TXS1) Receive buffer registers 0, 1 (RXB0, RXB1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) Baud rate generator mode control registers 00, 01 (BRGMC00, BRGMC01) Baud rate generator mode control registers 10, 11 (BRGMC10, BRGMC11)
It can therefore be used to reduce power
Control registers
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Figure 10-44. Block Diagram of UARTn
Internal bus
8
Receive buffer registers 0, 1 (RXB0, RXB1)
8
RXD0, RXD1 TXD0, TXD1
Receive shift registers 0, 1 (RX0, RX1)
8
Transmit shift registers 0, 1 (TXS0, TXS1) Receive control parity check Baud rate generator INTSR0, INTSR1
Transmit control parity addition
INTST0, INTST1 Selector fXX to fXX/29 TMx output
ASCK0, ASCK1
Remark
TMx output is as follows: When UART0: TM2 When UART1: TM3
(1) Transmit shift registers 0, 1 (TXS0, TXS1) TXSn is the register for setting transmit data. Data written to TXSn is transmitted as serial data. When the data length is set to 7 bits, bit 0 to bit 6 of the data written to TXSn is transmitted as serial data. Writing data to TXSn starts the transmit operation. TXSn can be written to by an 8-bit memory manipulation instruction. It cannot be read from. RESET input sets these registers to FFH. Caution Do not write to TXSn during a transmit operation.
(2) Receive shift registers 0, 1 (RX0, RX1) The RXn register converts serial data input via the RXD0 and RXD1 pins into parallel data. When one byte of data is received at RXn, the received data is transferred to receive buffer registers 0, 1(RXB0, RXB1). RX0, RX1 cannot be manipulated directly by a program. (3) Receive buffer registers 0, 1 (RXB0, RXB1) RXBn is used to hold receive data. transferred. When the data length is set to 7 bits, received data is sent to bit 0 to bit 6 of RXBn. In RXBn, the MSB must be set to 0. RXBn can be read by an 8-bit memory manipulation instruction. It cannot be written to. RESET input sets RXBn to FFH. When one byte of data is received, one byte of new receive data is
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(4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn). (5) Reception controller The reception controller controls receive operations based on the values set to asynchronous serial interface mode register n (ASIMn). During a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register n (ASISn) according to the type of error that is detected. 10.5.2 UARTn control registers UARTn uses the following registers for control function (n = 0, 1). * * * * Asynchronous serial interface mode register n (ASIMn) Asynchronous serial interface status register n (ASISn) Baud rate generator control register n (BRGCn) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1)
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(1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) ASIMn is an 8-bit register that controls the serial transfer operations of UARTn. ASIMn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H.
After reset: 00H <7> ASIMn (n = 0, 1) TXEn 0 0 1 1 RXEn 0 1 0 1 Operation mode Operation stop UARTn mode (receive only) UARTn mode (transmit only) UARTn mode (transmit and receive) RXDn/Pxx pin function Port function Serial function Port function Serial function TXDn/Pxx pin function Port function Port function Serial function Serial function TXEn R/W <6> RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 UCLn 2 SLn 1 ISRMn 0 0
PS1n 0 0
PS0n 0 1 No parity
Parity bit specification
Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity
1 1
0 1
UCLn 0 1 7 bits 8 bits
Character length specification
SLn 0 1 1 bit 2 bits
Stop bit length specification for transmit data
ISRMn 0 1
Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs
Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Be sure to set bit 0 to 0.
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(2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. ASISn can be read using an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H.
After reset: 00H 7 ASISn (n = 0, 1) PEn 0 1 No parity error Parity error (Transmit data parity does not match) Parity error flag 0 R 6 0 Address: FFFFF302H, FFFFF312H 5 0 4 0 3 0 <2> PEn <1> FEn <0> OVEn
FEn 0 1 No framing error Framing errorNote 1 (Stop bit not detected)
Framing error flag
OVEn 0 1 No overrun error
Overrun error flag
Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register)
Notes 1. Even if the stop bit length has been set to two bits by setting bit 2 (SLn) of asynchronous serial interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has occurred. Until the contents of RXBn are read, further overrun errors will occur when receiving data.
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(3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
After reset: 00H 7 BRGCn (n = 0, 1) MD Ln7 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln6 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln5 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln4 0 0 0 0 0 0 0 0 0 1 * * * 1 MD Ln3 0 1 1 1 1 1 1 1 1 0 * * * 1 MD Ln2 x 0 0 0 0 1 1 1 1 0 * * * 1 MD Ln1 x 0 0 1 1 0 0 1 1 0 * * * 1 MD Ln0 x 0 1 0 1 0 1 0 1 0 * * * 1 fSCK/255 Selection of input clock k MDLn7 R/W 6 MDLn6 Address: FFFFF304H, FFFFF314H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0
Setting prohibited fSCK/8 fSCK/9 fSCK/10 fSCK/11 fSCK/12 fSCK/13 fSCK/14 fSCK/15 fSCK/16 * * *
- 8 9 10 11 12 13 14 15 16 * * * 255
Cautions 1. The value of BRGCn becomes 00H after reset. Before starting operation, select a setting other than "Setting prohibited". Selecting the "Setting prohibited" setting in stop mode does not cause any problems. 2. If write is performed to BRGCn during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. Therefore, do not write to BRGCn during communication processing. Remark fSCK: Source clock of 8-bit counter
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(4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) These registers set the UARTn source clock. BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
After reset: 00H 7 BRGMCn0 (n = 0, 1) 0 R/W 6 0 Address: FFFFF30EH, FFFFF31EH 5 0 4 0 3 0 2 TPSn2 1 TPSn1 0 TPSn0
After reset: 00H 7 BRGMCn1 (n = 0, 1) 0
R/W 6 0
Address: FFFFF320H, FFFFF322H 5 0 4 0 3 0 2 0 1 0 0 TPSn3
TPSn3 0 0 0 0 0 0 0 0
TPSn2 0 0 0 0 1 1 1 1
TPSn1 0 0 1 1 0 0 1 1
TPSn0 0 1 0 1 0 1 0 1
8-bit counter source clock selection External clock (ASCKn) fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 at n = 0: TM3 output at n = 1: TM2 output fXX/64 fXX/128 fXX/256 fXX/512 Setting prohibited
m - 0 1 2 3 4 5 - 6 7 8 9 - - - -
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Cautions 1. If write is performed to BRGMCn0, n1 during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. Therefore, do not write to BRGMCn0, n1 during communication processing. 2. Be sure to set bits 7 to 3 of the BRGMCn0 to 0. Remarks 1. fSCK: Source clock of 8-bit counter 2. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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10.5.3 Operations UARTn has the following two operation modes. * * Operation stop mode Asynchronous serial interface mode
(1) Operation stop mode In this mode serial transfers are not performed, allowing a reduction in power consumption. When in operation stop mode, pins can be used as normal ports. (a) Register settings Operation stop mode settings are made via bits TxEn and RXEn of asynchronous serial interface mode register n (ASIMn). Figure 10-45. ASIMn Setting (Operation Stop Mode)
After reset: 00H 7 ASIMn (n = 0, 1) TXEn 0 RXEn 0 Operation mode Operation stop RXDn/Pxx pin function Port function TXDn/Pxx pin function Port function TXEn R/W 6 RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 CLn 2 SLn 1 ISRMn 0 0
Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Be sure to set bit 0 to 0.
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(2) Asynchronous serial interface mode This mode enables full-duplex operation, in which one byte of data is transmitted and received after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates. The UARTn baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 Kbps). (a) Register settings The asynchronous serial interface mode settings are made via ASIMn, BRGCn, BRGMCn0, and BRGMCn1 (n = 0, 1). Figure 10-46. ASIMn Setting (Asynchronous Serial Interface Mode)
After reset: 00H 7 ASIMn (n = 0, 1) TXEn 0 1 1 RXEn 1 0 1 Operation mode UARTn mode (receive only) UARTn mode (transmit only) UARTn mode (transmit and receive) RXDn/Pxx pin function Serial function Port function Serial function TXDn/Pxx pin function Port function Serial function Serial function TXEn R/W 6 RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 CLn 2 SLn 1 ISRMn 0 0
PS1n 0 0 1 1
PS0n 0 1 0 1 No parity
Parity bit specification
Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity
CLn 0 1 7 bits 8 bits
Character length specification
SLn 0 1 1 bit 2 bits
Stop bit length specification for transmit data
ISRMn 0 1
Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs
Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Be sure to set bit 0 to 0. 3. Set RXEn to 1 while a high level is being input to the RXDn pin. If RXEn is set to 1 while the RXDn pin is low level, reception is started unexpectedly.
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Figure 10-47. ASISn Setting (Asynchronous Serial Interface Mode)
After reset: 00H 7 ASISn (n = 0, 1) PEn 0 1 No parity error Parity error (Transmit data parity does not match) Parity error flag 0 R 6 0 Address: FFFFF302H, FFFFF312H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn
FEn 0 1 No framing error Framing errorNote 1 (Stop bit not detected)
Framing error flag
OVEn 0 1 No overrun error
Overrun error flag
Overrun errorNote 2 (Next receive operation was completed before data was read from receive buffer register)
Notes 1. Even if the stop bit length has been set to two bits by setting bit 2 (SLn) of asynchronous serial interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has occurred. Until the contents of RXBn are read, further overrun errors will occur when receiving data.
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Figure 10-48. BRGCn Setting (Asynchronous Serial Interface Mode)
After reset: 00H 7 BRGCn (n = 0, 1) MD Ln7 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln6 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln5 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln4 0 0 0 0 0 0 0 0 0 1 * * * 1 MD Ln3 0 1 1 1 1 1 1 1 1 0 * * * 1 MD Ln2 x 0 0 0 0 1 1 1 1 0 * * * 1 MD Ln1 x 0 0 1 1 0 0 1 1 0 * * * 1 MD Ln0 x 0 1 0 1 0 1 0 1 0 * * * 1 fSCK/255 Input clock selection k MDLn7 R/W 6 MDLn6 Address: FFFFF304H, FFFFF314H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0
Setting prohibited fSCK/8 fSCK/9 fSCK/10 fSCK/11 fSCK/12 fSCK/13 fSCK/14 fSCK/15 fSCK/16 * * *
- 8 9 10 11 12 13 14 15 16 * * * 255
Cautions 1. Reset input clears the BRGCn register to 00H. Before starting operation, select a setting other than "Setting prohibited". Selecting "Setting prohibited" setting in stop mode does not cause any problems. 2. If write is performed to BRGCn during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. Therefore, do not write to BRGCn during communication processing. Remark fSCK: Source clock of 8-bit counter
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Figure 10-49. BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode)
After reset: 00H 7 BRGMCn0 (n = 0, 1) 0 R/W 6 0 Address: FFFFF30EH, FFFFF31EH 5 0 4 0 3 0 2 TPSn2 1 TPSn1 0 TPSn0
After reset: 00H 7 BRGMCn1 (n = 0, 1) 0
R/W 6 0
Address: FFFFF320H, FFFFF322H 5 0 4 0 3 0 2 0 1 0 0 TPSn3
TPSn3 0 0 0 0 0 0 0 0
TPSn2 0 0 0 0 1 1 1 1
TPSn1 0 0 1 1 0 0 1 1
TPSn0 0 1 0 1 0 1 0 1
8-bit counter source clock selection External clock (ASCKn) fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 at n = 0: TM3 output at n = 1: TM2 output fXX/64 fXX/128 fXX/256 fXX/512 Setting prohibited
m - 0 1 2 3 4 5 - 6 7 8 9 - - - -
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Cautions 1. If write is performed to BRGMCn0, n1 during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. Therefore, do not write to BRGMCn0 and BRGMCn1 during communication processing. 2. Be sure to set bits 7 to 3 of the BRGMCn0 register to 0. Remarks 1. fXX: Main clock oscillation frequency 2. When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and P27/TO3/TI3 pins in the timer output mode.
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(b) Baud rate The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. * Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock. [Baud rate] = 2 fXX
m+1
xk
[Hz]
fXX: Main clock oscillation frequency m: Value set by TPSn3 to TPSn0 (0 m 9) k: * Value set by MDLn7 to MDLn0 (8 k 255)
Baud rate error tolerance The baud rate error tolerance depends on the number of bits in a frame and the counter division ratio [1/(16+k)]. Table 10-16 shows the relationship between the main clock and the baud rate, and Figure 10-50 shows an example of the baud rate error tolerance. Table 10-16. Relationship Between Main Clock and Baud Rate
Baud Rate (bps) 32 64 128 300 600 1200 2400 4800 9600 19200 38400 76800 150000 300000 312500
fXX = 8 MHz k 244 244 244 208 208 208 208 208 208 208 104 52 27 13 13 m 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 Error (%) 0.06 0.06 0.06 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.24 2.56 -1.54 k -
fXX = 12.58 MHz m - 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Error (%) - -0.02 -0.02 -0.12 -0.12 -0.12 -0.12 -0.12 -0.12 -0.12 -0.12 -0.12 -0.16 -0.16 0.64 k -
fXX = 16 MHz m - 9 8 7 6 5 4 3 2 1 0 0 0 0 0
Note 1
fXX = 20 MHz k - - 152 130 130 130 130 130 130 130 130 130 67 33 8 m - - 9 8 7 6 5 4 3 2 1 0 0 0 2
Note 2
Error (%) - 0.06 0.06 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.63 -1.24 -1.54
Error (%) - - 0.39 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.50 1.01 0.00
192 192 164 164 164 164 164 164 164 164 82 42 21 20
244 244 208 208 208 208 208 208 208 208 104 53 27 26
Notes 1. Only in the V850/SB1 and the H versions of the V850/SB2 2. Only in the V850/SB1 Remark fXX: Main clock oscillation frequency
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Figure 10-50. Error Tolerance (When k = 16), Including Sampling Errors
Ideal sampling point
32T 64T 256T 288T 320T 352T
304T Basic timing (clock cycle T) High-speed clock (clock cycle T') enabling normal reception Low-speed clock (clock cycle T") enabling normal reception START D0 D7 P
15.5T
336T
STOP
START 30.45T START
D0 60.9T D0 33.55T 67.1T
D7
P
STOP
304.5T
15.5T
Sampling error 0.5T
STOP
D7 301.95T
P
335.5T
Remark
T: 8-bit counter's source clock cycle
Baud rate error tolerance (when k = 16) =
15.5 320
x 100 = 4.8438 (%)
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(3) Communication operations (a) Data format As shown in Figure 10-43, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame (n = 0, 1). Figure 10-51. Format of Transmit/Receive Data in Asynchronous Serial Interface
1 data frame Start bit Parity bit Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
* Start bit ............. 1 bit * Character bits ... 7 bits or 8 bits * Parity bit ........... * Stop bit(s) ........ Even parity, odd parity, zero parity, or no parity 1 bit or 2 bits
When 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. Asynchronous serial interface mode register n (ASIMn) and baud rate generator control register n (BRGCn) are used to set the serial transfer rate (n = 0, 1). If a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register n (ASISn).
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(b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the oddnumber bit) can be detected. When zero parity or no parity is set, errors are not detected. (i) Even parity * During transmission The number of bits in transmit data including the parity bit is controlled so that an even number of "1" bits is set. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: The parity bit value is "1" If the transmit data contains an even number of "1" bits: The parity bit value is "0" * During reception The number of "1" bits is counted among the receive data including a parity bit, and a parity error occurs when the result is an odd number. (ii) Odd parity * During transmission The number of bits in transmit data including a parity bit is controlled so that an odd number of "1" bits is set. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: The parity bit value is "0" If the transmit data contains an even number of "1" bits: The parity bit value is "1" * During reception The number of "1" bits is counted among the receive data including a parity bit, and a parity error occurs when the result is an even number. (iii) Zero parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, the parity bit is not checked. Therefore, no parity errors will occur regardless of whether the parity bit is a "0" or a "1". (iv) No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will occur.
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(c) Transmission The transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmit completion interrupt (INTSTn) is issued. The timing of the transmit completion interrupt is shown below. Figure 10-52. Timing of Asynchronous Serial Interface Transmit Completion Interrupt
(a) Stop bit length: 1
TxDn (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSTn
(b) Stop bit length: 2
TxDn (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSTn
Caution Do not write to asynchronous serial interface mode register n (ASIMn) during a transmit operation. Writing to ASIMn during a transmit operation may disable further transmit operations (in such cases, input RESET to restore normal operation). Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (INTSTn) or the interrupt request flag (STIFn) that is set by INTSTn. Remark n = 0, 1
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(d) Reception The receive operation is enabled when "1" is set to bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn), and the input via the RXDn pin is sampled. The serial clock specified by BRGCn is used when sampling the RXDn pin. When the RXDn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the RXDn pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 8-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. Once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register n (RXBn) and a receive completion interrupt (INTSRn) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXBn. When an error occurs, INSTRn is generated if bit 1 (ISRMn) of ASIMn is cleared (0). On the other hand, INTSRn is not generated if the ISRMn bit is set (1). If the RXEn bit is reset to 0 during a receive operation, the receive operation is stopped immediately. At this time, the contents of RXBn and ASISn do not change, nor does INTSRn or INTSERn occur. The timing of the asynchronous serial interface receive completion interrupt is shown below. Figure 10-53. Timing of Asynchronous Serial Interface Receive Completion Interrupt
RXDn (input)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSRn
Caution Be sure to read the contents of receive buffer register n (RXBn) even when a receive error has occurred. If the contents of RXBn are not read, an overrun error will occur during the next data receive operation and the receive error status will remain. Remark n = 0, 1
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(e) Receive error Three types of errors can occur during a receive operation: a parity error, framing error, and overrun error. When, as the result of data reception, an error flag is set in asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated. The receive error interrupt request is generated prior to the receive completion interrupt request (INTSRn). By reading the contents of ASISn during receive error interrupt servicing (INTSERn), it is possible to ascertain which error has occurred during reception. The contents of ASISn are reset (0) by reading receive buffer register n (RXBn) or receiving subsequent data (if there is an error in the subsequent data, the error flag is set). Table 10-17. Receive Error Causes
Receive Error Parity error Framing error Overrun error Cause Parity specification at transmission and receive data parity do not match. Stop bit is not detected. Reception of subsequent data was completed before data was read from the receive buffer register. ASISn Value 04H 02H 01H
Figure 10-54. Receive Error Timing
RxDn (Input)
START
D0
D1
D2
D6
D7
Parity
STOP
INTSRn
Note
INTSERn
INTSERn
(When parity error occurs)
Note Even if a receive error occurs when the ISRMn bit of ASIMn is set (1), INTSRn is not generated. Cautions 1. The contents of asynchronous serial interface status register n (ASISn) are reset (0) by reading receive buffer register n (RXBn) or receiving subsequent data. To check the contents of error, always read ASISn before reading RXBn. 2. Be sure to read receive buffer register n (RXBn) even when a receive error occurs. If RXBn is not read out, an overrun error will occur during subsequent data reception and as a result receive errors will continue to occur. Remark n = 0, 1
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10.5.4 Standby function (1) Operation in HALT mode Serial transfer operations are performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are held. The TXDn pin output holds the data immediately before the clock was stopped (in STOP mode) during transmission. When the clock is stopped during reception, the receive data until the clock stopped is stored and subsequent receive operations are stopped. Reception resumes upon clock restart. (b) When external clock is selected as serial clock Serial transfer operations are performed normally.
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10.6 3-Wire Variable-Length Serial I/O (CSI4)
CSI4 has the following two operation modes. (1) Operation stop mode This mode is used when serial transfers are not performed. (2) 3-wire variable-length serial I/O mode (MSB/LSB first switchable) This mode transfers variable data of 8 to 16 bits via three lines: serial clock (SCK4), serial output (SO4), and serial input (SI4). Since the data can be transmitted and received simultaneously in the 3-wire variable-length serial I/O mode, the processing time of data transfer is shortened. MSB and LSB can be switched for the first bit of data to be transferred in serial. The 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. 10.6.1 Configuration CSI4 includes the following hardware. Table 10-18. Configuration of CSI4
Item Register Control registers Configuration Variable-length serial I/O shift register 4 (SIO4) Variable-length serial control register 4 (CSIM4) Variable-length serial setting register 4 (CSIB4) Baud rate generator source clock selection register 4 (BRGCN4) Baud rate generator output clock selection register 4 (BRGCK4)
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Figure 10-55. Block Diagram of CSI4
Internal bus
Direction controller
SI4
Variable-length I/O shift register 4 (8-/16-bit)
SO4
Serial clock counter (8-/16-bit switchable)
Interrupt generator
INTCSI4
SCK4
Serial clock controller
Selector
Baud rate generator
(1) Variable-length serial I/O shift register 4 (SIO4) SIO4 is a 16-bit variable register that performs parallel-serial conversion and transmit/receive (shift operations) synchronized with the serial clock. SIO4 is set by a 16-bit memory manipulation instruction. The serial operation starts when data is written to or read from SIO4, while the bit 7 (CSIE4) of variable-length serial control register 4 (CSIM4) is 1. When transmitting, data written to SIO4 is output via the serial output (SO4). When receiving, data is read from the serial input (SI4) and written to SIO4. RESET input clears SIO4 to 0000H. Caution Do not execute SIO4 access except for the access that becomes the transfer start trigger during transfer operations (read is disabled when MODE4 = 0 and write is disabled when MODE4 = 1).
After reset: 0000H R/W Address: FFFFF2E0H
15 SIO4
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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When the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether MSB or LSB is set for the first transfer bit. Any data can be set to the unused higher bits; however, in this case the received data after a serial transfer operation becomes 0. Figure 10-56. When Transfer Bit Length Other Than 16 Bits Is Set (a) When transfer bit length is 10 bits and MSB first
SO4
15 10 9 0
SI4
Fixed to 0
(b) When transfer bit length is 12 bits and LSB first
SI4
15 12 11 0
SO4
Fixed to 0
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10.6.2 CSI4 control registers CSI4 uses the following registers for control functions. * * * * Variable-length serial control register 4 (CSIM4) Variable-length serial setting register 4 (CSIB4) Baud rate generator source clock selection register 4 (BRGCN4) Baud rate generator output clock selection register 4 (BRGCK4)
(1) Variable-length serial control register 4 (CSIM4) This register is used to enable or disable serial interface channel 4's serial clock, operation modes, and specific operations. CSIM4 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CSIM4 to 00H.
After reset: 00H <7> CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4
CSIE4 Shift register operation 0 1 Operation disabled Operation enabled
SIO4 operation enable/disable specification Serial counter Clear Count operation enabled Port Port functionNote 1 Serial function + port functionNote 2
MODE4 Operation mode 0 1 Transmit/receive mode Receive-only mode
Transfer operation mode flag Transfer start trigger SIO4 write SIO4 read SO4 output Normal output Port function
SCL4 0 1 External clock input (SCK4) BRG (Baud rate generator)
Clock selection
Notes 1. 2.
When CSIE4 = 0 (SIO4 operation disabled status), the port function is available for the SI4, SO4, and SCK4 pins. When CSIE4 = 1 (SIO4 operation enable status), the port function is available only for the SI4 pin when using the transmit function only and to SO4 pin when using the receive function.
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(2) Variable-length serial setting register 4 (CSIB4) CSIB4 is used to set the operation format of serial interface channel 4. The bit length of a variable register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. CSIB4 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CSIB4 to 00H.
After reset: 00H 7 CSIB4 0 R/W <6> CMODE Address: FFFFF2E4H <5> DMODE <4> DIR 3 BSEL3 2 BSEL2 1 BSEL1 0 BSEL0
CMODE 0 0 1 1
DMODE 0 1 0 1
SCK4 active level Low level Low level High level High level
SI4 interrupt timing Rising edge of SCK4 Falling edge of SCK4 Falling edge of SCK4 Rising edge of SCK4
SO4 output timing Falling edge of SCK4 Rising edge of SCK4 Rising edge of SCK4 Falling edge of SCK4
DIR 0 1 LSB first MSB first
Serial transfer direction
BSEL3 0 1 1 1 1 1 1 1 1
BSEL2 0 0 0 0 0 1 1 1 1
BSEL1 0 0 0 1 1 0 0 1 1
BSEL0 0 0 1 0 1 0 1 0 1 16 bits 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits
Bit length of serial register
Other than above
Setting prohibited
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(3) Baud rate generator source clock selection register 4 (BRGCN4) BRGCN4 can be set by an 8-bit memory manipulation instruction. RESET input clears BRGCN4 to 00H.
After reset: 00H 7 BRGCN4 0 R/W 6 0 Address: FFFFF2E6H 5 0 4 0 3 0 2 BRGN2 1 BRGN1 0 BRGN0
BRGN2 0 0 0 0 1 1 1 1
BRGN1 0 0 1 1 0 0 1 1
BRGN0 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128
Source clock (fSCK)
n 0 1 2 3 4 5 6 7
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(4) Baud rate generator output clock selection register 4 (BRGCK4) BRGCK4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCK4 to 7FH.
After reset: 7FH 7 BRGCK4 0 R/W 6 BRGK6 Address: FFFFF2E8H 5 BRGK5 4 BRGK4 3 BRGK3 2 BRGK2 1 BRGK1 0 BRGK0
BRGK6 0 0 0 0
* * *
BRGK5 0 0 0 1
* * *
BRGK4 0 0 0 0
* * *
BRGK3 0 0 0 3
* * *
BRGK2 0 0 0 0
* * *
BRGK1 0 0 1 1
* * *
BRGK0 0 1 0 1
* * *
Baud rate output clock Setting prohibited fSCK/2 fSCK/4 fSCK/6
* * *
k 0 1 2 3
* * *
1 1
1 1
1 1
1 1
1 1
1 1
0 1
fSCK/252 fSCK/254
126 127
The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. * Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock. [Baud rate] = fxx 2 xkx2
n
[Hz]
fXX: Main clock oscillation frequency n: k: Caution Value set by BRGN2 to BRGN0 (0 n 7) Value set by BRGK7 to BRGK0 (1 k 127)
Do not use the baud rate transmit/receive clock of CSI4 with the transfer rate higher than the CPU operation clock. If used with the transfer rate higher than the CPU operation clock, transfer cannot be performed correctly.
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10.6.3 Operations CSI4 has the following two operation modes. * Operation stop mode * 3-wire variable-length serial I/O mode (1) Operation stop mode In this mode serial transfers are not performed and therefore power consumption can be reduced. When in operation stop mode, SI4, SO4, and SCK4 can be used as normal I/O ports. (a) Register settings Operation stop mode is set via CSIE4 bit of variable-length serial control register 4 (CSIM4). While CSIE4 = 0 (SIO4 operation stop state), the pins connected to SI4, SO4, or SCK4 function as port pins. Figure 10-57. CSIM4 Setting (Operation Stop Mode)
After reset: 00H 7 CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4
CSIE4 Shift register operation 0 Operation disabled
SIO4 operation enable/disable specification Serial counter Clear Port function Port
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(2) 3-wire variable-length serial I/O mode The 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK4), serial output line (SO4), and serial input line (SI4). (a) Register settings The 3-wire variable-length serial I/O mode is set via variable-length serial control register 4 (CSIM4). Figure 10-58. CSIM4 Setting (3-Wire Variable-Length Serial I/O Mode)
After reset: 00H 7 CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4
CSIE4 Shift register operation 1 Operation enabled
SIO4 operation enable/disable specification Serial counter Count operation enabled Port Serial function + port function
MODE4 Operation mode 0 1 Transmit/receive mode Receive-only mode
Transfer operation mode flag Transfer start trigger Write to SIO4 Read from SIO4 SO4 output Normal output Port function
SCL4 0 1 External clock input (SCK4) BRG (Baud rate generator)
Clock selection
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The bit length of a variable-length register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of CSIB4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. Figure 10-59. CSIB4 Setting (3-Wire Variable-Length Serial I/O Mode)
After reset: 00H 7 CSIB4 0 R/W <6> CMODE Address: FFFFF2E4H <5> DMODE <4> DIR 3 BSEL3 2 BSEL2 1 BSEL1 0 BSEL0
CMODE 0 0 1 1
DMODE 0 1 0 1
SCK4 active level Low level Low level High level High level
SI4 interrupt timing Rising edge of SCK4 Falling edge of SCK4 Falling edge of SCK4 Rising edge of SCK4
SO4 output timing Falling edge of SCK4 Rising edge of SCK4 Rising edge of SCK4 Falling edge of SCK4
DIR 0 1 LSB first MSB first
Serial transfer direction
BSEL3 0 1 1 1 1 1 1 1 1
BSEL2 0 0 0 0 0 1 1 1 1
BSEL1 0 0 0 1 1 0 0 1 1
BSEL0 0 0 1 0 1 0 1 0 1 16 bits 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits
Bit length of serial register
Other than above
Setting prohibited
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(b) Communication Operations In the 3-wire variable-length serial I/O mode, data is transmitted and received in 8 to 16-bit units, and is specified by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4 (CSIB4). Each bit of data is transmitted or received in synchronization with the serial clock. After transfer of all bits is completed, SIC4 stops operation automatically and the interrupt request flag (INTCSI4) is set. Bits 6 and 5 (CMODE and DMODE) of variable-length serial setting register 4 (CSIB4) can change the attribute of the serial clock (SCK4) and the phases of serial data (SI4 and SO4). Figure 10-60. Timing of 3-Wire Variable-Length Serial I/O Mode
SCK4 (CMODE = 0) SCK4 (CMODE = 1) SIO4 (write) SO4 (DMODE = 0) SO4 (DMODE = 1) INTCSI4
Remark
An arrow shows the SI4 data fetch timing.
When CMODE = 0, the serial clock (SCK4) stops at the high level during the operation stop, and outputs the low level during a data transfer operation. When CMODE = 1, on the other hand, SCK4 stops at the low level during the operation stop and outputs the high level during a data transfer operation. The phases of the SO4 output timing and the S14 fetch timing can be shifted half a clock by setting DMODE. However, the interrupt signal (INTCSI4) is generated at the final edge of the serial clock (SCK4), regardless the setting of CSIB4.
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(c) Transfer start A serial transfer becomes possible when the following two conditions have been satisfied. * The SIO4 operation control bit (CSIE4) = 1 * After a serial transfer, the internal serial clock is stopped. Serial transfer starts when the following operation is performed after the above two conditions have been satisfied. * Transmit/transmit and receive mode (MODE4 = 0) Transfer starts when writing to SIO4. * Receive-only mode Transfer starts when reading from SIO4. Caution After data has been written to SIO4, transfer will not start even if the CSIE4 bit value is set to 1. Completion of the final-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (INTCSI4).
Figure 10-61. Timing of 3-Wire Variable-Length Serial I/O Mode (When CSIB4 = 08H)
SCK4 (CMODE = 0) SO4 (DMODE = 0) SI4 INTCSI4 Transfer end
1
LSB
2
3
4
5
6
7
8 MSB MSB
LSB
Remark
CSIB4 = 08H (CMODE = 0, DMODE = 0, DIR = 0, BSEL3 to BSEL0 = 1000)
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11.1 Function
The A/D converter converts analog input signals into digital values with a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The V850/SB1 and V850/SB2 support the low power consumption mode by low-speed conversion. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified). (2) Software start Conversion is started by setting A/D converter mode register 1 (ADM1). One analog input channel is selected from ANI0 to ANI11, and A/D conversion is performed. If A/D conversion has been started by means of a hardware start, conversion stops once it has been completed, and an interrupt request (INTAD) is generated. If conversion has been started by means of a software start, conversion is performed repeatedly. Each time conversion is completed, INTAD is generated.
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The block diagram is shown below. Figure 11-1. Block Diagram of A/D Converter
AVDD
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11
Sample & hold circuit Voltage comparator
Tap selector Selector
AVREF
AVSS Successive approximation register (SAR)
AVSS
ADTRG
Edge detector
Controller
INTAD
4 Trigger enable
ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0
A/D conversion result register (ADCR)
EGA1 EGA0 ADPS
IEAD A/D converter mode register 2 (ADM2)
Analog input channel specification register (ADS)
A/D converter mode register 1 (ADM1) Internal bus
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11.2 Configuration
The A/D converter includes the following hardware. Table 11-1. Configuration of A/D Converter
Item Analog input Registers Configuration 12 channels (ANI0 to ANI11) Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read A/D converter mode register 1 (ADM1) A/D converter mode register 2 (ADM2) Analog input channel specification register (ADS)
Control registers
(1) Successive approximation register (SAR) This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (MSB). When the comparison result has been stored down to the least significant bit (LSB) (i.e., when the A/D conversion has been completed), the contents of the SAR are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Each time A/D conversion is completed, the result of the conversion is loaded to this register from the successive approximation register. The higher 10 bits of this register hold the result of the A/D conversion (the lower 6 bits are fixed to 0). This register is read using a 16-bit memory manipulation instruction. RESET input sets ADCR to 0000H. When using only the higher 8 bits of the result of the A/D conversion, ADCRH is read using an 8-bit memory manipulation instruction. RESET input sets ADCRH to 00H. Caution A write operation to A/D converter mode register 1 (ADM1) and the analog input channel specification register (ADS) may cause the ADCR contents to be undefined. Therefore, read the A/D conversion result during A/D conversion (ADCS = 1). Correct conversion results may not be read if the timing is other than the above. (3) Sample & hold circuit The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) Series resistor string The series resistor string is connected between AVREF and AVSS and generates a voltage for comparison with the analog input signal.
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(6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input the analog signals to be converted into digital signals. Pins other than ones selected as the analog input by the analog input channel specification register (ADS) can be used as input ports. Caution Make sure that the voltages input to ANI0 to ANI11 do not exceed the rated values. If a voltage higher than or equal to AVREF or lower than or equal to AVSS (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. (7) AVREF pin This pin inputs a reference voltage to the A/D converter. The signals input to the ANI0 to ANI11 pins are converted into digital signals based on the voltage applied across AVREF and AVSS. (8) AVSS pin This is the ground pin of the A/D converter. Always keep the potential at this pin the same as that at the VSS pin even when the A/D converter is not in use. (9) AVDD pin This is the analog power supply pin of the A/D converter. Always keep the potential at this pin the same as that at the VDD pin even when the A/D converter is not in use.
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11.3 Control Registers
The A/D converter is controlled by the following registers.
* * *
A/D converter mode register 1 (ADM1) Analog input channel specification register (ADS) A/D converter mode register 2 (ADM2)
(1) A/D converter mode register 1 (ADM1) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. ADM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADM1 to 00H. (1/2)
After reset: 00H <7> ADM1 ADCS R/W <6> TRG Address: FFFFF3C0H 5 FR2 4 FR1 3 FR0 2 EGA1 1 EGA0 <0> ADPS
ADCS 0 1 Conversion stopped Conversion enabled
A/D conversion control
TRG 0 1 Software start Hardware start
Software start or hardware start selection
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(2/2)
ADPS FR2 FR1 FR0 Conversion time + stabilization timeNote 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 168/fXX 120/fXX 84/fXX 60/fXX 48/fXX 36/fXX Setting prohibited 12/fXX 168/fXX + 64/fXX 120/fXX + 60/fXX 84/fXX + 42/fXX 60/fXX + 30/fXX 48/fXX + 24/fXX 36/fXX + 18/fXX Setting prohibited 12/fXX + 6/fXX 8.4 s 6.0 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 8.4 + 4.2 s 6.0 + 3.0 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited
Note 1
Selection of conversion time fXX 20 MHzNote 3 12.58 MHz Setting prohibited 9.5 s 6.7 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 9.5 + 4.8 s 6.7 + 3.3 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited
EGA1 0 0 1 1
EGA0 0 1 0 1
Valid edge specification for external trigger signal No edge detection Detection at falling edge Detection at rising edge Detection at both rising and falling edges
ADPS 0 1 Comparator on Comparator off
Comparator control when A/D conversion is stopped (ADCS = 0)
Notes 1. Conversion time (actual A/D conversion time). Always set the time to 5 s Conversion time 10 s. 2. Stabilization time (setup time of A/D converter) Each A/D conversion requires "conversion time + stabilization time". There is no stabilization time when ADPS = 0. 3. Only in the V850/SB1. Cautions 1. The A/D converter cannot be used when the operation frequency is 2.4 to 3.6 MHz. 2. Cut the current consumption by setting ADPS to 1 when ADCS = 0.
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(2) Analog input channel specification register (ADS) ADS specifies the port for inputting the analog voltage to be converted into a digital signal. ADS is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS to 00H.
After reset: 00H 7 ADS 0 R/W 6 0 Address: FFFFF3C2H 5 0 4 0 3 ADS3 2 ADS2 1 ADS1 0 ADS0
ADS3 0 0 0 0 0 0 0 0 1 1 1 1
ADS2 0 0 0 0 1 1 1 1 0 0 0 0
ADS1 0 0 1 1 0 0 1 1 0 0 1 1
ADS0 0 1 0 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11
Analog Input Channel Specification
Other than above
Setting prohibited
Caution Be sure to set bits 7 to 4 to 0. (3) A/D converter mode register 2 (ADM2) ADM2 specifies connection/disconnection of AVDD and AVREF. ADM2 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADM2 to 00H.
After reset: 00H 7 ADM2 0 R/W 6 0 Address: FFFFF3C8H 5 0 4 0 3 0 2 0 1 0 <0> IEAD
IEAD 0 1 Cut between AVDD and AVREF Connect between AVDD and AVREF
A/D current cut control
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11.4 Operation
11.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3> After sampling for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until it has been converted into a digital signal. <4> Set bit 9 of the successive approximation register (SAR). The tap selector sets the voltage tap of the series resistor string to (1/2) AVREF. <5> The voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage comparator. If the analog input voltage is greater than (1/2) AVREF, the MSB of the SAR remains set. If the analog input voltage is less than (1/2) AVREF, the MSB is reset. <6> Next, bit 8 of the SAR is automatically set, and the analog input voltage is compared again. Depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows:
* *
Bit 9 = 1: (3/4) AVREF Bit 9 = 0: (1/4) AVREF
The analog input voltage is compared with one of these voltage taps, and bit 8 of the SAR is manipulated as follows depending on the result of the comparison.
* *
Analog input voltage voltage tap: Bit 8 = 1 Analog input voltage voltage tap: Bit 8 = 0
<7> The above steps are repeated until the bit 0 of the SAR has been manipulated. <8> When comparison of all 10 bits of the SAR has been completed, the valid digital value remains in the SAR, and the value of the SAR is transferred and latched to the A/D conversion result register (ADCR). At the same time, an A/D conversion end interrupt request (INTAD) can be generated. Caution The first conversion value immediately after setting ADCS = 0 1 may not satisfy the ratings.
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Figure 11-2. Basic Operation of A/D Converter
Conversion time Sampling time Operation of A/D converter
Sampling
A/D conversion
SAR
Undefined
Conversion result
ADCR
Conversion result
INTAD
A/D conversion is successively executed until bit 7 (ADCS) of A/D converter mode register 1 (ADM1) is reset to 0 by software. If ADM1 and the analog input channel specification register (ADS) are written during A/D conversion, the conversion is initialized. If ADCS is set to 1 at this time, conversion is started from the beginning. RESET input sets the A/D conversion result register (ADCR) to 0000H.
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11.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows. ADCR = INT( Or, (ADCR - 0.5) x AVREF 1024 VIN < (ADCR + 0.5) x AVREF 1024 VIN AVREF x 1024 + 0.5)
INT ( ): Function that returns integer of value in ( ) VIN: Analog input voltage AVREF: AVREF pin voltage ADCR: Value of the A/D conversion result register (ADCR) The relationship between the analog input voltage and A/D conversion result is shown below. Figure 11-3. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
A/D conversion result (ADCR)
1021
3
2
1
0 1 1 3 2 5 3 2048 1024 20481024 2048 1024 2043 1022 20451023 2047 1 2048 1024 20481024 2048
Input voltage/AVREF
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11.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. The A/D conversion can be started in the following two ways.
*
Hardware start: Software start:
Started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified) Started by setting A/D converter mode register 1 (ADM1)
*
The result of the A/D conversion is stored in the A/D conversion result register (ADCR) and an interrupt request signal (INTAD) is generated at the same time. (1) A/D conversion by hardware start A/D conversion is on standby if bit 6 (TRG) and bit 7 (ADCS) of A/D converter mode register 1 (ADM1) are set to 1. When an external trigger signal is input, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal. When the A/D conversion has been completed, the result of the conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once A/D conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. If data with ADCS set to 1 is written to ADM during A/D conversion, the conversion under execution is stopped, and the A/D converter stands by until a new external trigger signal is input. If the external trigger signal is input, A/D conversion is executed again from the beginning. If data with ADCS set to 0 is written to ADM1 during A/D conversion, the conversion is immediately stopped. Figure 11-4. A/D Conversion by Hardware Start (with Falling Edge Specified)
External trigger input signal Rewriting ADS ADCS = 1, TRG = 1 Standby status Standby status Rewriting ADS ADCS = 1, TRG = 1 Standby status
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
ANIm
ADCR
ANIn
ANIn
ANIn
ANIm
ANIm
INTAD
Remarks 1. 2.
n = 0, 1, ..., 11 m = 0, 1, ..., 11
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(2) A/D conversion by software start If bit 6 (TRG) of A/D converter mode register 1 (ADM1) is set to 0 and bit 7 (ADCS) is set to 1, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal. When A/D conversion has been completed, the result of the conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once A/D conversion has been started and completed, the next conversion is started immediately. A/D conversion is repeated until new data is written to ADS. If ADS is rewritten during A/D conversion, the conversion under execution is stopped, and conversion of the newly selected analog input channel is started. If data with ADCS set to 0 is written to ADM1 during A/D conversion, the conversion is immediately stopped. Figure 11-5. A/D Conversion by Software Start
Rewriting ADS ADCS = 1, TRG = 0 Rewriting ADS ADCS = 1, TRG = 0
ADCS = 0
A/D conversion
ANIn
ANIn
ANIn Conversion stopped. Conversion result does not remain.
ANIm
ANIm

Stopped
ADCR
ANIn
ANIn
ANIm
INTAD
Remarks 1. 2.
n = 0, 1, ..., 11 m = 0, 1, ..., 11
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11.5 Low Power Consumption Mode
The V850/SB1 and V850/SB2 feature a function that can cut or connect the current between AVDD and AVREF. Switching can be performed by setting A/D converter mode register 2 (ADM2). When AVDD = AVREF, and when the system does not require high precision, current consumption can be reduced by connecting AVDD and AVREF in the normal mode or disconnecting them in standby mode after opening the AVREF pin. The conversion precision of the reference voltage is reduced since the reference voltage is supplied from AVDD via a switch. When the A/D converter is not used, cut the tap selector that reduces the current when A/D conversion is stopped (ADCS = 0), and the supply voltage (AVDD), in order to reduce the current consumption. * Set the ADPS bit of A/D converter mode register 1 (ADM1) to 1. * Clear the IEAD bit of A/D converter mode register 2 (ADM2) to 0. When the ADPS bit is cleared to 0 (comparator on) again, a stabilization time (5 s max.) is required until the A/D converter is started. Therefore, use software to ensure that a wait time of 5 s elapses.
11.6 Cautions
(1) Current consumption in standby mode The A/D converter stops operation in the IDLE/STOP mode (operable in the HALT mode). At this time, the current consumption of the A/D converter can be reduced by stopping the conversion (by resetting the bit 7 (ADCS) of A/D converter mode register 1 (ADM1) to 0). To reduce the current consumption in the IDLE/STOP mode, set the AVREF potential in the user circuit to the same value (0 V) as the AVSS potential. (2) Input range of ANI0 to ANI11 Keep the input voltage of the ANI0 to ANI11 pins to within the rated range. If a voltage greater than or equal to AVREF or lower than or equal to AVSS (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the channel becomes undefined. Moreover, the values of the other channels may also be affected. (3) Conflict <1> Conflict between writing A/D conversion result register (ADCR) and reading ADCR at end of conversion Reading ADCR takes precedence. After ADCR has been read, a new conversion result is written to ADCR. <2> Conflict between writing ADCR and external trigger signal input at end of conversion The external trigger signal is not input during A/D conversion. Therefore, the external trigger signal is not acknowledged during writing of ADCR. <3> Conflict between writing of ADCR and writing A/D converter mode register 1 (ADM1) or analog input channel specification register (ADS) When ADM1 or ADS write is performed immediately after ADCR write following the end of A/D conversion, the conversion result cannot be guaranteed since an undefined value is stored in the ADCR register.
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(4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the AVREF and ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor as shown in Figure 11-6 is recommended. Figure 11-6. Handling of Analog Input Pin
Clamp with diode with a low VF (0.3 V MAX.) if noise higher than AVREF or lower than AVSS may be generated.
Reference voltage input
AVREF
C = 100 to 1000 pF VDD AVDD AVSS VSS
(5) ANI0 to ANI11 The analog input (ANI0 to ANI11) pins function alternately as port pins. To execute A/D conversion with any of ANI0 to ANI11 selected, do not execute an instruction that inputs data to the port during conversion; otherwise, the resolution may drop. If a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected A/D conversion result may not be obtained because of the influence of coupling noise. Therefore, do not apply a pulse to the adjacent pins. (6) Input impedance of AVREF pin A series resistor string is connected between the AVREF and AVSS pins. If the output impedance of the reference voltage source is too high, the series resistor string between the AVREF and AVSS pins is connected in series, increasing the error of the reference voltage.
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(7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten. If ADIF is read immediately after ADS has been rewritten, it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet. When stopping A/D conversion and then resuming, clear ADIF before resuming conversion. Figure 11-7. A/D Conversion End Interrupt Generation Timing
Rewriting ADS (ANIn conversion starts) Rewriting ADS (ANIm conversion starts) ADIF is set but conversion of ANIm is not completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remarks 1. 2.
n = 0, 1, ..., 11 m = 0, 1, ..., 11
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(8) AVDD pin The AVDD pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a backup power supply is used, therefore, be sure to apply the same voltage as the VDD pin to the AVDD pin as shown in Figure 11-8. Figure 11-8. Handling of AVDD Pin
AVREF VDD AVDD Main power supply Backup capacitor VSS AVSS
(9) Reading out A/D converter result register (ADCR) A write operation to A/D converter mode register 1 (ADM1) and the analog input channel specification register (ADS) may cause the ADCR contents to be undefined. Therefore, read the A/D conversion result during A/D conversion (ADCS = 1). Incorrect conversion results may be read out at a timing other than the above.
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11.7 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREF - 0)/100 = AVREF/100 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/2 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 11-9. Overall Error
1......1
10
Ideal line
Digital output
Overall error
0......0 0 Analog input AVREF
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(3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 11-10. Quantization Error
1......1
Digital output
1/2LSB
Quantization error 1/2LSB
0......0 0 Analog input AVREF
(4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. Figure 11-11. Zero-Scale Error
111
Digital output (Lower 3 bits)
Ideal line 100 Zero-scale error 011
010 001 000 -1 0 1 2 3 AVREF Analog input (LSB)
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(5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1......110 to 1......111. Figure 11-12. Full-Scale Error
Full-scale error
Digital output (Lower 3 bits)
111 100 011 010
000 0 AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB)
(6) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 11-13. Differential Linearity Error
1......1 Ideal 1LSB width
Digital output
Differential linearity error 0......0 0 Analog input AVREF
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(7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 11-14. Integral Linearity Error
1......1 Ideal line
Digital output
0......0 0
Integral linearity error AVREF Analog input
(8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 11-15. Sampling Time
Sampling time
Conversion time
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12.1 Functions
The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as the serial interface, timer, or A/D converter). This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units. maximum number of transfers is 256 (when transferring data in 8-bit units). After a DMA transfer has occurred a specified number of times, DMA transfer completion interrupt (INTDMA0 to INTDMA5) requests are output individually from the various channels. The priority levels of the DMA channels are fixed as follows for simultaneous generation of multiple DMA transfer requests. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 The
12.2 Transfer Completion Interrupt Request
After a DMA transfer has occurred a specified number of times and the TCn bit in the corresponding DMA channel control register (DCHCn) has been set to 1, a DMA transfer completion interrupt request (INTDMA0 to INTDMA5) is sent to the interrupt controller for each channel.
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12.3 Configuration
Figure 12-1. Block Diagram of DMA
DMA transfer trigger (INT signal)
DMA transfer request control
DMA peripheral I/O address register n (DIOAn) DMA byte count register n (DBCn) DMA internal RAM address register n (DRAn) INTDMAn
DMA channel control register n (DCHCn) DMA transfer acknowledge signal Channel controller CPU
Interface control
Internal RAM
Internal bus
Peripheral I/O register
Remark n = 0 to 5 (1) DMA transfer request control block The DMA transfer request control block generates a DMA transfer request signal for the CPU when the required DMA transfer trigger (INT signal) is input. When the DMA transfer request signal is acknowledged, the CPU generates a DMA transfer acknowledge signal for the channel control block and interface control block after the current CPU processing has finished. For the INT signal, refer to the TTYPn1 and TTYPn0 bits in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5). (2) Channel control block The channel control block distinguishes the DMA transfer channel (DMA0 to DMA5) to be transferred and controls the internal RAM, peripheral I/O addresses, and access cycles (internal RAM: 1 clock, peripheral I/O register: 3 clocks) set by the peripheral I/O registers of the channel to be transferred, the transfer direction, and the transfer count. In addition, it also controls the priority order when two or more DMAn transfer triggers (INT signals) are generated simultaneously.
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12.4 Control Registers
(1) DMA peripheral I/O address registers 0 to 5 (DIOA0 to DIOA5) These registers are used to set the peripheral I/O register address for DMA channel n. These registers are can be read/written in 16-bit units.
After reset: Undefined R/W Address: DIOA0 DIOA1 DIOA2 15 DIOAn 0 14 0 13 0 12 0 11 0 10 0 9 IOAn9 to IOAn1 FFFFF180H FFFFF190H FFFFF1A0H DIOA3 DIOA4 DIOA5 FFFFF1B0H FFFFF1C0H FFFFF100H 1 0 0
(n = 0 to 5) Caution The following peripheral I/O registers must not be set. P4, P5, P6, P9, P11, PM4, PM5, PM6, PM9, PM11, MM, DWC, BCC, SYC, PSC, PCC, SYS, PRCMD, DIOAn, DRAn, DBCn, DCHCn, CORCN, CORRQ, CORADn, Interrupt control register (xxICn), ISPR
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(2) DMA internal RAM address registers 0 to 5 (DRA0 to DRA5) These registers set DMA channel n internal RAM addresses (n = 0 to 5). Since each product has a different internal RAM capacity, the internal RAM areas that are usable for DMA differ depending on the product. The internal RAM areas that can be set in the DRAn registers for each product are shown below. Table 12-1. Internal RAM Area Usable in DMA
Product Internal RAM Capacity 8 KB RAM Size Usable in DMA 8 KB RAM Area Usable in DMA
V850/SB1 V850/SB2 V850/SB1 V850/SB2 V850/SB1
PD703031B, 703031BY PD703034B, 703034BY PD703031A, 703031AY, PD703034A, 703034AY PD703033A, 703033AY, 703033B, 703033BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY PD703035A, 703035AY, 703035B, 703035BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY PD703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY
xxFFD000H to xxFFEFFFH
12 KB
12 KB
xxFFC000H to xxFFEFFFH
16 KB
16 KB
xxFFB000H to xxFFEFFFH
V850/SB2
V850/SB1
24 KB
16 KB
xxFF9000H to xxFFBFFFH, xxFFE000H to xxFFEFFFH
V850/SB2
An address is incremented after each transfer is completed, when the DADn bit of the DCHDn register is 0. The incrementation value is "1" during 8-bit transfers and "2" during 16-bit transfers (n = 0 to 5). These registers are can be read/written in 16-bit units.
After reset: Undefined R/W Address: DRA0 DRA1 DRA2 15 DRAn 0 14 0 13 RAn13 to RAn0 FFFFF182H FFFFF192H FFFFF1A2H DRA3 DRA4 DRA5 FFFFF1B2H FFFFF1C2H FFFFF1D2H 0
(n = 0 to 5)
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The correspondence between DRAn setting value and internal RAM area is shown below. (a) V850/SB1 (PD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) Set the DRAn register to a value in the range of 0000H to 1FFFH (n = 0 to 5). Setting is prohibited for values between 2000H and 3FFFH. Figure 12-2. Correspondence Between DRAn Setting Value and Internal RAM (8 KB)
(DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH On-chip peripheral I/O area (1FFFH)
Internal RAM area
8 KB (usable for DMA)
xxFFD000H xxFFCFFFH
(0000H)
Access-prohibited area
xxFF8000H xxFF7FFFH Expansion ROM are
Cautions 1. Do not set odd addresses for 16-bit transfer (DCHCn register DSn = 1). 2. While the increment function is being used (DCHCn register DDADn = 0), if the DRAn register value is set to 1FFFH, it will be incremented to 2000H, and will thus become a setting-prohibited value. Remark The DRAn register setting values are in parentheses.
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(b) V850/SB1 (PD703031A, 703031AY), V850/SB2 (PD703034A, 703034AY) Set the DRAn register to a value in the range of 0000H to 2FFFH (n = 0 to 5). Setting is prohibited for values between 3000H and 3FFFH. Figure 12-3. Correspondence Between DRAn Setting Value and Internal RAM (12 KB)
(DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH On-chip peripheral I/O area (2FFFH)
Internal RAM area
12 KB (usable for DMA)
xxFFC000H xxFFBFFFH
(0000H)
Access-prohibited area
xxFF8000H xxFF7FFFH Expansion ROM area
Cautions 1. Do not set odd addresses for 16-bit transfer (DCHCn register DSn = 1). 2. While the increment function is being used (DCHCn register DDADn = 0), if the DRAn register value is set to 2FFFH, it will be incremented to 3000H, and will thus become a setting-prohibited value. Remark The DRAn register setting values are in parentheses.
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(c) V850/SB1 (PD703033A, 703033AY, 703033B, 703033BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY) V850/SB2 (PD703035A, 703035AY, 703035B, 703035BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY) Set the DRAn register to a value in the range of 000H to 2FFFH or 3000H to 3FFFH (n = 0 to 5). Figure 12-4. Correspondence Between DRAn Setting Value and Internal RAM (16 KB)
(DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH On-chip peripheral I/O area (2FFFH)
Internal RAM area xxFFC000H xxFFBFFFH xxFFB000H xxFFAFFFH
16 KB (usable for DMA) (0000H) (3FFFH) (3000H)
Access-prohibited area
xxFF8000H xxFF7FFFH Expansion ROM area
Caution Remark
Do not set odd addresses for 16-bit transfer (DCHCn register DSn =1). The DRAn register setting values are in parentheses.
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(d) V850/SB1 (PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY) V850/SB2 (PD703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY) Set the DRAn register to a value in the range of 0000H to 0FFFH or 1000H to 3FFFH (n = 0 to 5). Figure 12-5. Correspondence Between DRAn Setting Value and Internal RAM (24 KB)
(DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH xxFFE000H xxFFDFFFH On-chip peripheral I/O area (0FFFH) 4 KB (usable for DMA) (0000H)
xxFFC000H xxFFBFFFH
Internal RAM area
(3FFFH)
12 KB (usable for DMA)
xxFF9000H xxFF8FFFH xxFF8000H xxFF7FFFH
(1000H) Access-prohibited area
Expansion ROM area
Caution Remark
Do not set odd addresses for 16-bit transfer (DCHCn register DSn =1). The DRAn register setting values are in parentheses.
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(3) DMA byte count registers 0 to 5 (DBC0 to DBC5) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during the DMA transfers. A value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer. The transfers are terminated when a borrow operation occurs. Accordingly, "number of transfers - 1" should be set for byte (8-bit) transfers and "(number of transfers - 1) x 2" should be set for 16-bit transfers. These registers are can be read/written in 8-bit units.
After reset: Undefined R/W Address: DBC0 DBC1 DBC2 7 DBCn BCn7 6 BCn6 5 BCn5 4 BCn4 FFFFF184H FFFFF194H FFFFF1A4H 3 BCn3 DBC3 DBC4 DBC5 FFFFF1B4H FFFFF1C4H FFFFF1D4H 2 BCn2 1 BCn1 0 BCn0
(n = 0 to 5) Caution Values set to bit 0 are ignored during 16-bit transfers. (4) DMA start factor expansion register (DMAS) This is an 8-bit register for expanding the factors that start DMA. The DMA start factor is decided according to the combination of TTYPn1 and TTYPn0 of the DCHCn register. For setting bits DMAS2 to DMAS0, refer to 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) (n = 0 to 5). This register can be read/written in 8/1-bit units.
After reset: 00H 7 DMAS 0 R/W 6 0 Address: 5 0 FFFFF38EH 4 0 3 0 2 DMAS2 1 DMAS1 0 DMAS0
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(5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) These registers are used to control the DMA transfer operation mode for DMA channel n. These registers are can be read/written in 1-bit or 8-bit units. (1/2)
After reset:
00H
R/W
Address:
DCHC0 DCHC1 DCHC2
FFFFF186H FFFFF196H FFFFF1A6H 3 TTYPn0
DCHC3 FFFFF1B6H DCHC4 FFFFF1C6H DCHC5 FFFFF1D6H <2> TDIRn <1> DSn <0> ENn
<7> DCHCn (n = 0 to 5) TCn 0 1 TCn
6 0
<5> DDADn
4 TTYPn1
DMA transfer completed/not completedNote 1 Not completed Completed
DDADn 0 1 Increment Address is fixed
Internal RAM address count direction control
Channel n 0
DMAS2 x
DMAS1 x
DMAS0 x
TTYPn1 0 0 1 1
TTYPn0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1
DMA transfer start factor setting INTCSI0/INTIIC0Note 2 INTCSI1/INTSR0 INTAD INTTM00 INTCSI0/INTIIC0Note 2 INTCSI1/INTSR0 INTST0 INTP0 INTTM10 INTIIC1Note 2 INTCSI3/INTSR1 INTP6 INTIE1 (V850/SB2 only) INTAD INTIIC1Note 2 INTCSI3/INTSR1 INTCSI2 INTIE1 (V850/SB2 only) INTTM4
1
x
x
0 1 x
0 0 0 1 1
2
x
0 1 x
x
0 0 0 1 1
3
0 1 x
x
x
0 0 0 1 1
Caution If an interrupt source is generated asynchronously to the internal system clock, do not set the interrupt source as multiple DMA transfer triggers at the same time (for example, when the serial interface is operated with external clock input). If it is set, the DMA transfer priority may be reversed.
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(2/2)
Channel n 4 DMAS2 x DMAS1 x DMAS0 x TTYPn1 0 0 1 1 5 x x x 0 0 1 1 TTYPn0 0 1 0 1 0 1 0 1 DMA transfer start factor setting INTST1 INTCSI4 INTAD INTTM2 INTCSI3/INTSR1 INTCSI4 INTCSI2 INTTM6
TDIRn 0 1
Transfer direction control between peripheral I/Os and internal RAMNote 3 From internal RAM to peripheral I/Os From peripheral I/Os to internal RAM
DSn 0 1 8-bit transfer 16-bit transfer
Control of transfer data size for DMA transferNote 3
ENn 0 1 Disabled
Control of DMA transfer enable/disable statusNote 4
Enabled (reset to 0 after DMA transfer is completed)
Notes
1. TCn (n = 0 to 5) is set to 1 when a specified number of transfers are completed, and is cleared to 0 when a write instruction is executed. 2. INTIIC0 and INTIIC1 are available only in the Y versions (products with on-chip I C). 3. Make sure that the transfer format conforms to the peripheral I/O register specifications (accessenabled data size, read/write, etc.) for the DMA peripheral I/O address register (DIOAn). 4. After the specified number of transfers are completed, this bit is cleared to 0.
2
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12.5 Operation
When a DMA transfer request is generated during CPU processing, DMA transfer is started after the current CPU processing has finished. Regardless of the transfer direction, 4 CPU clocks (fCPU) are required for one DMA transfer. The 4 CPU clocks are divided as follows. * Internal RAM access: 1 clock * Peripheral I/O access: 3 clocks After one DMA transfer (8/16 bits) ends, control always shifts to the CPU processing. A DMA transfer operation timing chart is shown below. Figure 12-6. DMA Transfer Operation Timing
fCPU
DMA transfer processing signal
DMA transfer acknowledge signal
Processing format
CPU processing
DMA transfer processing
CPU processing
Access destination for transfer from internal RAM to peripheral I/O
RAM Peripheral I/O
Access destination for transfer from peripheral I/O to internal RAM
Peripheral I/O RAM INTDMAn occurs when a DBCn register borrow occurs
Remark
n = 0 to 5
If two or more DMA transfer requests are generated simultaneously, the DMA transfer requests are executed in accordance with the following priority order: DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5. While a higher priority DMA transfer request is being executed, the lower priority DMA transfer requests are held pending. After the higher priority DMA transfer ends, control always shifts to the CPU processing once, and then the lower priority DMA transfer is executed. The processing when the transfer requests DMA0 to DMA5 are generated simultaneously is shown below.
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Figure 12-7. Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously
CPU DAM0 CPU DAM1 CPU DAM2 CPU DAM3 CPU DAM4 CPU DAM5 CPU processing processing processing processing processing processing processing processing processing processing processing processing processing
Transfer requests DMA0 to DMA5 are generated simultaneously
DMA operation stops only in the IDLE/STOP mode. In the HALT mode, DMA operation continues. DMA also operates during the bus hold period and after access to the external memory.
12.6 Cautions
When using the DMA function, if all the following conditions are met during the EI state (interrupt enable state), two interrupts occur when only one interrupt would occur normally. [Occurrence conditions] (i) (ii) A bit manipulation instruction (SET1, CLR1, NOT1, TST1) was executed to the interrupt request flag (xxIFn) of the interrupt control register (xxICn). An interrupt was processed by hardware at the same register as the register used in (i). xx: Identifying name of peripheral unit (see Table 5-2) n: Peripheral unit number (see Table 5-2) For example, when using the DMA function, if an unmasked INTCSI0 interrupt occurs during bit manipulation of the interrupt request flag (CSIF0) of the CSIC0 register by the CLR1 instruction, INTCSI0 interrupt servicing occurs twice. Under such conditions, because the interrupt request flag (xxIF) is not cleared (0) by hardware when the interrupt servicing is acknowledged, the interrupt servicing is executed again after RETI instruction execution (interrupt servicing restoration). Therefore, use the DMA function under either of the following conditions. [Use conditions] (i) (ii) When bit manipulation is executed for the interrupt control register (xxICn), the DI instruction must be executed before the manipulation and the EI instruction must be executed after the manipulation. The interrupt request flag (xxIFn) must be cleared (0) at the start of the interrupt routine. When the DMA function is not used, execution of (i) or (ii) is not necessary. xx: Identification name of each peripheral unit (see Table 5-2) n: Peripheral unit number (see Table 5-2)
Remark
Caution Remark
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Figure 12-8. When Interrupt Servicing Occurs Twice During DMA Operation (1/2) (a) Normal interrupt servicing
Main routine Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0). EI
Interrupt request
RETI
(b) Interrupt servicing when interrupt servicing occurs twice
Main routine EI Bit manipulation instruction to xxIFn Interrupt request Since the interrupt request flag (xxIFn) remains 1, the interrupt is serviced again. Interrupt servicing routine Interrupt request flag (xxIFn) is not cleared and remains 1.
RETI Interrupt request flag (xxIFn) is cleared (0).
RETI
Remark
xx: Identification name of each peripheral unit (see Table 5-2) n: Peripheral unit number (see Table 5-2)
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Figure 12-8. When Interrupt Servicing Occurs Twice During DMA Operation (2/2) (c) Countermeasure (use condition (i))
Main routine EI DI Bit manipulation instruction to xxIFn Interrupt request EI The interrupt is serviced in the EI state (interrupt enable state) (the interrupt is not serviced immediately after bit manipulation instruction execution).
Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0).
RETI
(d) Countermeasure (use condition (ii))
Main routine EI Bit manipulation instruction to xxIFn Interrupt request EI Interrupt servicing routine Interrupt request flag (xxIFn) is not cleared (0) and remains 1. xxIFn is cleared (0) at the start of the interrupt servicing routine
RETI
Remark
xx: Identification name of each peripheral unit (see Table 5-2) n: Peripheral unit number (see Table 5-2)
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REAL-TIME OUTPUT FUNCTION (RTO)
13.1 Function
The V850/SB1 and V850/SB2 incorporate a real-time output function (RTO) that transfers preset data to real-time output buffer registers (RTBL, RTBH) and then transfers this data with hardware to an external device via the output latches, upon the occurrence of an external interrupt or external trigger. Because RTO can output signals without jitter, it is suitable for controlling a stepper motor. The real-time output port can be set in port mode or real-time output port mode in 1-bit units.
13.2 Features
8-bit real-time output unit Port mode and real-time output mode can be selected in 1-bit units 8 bits x 1 channel or 4 bits x 2 channels can be selected Trigger signal: Selectable from the following three. External interrupt: RTPTRG Internal interrupt: INTTM4, INTTM5
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13.3 Configuration
A block diagram of RTO is shown below. Figure 13-1. Block Diagram of RTO
Internal bus Real-time output port control register (RTPC) RTPOE RTPEG BYTE 4 RTPTRG INTTM4 INTTM5 Output trigger controller Real-time output Real-time output buffer register, higher buffer register, lower 4 bits (RTBH) 4 bits (RTBL) Real-time output port mode register (RTPM) EXTR
Output latch
RTP7
RTP6
RTP5
RTP4
RTP3
RTP2
RTP1
RTO includes the following hardware. Table 13-1. Configuration of RTO
Item Registers Control registers Configuration Real-time output buffer registers (RTBL, RTBH) Real-time output port mode register (RTPM) Real-time output port control register (RTPC)
RTP0
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(1) Real-time output buffer registers (RTBL, RTBH) RTBL and RTBH are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the peripheral I/O register area as shown in Figure 132. If an operation mode of 4 bits x 2 channels is specified, data can be individually set to RTBL and RTBH. The data of both the registers can be read all at once by specifying the address of either of the registers. If an operation mode of 8 bits x 1 channel is specified, 8-bit data can be set to both RTBL and RTBH respectively by writing the data to either of the registers. The data of both the registers can be read all at once by specifying the address of either of the registers. Figure 13-2 shows the configuration of RTBL and RTBH, and Table 13-2 shows the operation to be performed when RTBL and RTBH are manipulated. Figure 13-2. Configuration of Real-Time Output Buffer Registers
Higher 4 bits Lower 4 bits RTBL RTBH
Table 13-2. Operation When Real-Time Output Buffer Registers Are Manipulated
Operation Mode Register to Be Manipulated Read Higher 4 bits 4 bits x 2 channels RTBL RTBH 8 bits x 1 channel RTBL RTBH RTBH RTBH RTBH RTBH
Note 1
Write Higher 4 bits Invalid RTBH RTBH RTBH
Note 2
Lower 4 bits RTBL RTBL RTBL RTBL
Lower 4 bits RTBL Invalid RTBL RTBL
Notes 1. Only the bits set in the real-time output port mode (RTPM) can be read. If a bit set in the port mode is read, 0 is read. 2. Set output data to RTBL and RTBH after setting the real-time output port and before the real-time output trigger is generated. (2) Output latch This is the output latch to which the value set by the real-time output buffer register (RTBL, RTBH) is automatically transferred when the real-time output trigger occurs. Output latches cannot be accessed. A port specified as a real-time output port cannot set data to the port output latch. To set the initial values of the real-time output port, set data to the port output latch in the port mode and then set to the real-time output port mode (refer to 13.5 Usage).
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13.4 RTO Control Registers
RTO is controlled by using the following two types of registers. * * Real-time output port mode register (RTPM) Real-time output port control register (RTPC)
(1) Real-time output port mode register (RTPM) This register selects real-time output port mode or port mode in 1-bit units. RTPM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears RTPM to 00H.
After reset: 00H 7 RTPM RTPM7 R/W 6 RTPM6 Address: FFFFF3A4H 5 RTPM5 4 RTPM4 3 RTPM3 2 RTPM2 1 RTPM1 0 RTPM0
RTPMn 0 1 Port mode
Selection of real-time output port (n = 0 to 7)
Real-time output port mode
Cautions 1. Set a port pin to the output mode when it is used as a real-time output port pin. 2. A port specified as a real-time output port cannot set data to the port output latch. To set the initial values of the real-time output port, set data to the port output latch in the port mode and then set to the real-time output port mode (refer to 13.5 Usage).
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(2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 133. RTPC is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears RTPC to 00H.
After reset: 00H <7> RTPC RTPOE R/W <6> RTPEG Address: FFFFF3A6H <5> BYTE <4> EXTR 3 0 2 0 1 0 0 0
RTPOE 0 1 Disable operation Enable operation
Note
Control of operation of real-time output port
RTPEG 0 1 Falling edge Rising edge
Valid edge of RTPTRG
BYTE 0 1 4 bits x 2 channels 8 bits x 1 channel
Operation mode of real-time output port
EXTR 0 1
Control of real-time output by RTPTRG signal Do not use RTPTRG as real-time output trigger Use RTPTRG as real-time output trigger
Note
RTP0 to RTP7 output 0 if the real-time output operation is disabled (RTPOE = 0). Table 13-3. Operation Mode and Output Trigger of Real-Time Output Port
BYTE 0
EXTR 0 1
Operation Mode 4 bits x 2 channels
RTBH Port Output INTTM5 INTTM4
RTBL Port Output INTTM4 RTPTRG
1
0 1
8 bits x 1 channel
INTTM4 RTPTRG
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13.5 Usage
(1) Disable the real-time output operation. Clear bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Initial setting (i) Set the value to be output first to the real-time output port to the output latch of port 10. (ii) Set the PM10 register to output mode. (iii) Specify the real-time output port mode or port mode in 1-bit units. Set the real-time output port mode register (RTPM). (iv) Select a trigger and valid edge. Set bits 4, 5, and 6 (EXTR, BYTE, and RTPEG) of RTPC. (v) Set the same value as (i) to the real-time output buffer registers (RTBH and RTBL). (3) Enable the real-time output operation. Set RTPOE to 1. (4) Set the output latches (P100 to P107) of port 10 to 0, and the next output to RTBH and RTBL before the selected transfer trigger is generated. (5) Set the next real-time output value to RTBH and RTBL by interrupt servicing corresponding to the selected trigger.
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13.6 Operation
If the real-time output operation is enabled by setting bit 7 (RTPOE) of the real-time output port control register (RTPC) to 1, the data of the real-time output buffer registers (RTBH and RTBL) is transferred to the output latch in synchronization with the generation of the selected transmit trigger (set by EXTR and BYTE
Note
). Of the transferred
data, only the data of the bits specified in the real-time output mode by the real-time output port mode register (RTPM) is output from the bits of RTP0 to RTP7. The bits specified in the port mode by RTPM output 0. If the real-time output operation is disabled by clearing RTPOE to 0, RTP0 to RTP7 output 0 regardless of the setting of RTPM. Note EXTR: Bit 4 of the real-time output port control register (RTPC) BYTE: Bit 5 of the real-time output port control register (RTPC) Figure 13-3. Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0)
INTTM5 (internal)
INTTM4 (internal)
CPU operation
A D01 D11 D01
B D02
A
B D03
A
B D04
A
B
RTBH
RTBL
D12 D02 D11 D12
D13 D03 D13
D14 D04 D14
RT output latch (H)
RT output latch (L)
A: Software processing by interrupt request input to INTTM5 (RTBH write) B: Software processing by interrupt request input to INTTM4 (RTBL write)
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13.7 Cautions
(1) Before performing initialization, disable the real-time output operation by clearing bit 7 (RTPOE) of the real-time output port control register (RTPC) to 0. (2) Once the real-time output operation is disabled (RTPOE = 0), be sure to set the same initial value as the output latch to the real-time output buffer registers (RTBH and RTBL) before enabling the real-time output operation (RTPOE = 0 1). (3) Operation cannot be guaranteed if a conflict between the following signals occurs. Use software to avoid a conflict. * Conflict between the switch operation from the RTP mode to the port mode (RTPOE = 1) and the valid edge of the selected real-time output port trigger * Conflict between the write operation to the real-time output buffer register (RTBL, RTBH) in the RTP mode and the valid edge of the selected real-time output port trigger
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14.1 Port Configuration
The V850/SB1 and V850/SB2 include 83 I/O port pins from ports 0 to 11 (12 port pins are input only). There are three power supplies for the I/O buffers: AVDD, BVDD, and EVDD, which are described below. Table 14-1. Pin I/O Buffer Power Supplies
Power Supply AVDD Port 7, port 8 Corresponding Pins Usable Voltage Range When using A/D converter: 4.5 V AVDD 5.5 V When using A/D converter: 3.5 V AVDD 5.5 V 3.0 V BVDD 5.5 V 3.0 V EVDD 5.5 V
BVDD EVDD
Port 4, port 5, port 6, port 9, CLKOUT Port 0, port 1, port 2, port 3, port 10, port 11, RESET
Caution The electrical specifications in the case of 3.0 to up to 4.0 V are different from those for 4.0 to 5.5 V.
14.2 Port Pin Function
14.2.1 Port 0 Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). When using P00 to P04 as the NMI or INTP0 to INTP3 pins, noise is eliminated by an analog noise eliminator. When using P05 to P07 as the INTP4/ADTRG, INTP5/RTPTRG, and INTP6 pins, noise is eliminated by a digital noise eliminator.
After reset:
00H
7
R/W 6 P06 5 P05
Address: FFFFF000H 4 P04 3 P03 2 P02 1 P01 0 P00
P0
P07
P0n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0, 1)
Remark
In input mode:
When the P0 register is read, the pin levels at that time are read. Writing to P0 writes the values to that register. This does not affect the input pins.
In output mode: When the P0 register is read, the P0 register's values are read. Writing to P0 writes the values to that register, and those values are immediately output.
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Port 0 includes the following alternate functions. Table 14-2. Port 0 Alternate Function Pins
Pin Name Port 0 P00 P01 P02 P03 P04 P05 P06 P07 NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 Digital noise elimination Alternate Function I/O I/O PULLNote Yes Remark Analog noise elimination
Note Software pull-up function
(1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 0 mode register (PM0). In output mode, the values set to each bit are output to the port 0 register (P0). When using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for NMI requests). When using this port in input mode, the pin statuses can be read by reading the P0 register. Also, the P0 register (output latch) values can be read by reading the P0 register while in output mode. The valid edge of NMI and INTP0 to INTP6 are specified via rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0). A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 0 (PU0). When a reset is input, the settings are initialized to input mode. Also, the valid edge of each interrupt request becomes invalid (NMI and INTP0 to INTP6 do not function immediately after reset). (2) Noise elimination (a) Elimination of noise from NMI and INTP0 to INTP3 pins An on-chip noise eliminator uses analog delay to eliminate noise. edge detection occurs after the specified amount of time. (b) Elimination of noise from INTP4 to INTP6, ADTRG, and RTPTRG pins A digital noise eliminator is provided on chip. This circuit uses digital sampling. A pin's input level is detected using a sampling clock (fXX), and noise elimination is performed for the INTP4, INTP5, ADTRG, and RTPTRG pins if the same level is not detected three times consecutively. The noise-elimination width can be changed for the INTP6 pin (see 5.3.8 (3) Noise elimination of INTP6 pin). Consequently, if a signal having a constant level is input for longer than a specified time to these pins, it is detected as a valid edge. Such
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Cautions 1. If the input pulse width is 2 to 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undefined. 2. To ensure correct detection of pulses as pulses, constant-level input is required for 3 clocks or more. 3. If noise is occurring in synchronization with the sampling clock, it may not be recognized as noise. In such cases, attach a filter to the input pins to eliminate the noise. 4. Noise elimination is not performed when these pins are used as an normal input port pins. (3) Control registers (a) Port 0 mode register (PM0) PM0 can be read/written in 8-bit or 1-bit units.
After reset:
FFH
7
R/W 6 PM06 5 PM05
Address: FFFFF020H 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00
PM0
PM07
PM0n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
(b) Pull-up resistor option register 0 (PU0) PU0 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 PU06 5 PU05
Address: FFFFF080H 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00
PU0
PU07
PU0n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 7)
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(c) Rising edge specification register 0 (EGP0) EGP0 can be read/written in 8-bit or 1-bit units.
After reset:
00H
<7>
R/W <6> EGP06 <5> EGP05
Address: FFFFF0C0H <4> EGP04 <3> EGP03 <2> EGP02 <1> EGP01 <0> EGP00
EGP0
EGP07
EGP0n 0 1
Control of rising edge detection (n = 0 to 7) Interrupt request signal did not occur at rising edge Interrupt request signal occurred at rising edge
Remark
n = 0: n = 1 to 7:
Control of NMI pin Control of INTP0 to INTP6 pins
(d) Falling edge specification register 0 (EGN0) EGN0 can be read/written in 8-bit or 1-bit units.
After reset:
00H
<7>
R/W <6> EGN06 <5> EGN05
Address: FFFFF0C2H <4> EGN04 <3> EGN03 <2> EGN02 <1> EGN01 <0> EGN00
EGN0
EGN07
EGN0n 0 1
Control of falling edge detection (n = 0 to 7) Interrupt request signal did not occur at falling edge Interrupt request signal occurred at falling edge
Remark
n = 0: n = 1 to 7:
Control of NMI pin Control of INTP0 to INTP6 pins
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(4) Block diagram (Port 0) Figure 14-1. Block Diagram of P00 to P07
VDD
WRPU
PU0 PU0n P-ch
RD
Selector WRPORT Output latch (P0n) P00/NMI P01/INTP0 P02/INTP1 P03/INTP2 P04/INTP3 P05/INTP4/ADTRG P06/INTP5/RTPTRG P07/INTP6
Internal bus
WRPM
PM0 PM0n
Remarks 1. PU0: Pull-up resistor option register 0 PM0: Port 0 mode register RD: WR: Port 0 read signal Port 0 write signal
2. n = 0 to 7
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14.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Bits 0, 1, 2, 4, and 5 are selectable as normal outputs or N-ch open-drain outputs.
After reset:
00H
7
R/W 6 0 5 P15
Address: FFFFF002H 4 P14 3 P13 2 P12 1 P11 0 P10
P1
0
P1n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 5)
Remark
In input mode:
When the P1 register is read, the pin levels at that time are read. Writing to P1 writes the values to that register. This does not affect the input pins.
In output mode: When the P1 register is read, the P1 register's values are read. Writing to P1 writes the values to that register, and those values are immediately output. Port 1 includes the following alternate functions. SDA0 and SCL0 pins are available only in the Y versions (products with on-chip I C). Table 14-3. Port 1 Alternate Function Pins
Pin Name Port 1 P10 P11 P12 P13 P14 P15 Alternate Function SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 - Selectable as N-ch open-drain output I/O I/O PULLNote Yes Remark Selectable as N-ch open-drain output
2
Note Software pull-up function
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(1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to the port 1 register (P1). The port 1 function register (PF1) can be used to specify whether P10 to P12, P14, and P15 are normal outputs or N-ch open-drain outputs. When using this port in input mode, the pin statuses can be read by reading the P1 register. Also, the P1 register (output latch) values can be read by reading the P1 register while in output mode. A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 1 (PU1). Clear the P1 and PM1 registers to 0 when using alternate-function pins as outputs. The ORed result of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 1 mode register (PM1) PM1 can be read/written in 8-bit or 1-bit units.
After reset: 3FH 7 PM1 0 R/W 6 0 5 PM15 Address: FFFFF022H 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10
PM1n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
(b) Pull-up resistor option register 1 (PU1) PU1 can be read/written in 8-bit or 1-bit units.
After reset: 00H 7 PU1 0 R/W 6 0 5 PU15 Address: FFFFF082H 4 PU14 3 PU13 2 PU12 1 PU11 0 PU10
PU1n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 5)
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(c) Port 1 function register (PF1) PF1 can be read/written in 8-bit or 1-bit units.
After reset: 00H 7 PF1 0 R/W 6 0 5 PF15 Address: FFFFF0A2H 4 PF14 3 0
Note
2 PF12
1 PF11
0 PF10
PF1n 0 1 Normal output
Control of normal output/N-ch open-drain output (n = 0 to 2, 4, 5)
N-ch open-drain output
Note Bit 3 is fixed as a normal output.
(3) Block diagram (Port 1) Figure 14-2. Block Diagram of P10 to P12, P14, and P15
VDD WRPU
PU1 PU1n P-ch
RD
Selector
Internal bus
WRPF
PF1 PF1n VDD
WRPORT Output latch (P1n) WRPM PM1 PM1n P-ch N-ch P10/SI0/SDA0Note P11/SO0 P12/SCK0/SCL0Note P14/SO1/TxD0 P15/SCK1/ASCK0
Alternate function
Note
The SDA0 and SCL0 pins are available only in the Y versions (products with on-chip I C).
2
Remarks 1. PU1: Pull-up resistor option register 1 PF1: RD: WR: Port 1 function register Port 1 read signal Port 1 write signal PM1: Port 1 mode register
2. n = 0 to 2, 4, 5
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Figure 14-3. Block Diagram of P13
VDD WRPU
PU1 PU13 P-ch
RD
Selector
Internal bus
WRPORT Output latch (P13)
P13/SI1/RxD0
WRPM
PM1 PM13
Alternate function
Remark
PU1: RD: WR:
Pull-up resistor option register 1 Port 1 read signal Port 1 write signal
PM1: Port 1 mode register
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14.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). P20, P21, P22, P24 and P25 are selectable as normal outputs or N-ch open-drain outputs. When P26 and P27 are used as the TI2 and TI3 pins, noise is eliminated from these pins by a digital noise eliminator.
After reset:
00H
7
R/W 6 P26 5 P25
Address: FFFFF004H 4 P24 3 P23 2 P22 1 P21 0 P20
P2
P27
P2n 0 1 Outputs 0 Outputs 1
Control of output data (in output mode) (n = 0 to 7)
Remark
In input mode:
When the P2 register is read, the pin levels at that time are read. Writing to P2 writes the values to that register. This does not affect the input pins.
In output mode: When the P2 register is read, the P2 register's values are read. Writing to P2 writes the values to that register, and those values are immediately output. Port 2 includes the following alternate functions. SDA1 and SCL1 are available only in the Y versions (products with on-chip I C). Table 14-4. Port 2 Alternate Function Pins
Pin Name Port 2 P20 P21 P22 P23 P24 P25 P26 P27 Alternate Function SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 Digital noise elimination - Selectable as N-ch open-drain output I/O I/O PULLNote Yes Remark Selectable as N-ch open-drain output
2
Note Software pull-up function
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(1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to the port 2 register (P2). The port 2 function register (PF2) can be used to specify whether P20, P21, P22, P24 and P25 are normal outputs or N-ch open-drain outputs. When using this port in input mode, the pin statuses can be read by reading the P2 register. Also, the P2 register (output latch) values can be read by reading the P2 register while in output mode. A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 2 (PU2). When using the alternate function as TI2 and TI3 pins, noise elimination is provided by a digital noise eliminator (same as digital noise eliminator for port 0). Clear the P2 and PM2 registers to 0 when using alternate-function pins as outputs. The ORed result of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 2 mode register (PM2) PM2 can be read/written in 8-bit or 1-bit units.
After reset: FFH 7 PM2 PM27 R/W 6 PM26 5 PM25 Address: FFFFF024H 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20
PM2n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
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(b) Pull-up resistor option register 2 (PU2) PU2 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 PU26 5 PU25
Address: FFFFF084H 4 PU24 3 PU23 2 PU22 1 PU21 0 PU20
PU2
PU27
PU2n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 7)
(c) Port 2 function register (PF2) PF2 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 0 5 PF25
Address: FFFFF0A4H 4 PF24 3 0 2 PF22 1 PF21 0 PF20
PF2
0
PF2n 0 1 Normal output
Control of normal output/N-ch open-drain output (n = 0 to 2, 4, 5)
N-ch open-drain output
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(3) Block diagram (Port 2) Figure 14-4. Block Diagram of P20 to P22, P24, and P25
VDD WRPU
PU2 PU2n P-ch
RD
Selector
Internal bus
WRPF
PF2 PF2n VDD
WRPORT Output latch (P2n) WRPM PM2 PM2n P-ch N-ch P20/SI2/SDA1Note P21/SO2 P22/SCK2/SCL1Note P24/SO3/TxD1 P25/SCK3/ASCK1
Alternate function
Note
The SDA1 and SCL1 pins are available only in the Y versions (products with on-chip I C).
2
Remarks 1. PU2: Pull-up resistor option register 2 PF2: RD: WR: Port 2 function register Port 2 read signal Port 2 write signal PM2: Port 2 mode register
2. n = 0 to 2, 4, 5
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Figure 14-5. Block Diagram of P23, P26, and P27
VDD WRPU
PU1 PU13 P-ch
RD
Selector
Internal bus
WRPORT Output latch (P13)
P13/SI1/RxD0
WRPM
PM1 PM13
Alternate function
Remarks 1. PU2: Pull-up resistor option register 2 PM2: Port 2 mode register RD: WR: Port 2 read signal Port 2 write signal
2. n = 3 , 6, or 7
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14.2.4 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). Either a normal output or N-ch open-drain out can be selected for P33 and P34. When using P36 and P37 as the TI4 and TI5 pins, noise is eliminated by the digital noise eliminator.
After reset:
00H
7
R/W 6 P36 5 P35
Address: FFFFF006H 4 P34 3 P33 2 P32 1 P31 0 P30
P3
P37
P3n 0 1 Output 0 Output 1
Control of output data (In output mode) (n = 0 to 7)
Remark
In input mode:
When the P3 register is read, the pin levels at that time are read. Writing to P3 writes the values to that register. This does not affect the input pins.
In output mode: When the P3 register is read, the P3 register's values are read. Writing to P3 writes the values to that register, and those values are immediately output. Port 3 includes the following alternate functions. Table 14-5. Port 3 Alternate Function Pins
Pin Name Port 3 P30 P31 P32 P33 P34 P35 P36 P37 TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 - Digital noise elimination Selectable as N-ch open-drain output. Alternate Function I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(1) Function of P3 pins Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to the port 3 register (P3). The port 3 function register (PF3) can be used to specify whether P33 and P34 are normal outputs or N-ch open-drain outputs. When using this port in input mode, the pin statuses can be read by reading the P3 register. Also, the P3 register (output latch) values can be read by reading the P3 register while in output mode. A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 3 (PU3). When using the alternate-function TI4 and TI5 pins, noise elimination is provided by a digital noise eliminator (same as digital noise eliminator for port 0). When using the alternate-function A13 to A15 pins, set the pin functions via the memory address output mode register (MAM). At this time, be sure to set the PM3 registers (PM34, PM35, PM36) and the P3 registers (P34, P35, P36) to 0. Clear the P3 and PM3 registers to 0 when using alternate-function pins as outputs. The ORed result of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 3 mode register (PM3) PM3 can be read/written in 8-bit or 1-bit units.
After reset:
FFH
7
R/W 6 PM36 5 PM35
Address: FFFFF026H 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30
PM3
PM37
PM3n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
(b) Pull-up resistor option register 3 (PU3) PU3 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 PU36 5 PU35
Address: FFFFF086H 4 PU34 3 PU33 2 PU32 1 PU31 0 PU30
PU3
PU37
PU3n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 7)
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(c) Port 3 function register (PF3) PF3 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 0 5 0
Address: FFFFF0A6H 4 PF34 3 PF33 2 0 1 0 0 0
PF3
0
PF3n 0 1 Normal output
Control of normal output/N-ch open-drain output (n = 3, 4)
N-ch open-drain output
(3) Block diagram (Port 3) Figure 14-6. Block Diagram of P30 to P32 and P35 to P37
VDD WRPU
PU3 PU3n P-ch
RD
Selector
Internal bus
WRPORT Output latch (P3n)
P30/TI00 P31/TI01 P32/TI10/SI4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5
WRPM
PM3 PM3n
Alternate function
Remarks 1. PU3: Pull-up resistor option register 3 PM3: Port 3 mode register RD: WR: Port 3 read signal Port 3 write signal
2. n = 0 to 2, 5 to 7
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Figure 14-7. Block Diagram of P33 and P34
VDD WRPU
PU3 PU3n P-ch
RD
Selector
Internal bus
WRPF
PF3 PF3n VDD
WRPORT Output latch (P3n) WRPM PM3 PM3n P-ch N-ch P33/TI11/SO4 P34/TO0/A13/SCK4
Alternate function
Remarks 1. PU3: Pull-up resistor option register 3 RF3: Port 3 function register PM3: Port 3 mode register RD: WR: Port 3 read signal Port 3 write signal
2. n = 3, 4
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14.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units.
After reset:
00H
7
R/W 6 Pn6 5 Pn5
Address: FFFFF008H, FFFFF00AH 4 Pn4 3 Pn3 2 Pn2 1 Pn1 0 Pn0
Pn
Pn7
Pnx 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 4, 5, x = 0 to 7)
Remark
In input mode:
When the P4 and P5 registers are read, the pin levels at that time are read. Writing to P4 and P5 writes the values to those registers. This does not affect the input pins.
In output mode: When the P4 and P5 registers are read, their values are read. Writing to P4 and P5 writes the values to those registers, and those values are immediately output. Ports 4 and 5 include the following alternate functions. Table 14-6. Alternate Function Pins of Ports 4 and 5
Pin Name Port 4 P40 P41 P42 P43 P44 P45 P46 P47 Port 5 P50 P51 P52 P53 P54 P55 P56 P57 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 I/O No - Alternate Function I/O I/O PULLNote No Remark -
Note Software pull-up function
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(1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 4 mode register (PM4) the and port 5 mode register (PM5). In output mode, the values set to each bit are output to the port 4 and 5 registers (P4 and P5). When using these ports in input mode, the pin statuses can be read by reading the P4 and P5 registers. Also, the P4 and P5 register (output latch) values can be read by reading the P4 and P5 registers while in output mode. A software pull-up function is not implemented. When using the alternate function as AD0 to AD15, set the pin functions via the memory expansion register (MM). This does not affect the PM4 and PM5 registers. When a reset is input, the settings are initialized to input mode. (2) Control register (a) Port 4 mode register and port 5 mode register (PM4 and PM5) PM4 and PM5 can be read/written in 1-bit or 8-bit units.
After reset: FFH 7 PMn (n = 4, 5) PMnx 0 1 Output mode Input mode Control of I/O mode (n = 4, 5, x = 0 to 7) PMn7 R/W 6 PMn6 5 PMn5 Address: FFFFF028H, FFFFF02AH 4 PMn4 3 PMn3 2 PMn2 1 PMn1 0 PMn0
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(3) Block diagram (Ports 4 and 5) Figure 14-8. Block Diagram of P40 to P47 and P50 to P57
RD
Selector
Internal bus
WRPORT Output latch (mn) Pmn/ADx
WRPM
PMm PMmn
Remarks 1. PMm: Port m mode register RD: WR: Port m read signal Port m write signal
2. m = 4, 5 n = 0 to 7 x = 0 to 15
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14.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units.
After reset:
00H
7
R/W 6 0 5 P65
Address: FFFFF00CH 4 P64 3 P63 2 P62 1 P61 0 P60
P6
0
P6n 0 1 Outputs 0 Outputs 1
Control of output data (in output mode) (n = 0 to 5)
Remark
In input mode:
When the P6 register is read, the pin levels at that time are read. Writing to P6 writes the values to that register. This does not affect the input pins.
In output mode: When the P6 register is read, the P6 register's values are read. Writing to P6 writes the values to that register, and those values are immediately output. Port 6 includes the following alternate functions. Table 14-7. Port 6 Alternate Function Pins
Pin Name Port 6 P60 P61 P62 P63 P64 P65 A16 A17 A18 A19 A20 A21 Alternate Function I/O I/O PULLNote No Remark -
Note Software pull-up function
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(1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 6 mode register (PM6). In output mode, the values set to each bit are output to the port 6 register (P6). When using this port in input mode, the pin statuses can be read by reading the P6 register. Also, the P6 register (output latch) values can be read by reading the P6 register while in output mode. A software pull-up function is not implemented. When using the alternate-function A16 to A21 pins, set the pin functions via the memory expansion register (MM). This does not affect the PM6 register. When a reset is input, the settings are initialized to input mode. (2) Control register (a) Port 6 mode register (PM6) PM6 can be read/written in 8-bit or 1-bit units.
After reset:
3FH
7
R/W 6 0 5 PM65
Address: FFFFF02CH 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60
PM6
0
PM6n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
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(3) Block diagram (Port 6) Figure 14-9. Block Diagram P60 to P65
RD
Selector Internal bus WRPORT Output latch (P6n) P6n/Ax
WRPM
PM6 PM6n
Remarks 1. PM6: Port 6 mode register RD: WR: Port 6 read signal Port 6 write signal
2. n = 0 to 5 x = 16 to 21
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14.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8-bit or 1-bit units.
After reset: Undefined 7 P7 P77 R 6 P76 5 P75 Address: FFFFF00EH 4 P74 3 P73 2 P72 1 P71 0 P70
P7n 0/1 Read pin level of bit n
Pin level (n = 0 to 7)
After reset:
Undefined 7
R 6 0 5 0
Address: FFFFF010H 4 0 3 P83 2 P82 1 P81 0 P80
P8
0
P8n 0/1 Read pin level of bit n
Pin level (n = 0 to 3)
Ports 7 and 8 include the following alternate functions. Table 14-8. Alternate Function Pins of Ports 7 and 8
Pin Name Port 7 P70 P71 P72 P73 P74 P75 P76 P77 Port 8 P80 P81 P82 P83 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 Input No - Alternate Function I/O Input PULLNote No Remark -
Note Software pull-up function
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(1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading the port 7 and 8 registers (P7 and P8). Data cannot be written to P7 or P8. A software pull-up function is not implemented. Values read from pins specified as analog inputs are undefined values. Do not read values from P7 or P8 during A/D conversion. (2) Block diagram (Ports 7 and 8) Figure 14-10. Block Diagram of P70 to P77 and P80 to P83
RD
Internal bus
Pmn/ANIx
Remarks 1. RD:
Port 7, port 8 read signals
2. m = 7, 8 n = 0 to 7 (m = 7), 0 to 3 (m = 8) x = 0 to 7 (m = 7), 8 to 11 (m = 8)
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14.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units.
After reset:
00H
7
R/W 6 P96 5 P95
Address: FFFFF012H 4 P94 3 P93 2 P92 1 P91 0 P90
P9
0
P9n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 6)
Remark
In input mode:
When the P9 register is read, the pin levels at that time are read. Writing to P9 writes the values to that register. This does not affect the input pins.
In output mode: When the P9 register is read, the P9 register's values are read. Writing to P9 writes the values to that register, and those values are immediately output. Port 9 includes the following alternate functions. Table 14-9. Port 9 Alternate Function Pins
Pin Name Port 9 P90 P91 P92 P93 P94 P95 P96 Alternate Function LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ I/O I/O PULLNote No Remark -
Note Software pull-up function
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(1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to the port 9 register (P9). When using this port in input mode, the pin statuses can be read by reading the P9 register. Also, the P9 register (output latch) values can be read by reading the P9 register while in output mode. A software pull-up function is not implemented. When using the P9 for control signals in expansion mode, set the pin functions via the memory expansion mode register (MM). When a reset is input, the settings are initialized to input mode. Caution When using port 9 as an I/O port, set the BIC bit of the system control register (SYC) to 0. After the system is reset, the BIC bit is 0. (2) Control register (a) Port 9 mode register (PM9) PM9 can be read/written in 1-bit or 8-bit units.
After reset:
7FH
7
R/W 6 PM96 5 PM95
Address: FFFFF032H 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90
PM9
0
PM9n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 6)
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(3) Block diagram (Port 9) Figure 14-11. Block Diagram of P90 to P96
RD
Selector
Internal bus
WRPORT Output latch (P9n)
P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ
WRPM
PM9 PM9n
Remarks 1. PM9: Port 9 mode register RD: WR: Port 9 read signal Port 9 write signal
2. n = 0 to 6
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14.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). The pins in this port are selectable as normal outputs or N-ch open-drain outputs. When using P100 to P107 as KR0 to KR7 pins, noise is eliminated by the analog noise eliminator.
After reset:
00H
7
R/W 6 P106 5 P105
Address: FFFFF014H 4 P104 3 P103 2 P102 1 P101 0 P100
P10
P107
P10n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 7)
Remark
In input mode:
When the P10 register is read, the pin levels at that time are read. Writing to P10 writes the values to that register. This does not affect the input pins.
In output mode: When the P10 register is read, the P10 register's values are read. Writing to P10 writes the values to that register, and those values are immediately output. Port 10 includes the following alternate functions. IERX and IETX pins are valid only in the V850/SB2. Table 14-10. Port 10 Alternate Function Pins
Pin Name Port 10 P100 P101 P102 P103 P104 P105 P106 P107 Alternate Function RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4/IERX RTP5/A10/KR5/IETX RTP6/A11/KR6 RTP7/A12/KR7 I/O I/O PULLNote Yes Remark Selectable as N-ch open-drain outputs Analog noise elimination
Note Software pull-up function
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(1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to the port 10 register (P10). The port 10 function register (PF10) can be used to specify whether outputs are normal outputs or N-ch open-drain outputs. When using this port in input mode, the pin statuses can be read by reading the P10 register. Also, the P10 register (output latch) values can be read by reading the P10 register while in output mode. A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 10 (PU10). When using the alternate-function A5 to A12 pins, see the pin functions via the memory address output mode register (MAM). At this time, be sure to set P10 and PM10 to 0. When used as the KR0 to KR7 pins, noise is eliminated by the analog noise eliminator. When using alternate-function pins as outputs, the ORed result of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. Caution When using port 10 as a real-time output port, set in accordance with 13. 5 Usage. (2) Control register (a) Port 10 mode register (PM10) PM10 can be read/written in 1-bit or 8-bit units.
After reset:
FFH
7
R/W 6 PM106 5 PM105
Address: FFFFF034H 4 PM104 3 PM103 2 PM102 1 PM101 0 PM100
PM10
PM107
PM10n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
(b) Pull-up resistor option register 10 (PU10) PU10 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 PU106 5 PU105
Address: FFFFF094H 4 PU104 3 PU103 2 PU102 1 PU101 0 PU100
PU10
PU107
PU10n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 7)
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(c) Port 10 function register (PF10) PF10 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 PF106 5 PF105
Address: FFFFF0B4H 4 PF104 3 PF103 2 PF102 1 PF101 0 PF100
PF10
PF107
PF10n 0 1 Normal output
Control of normal output/N-ch open-drain output (n = 0 to 7)
N-ch open-drain output
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(3) Block diagram (Port 10) Figure 14-12. Block Diagram of P100 to P107
VDD WRPU
PU10 PU10n P-ch
RD
Selector
Internal bus
WRPF
PF10 PF10n VDD P100/RTP0/A5/KR0 P101/RTP1/A6/KR1 P102/RTP2/A7/KR2 P103/RTP3/A8/KR3 P104/RTP4/A9/KR4/IERXNote P105/RTP5/A10/KR5/IETXNote P106/RTP6/A11/KR6 P107/RTP7/A12/KR7
WRPORT Output latch (P10n) WRPM PM10 PM10n P-ch N-ch
Alternate function
Note
The IERX, IETX pins apply only to the V850/SB2.
Remarks 1. PU10: Pull-up resistor option register 10 RF10: Port 10 function register PM10: Port 10 mode register RD: WR: Port 10 read signal Port 10 write signal
2. n = 0 to 7
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14.2.10 Port 11 Port 11 is a 4-bit port. A pull-up resistor can be connected to bits 0 to 3 in 1-bit units (software pull-up function). P11 can be read/written in 8-bit or 1-bit units. The on/off of wait function can be switched with a port alternate-function control register (PAC). Caution
After reset:
When using the wait function, set BCDD to the same potential as EVDD. 00H
7 R/W 6 0 5 0 Address: FFFFF016H 4 Undefined 3 P113 2 P112 1 P111 0 P110
P11
0
P11n 0 1 Output 0 Output 1
Control of output data (in output mode) (n = 0 to 3)
Remark
In input mode:
When the P11 register is read, the pin levels at that time are read. Writing to P11 writes the values to that register. This does not affect the input pins.
In output mode: When the P11 register is read, the P11 register's values are read. Writing to P11 writes the values to that register, and those values are immediately output. Port 11 includes the following alternate functions. Table 14-11. Port 11 Alternate Function Pins
Pin Name Port 11 P110 P111 P112 P113 Alternate Function A1/WAIT A2 A3 A4 I/O I/O PULLNote Yes Remark -
Note Software pull-up function
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(1) Function of P11 pins Port 11 is a 4-bit (total) port for which I/O settings can be controlled in 1-bit units. In output mode, the values set to each bit (bit 0 to bit 3) are output to the port register (P11). When using this port in input mode, the pin statuses can be read by reading the P11 register. Also, the P11 register (output latch) values can be read by reading the P11 register while in output mode (bit 0 to bit 3 only). A pull-up resistor can be connected in 1-bit units for P110 to P113 when specified via pull-up resistor option register 11 (PU11). The on/off of wait function can be switched with a port-alternate function control register (PAC). When using the alternate-function A1 to A4 pins, set the pin functions via the memory address output mode register (MAM). At this time, be sure to clear P11 and PM11 to 0. When a reset is input, the settings are initialized to input mode. Caution A wait function generated by the WAIT pin cannot be used while a separate bus is being used. However, a programmable wait is possible. (2) Control register (a) Port 11 mode register (PM11) PM11 can be read/written in 1-bit or 8-bit units.
After reset:
1FH
7
R/W 6 0 5 0
Address: FFFFF036H 4 1 3 PM113 2 PM112 1 PM111 0 PM110
PM11
0
PM11n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 3)
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(b) Pull-up resistor option register 11 (PU11) PU11 can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 0 5 0
Address: FFFFF096H 4 0 3 PU113 2 PU112 1 PU111 0 PU110
PU11
0
PU11n 0 1 Do not connect Connect
Control of on-chip pull-up resistor connection (n = 0 to 3)
(c) Port alternate-function control register (PAC) PAC can be read/written in 8-bit or 1-bit units.
After reset:
00H
7
R/W 6 0 5 0
Address: FFFFF040H 4 0 3 0 2 0 1 0 <0> WAC
PAC
0
P120 0 1 Wait function off Wait function on
Control of output data (in output mode)
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(3) Block diagram (Port 11) Figure 14-13. Block Diagram of P110 to P113
VDD WRPU
PU11 PU11n P-ch
RD
Selector
Internal bus
WRPORT Output latch (P11n) P110/A1/WAIT P111/A2 P112/A3 P113/A4
WRPM
PM11 PM11n
Remarks 1. PU11: Pull-up resistor option register 11 PM11: Port 11 mode register RD: WR: Port 11 read signal Port 11 write signal
2. n = 0 to 3
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14.3 Setting When Port Pin Is Used as Alternate Function
When a port pin is used as an alternate function, set the port n mode register (PM0 to PM6 and PM9 to PM11) and output latch as shown in Table 14-12 below. Table 14-12. Setting When Port Pin Is Used as Alternate Function (1/4)
Pin Name Alternate Function Function Name P00 NMI I/O Input PMnx Bit of PMn Register PM00 = 1 Pnx Bit of Pn Register Setting not needed for P00 P01 INTP0 Input PM01 = 1 Setting not needed for P01 P02 INTP1 Input PM02 = 1 Setting not needed for P02 P03 INTP2 Input PM03 = 1 Setting not needed for P03 P04 INTP3 Input PM04 = 1 Setting not needed for P04 P05 INTP4 ADTRG P06 INTP5 RTPTRG P07 INTP6 Input Input Input Input Input PM07 = 1 PM06 = 1 PM05 = 1 Setting not needed for P05 Setting not needed for P06 Setting not needed for P07 P10 SI0 Input PM10 = 1 Setting not needed for P10 SDA0Note P11 P12 SO0 SCK0 I/O Output Input PM10 = 0 PM11 = 0 PM12 = 1 P10 = 0 P11 = 0 Setting not needed for P12 Output SCL0Note P13 SI1 RXD0 P14 SO1 TXD0 P15 SCK1 I/O Input Input Output Output Input PM15 = 1 Setting not needed for P15 Output ASCK0 Input PM15 = 0 PM15 = 1 P12 = 0 Setting not needed for P15 PM14 = 0 PM13 = 1 Setting not needed for P13 P14 = 0 PM12 = 0 P12 = 0 PF12 = 1 PF10 = 1 Other Bits (Register)
Note Available only in the Y versions (products with on-chip I C)
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Table 14-12. Setting When Port Pin Is Used as Alternate Function (2/4)
Pin Name Alternate Function Function Name P20 SI2 I/O Input PMnx Bit of PMn Register PM20 = 1 Pnx Bit of Pn Register Setting not needed for P20 SDA1Note P21 P22 SO2 SCK2 I/O Output Input PM20 = 0 PM21 = 0 PM22 = 1 P20 = 0 P21 = 0 Setting not needed for P22 Output SCL1 P23 SI3 RXD1 P24 SO3 TXD1 P25 SCK3
Note
Other Bits (Register)
PF20 = 1
PM22 = 0
P22 = 0 PF22 = 1
I/O Input Input Output Output Input PM25 = 1 Setting not needed for P25 Output PM25 = 0 PM25 = 1 P25 = 0 Setting not needed for P25 PM24 = 0 PM23 = 1 Setting not needed for P23 P24 = 0

ASCK1
Input
P26
TI2
Input
PM26 = 1
Setting not needed for P26
TO2 P27 TI3
Output Input
PM26 = 0 PM27 = 1
P26 = 0 Setting not needed for P27
TO3 P30 TI00
Output Input
PM27 = 0 PM30 = 1
P27 = 0 Setting not needed for P30
P31
TI01
Input
PM31 = 1
Setting not needed for P31
P32
TI10 SI4
Input Input Input
PM32 = 1
Setting not needed for P32
P33
TI11
PM33 = 1
Setting not needed for P33
SO4 P34 TO0 A13 SCK4
Output Output Output Input
PM33 = 0 PM34 = 0
P33 = 0 P34 = 0 Refer to 3.4.6 (2) (MAM)
PM34 = 1
Setting not needed for P34
Output
PM34 = 0
2
P34 = 0
Note Available only in the Y versions (products with on-chip I C)
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Table 14-12. Setting When Port Pin Is Used as Alternate Function (3/4)
Pin Name Alternate Function Function Name P35 TO1 A14 P36 TI4 I/O Output Output Input PM36 = 1 Setting not needed for P36 TO4 A15 P37 TI5 Output Output Input PM37 = 1 Setting not needed for P37 TO5 P40 to P47 AD0 to AD7 Output I/O PM37 = 0 Setting not needed for PM40 to PM47 P50 to P57 AD8 to AD15 I/O Setting not needed for PM50 to PM57 P60 to P65 A16 to A21 Output Setting not needed for PM60 to PM65 P70 to P77 ANI0 to ANI7 Input None P37 = 0 Setting not needed for P40 to P47 Setting not needed for P50 to P57 Setting not needed for P60 to P65 Setting not needed for P70 to P77 P80 to P83 ANI8 to ANI11 Input None Setting not needed for P80 to P83 P90 LBEN WRL P91 UBEN Output Output Output Setting not needed for PM90 Setting not needed for PM91 P92 R/W WRH P93 DSTB RD P94 ASTB Output Output Output Output Output Setting not needed for PM92 Setting not needed for PM93 Setting not needed for PM94 P95 HLDAK Output Setting not needed for PM95 P96 HLDRQ Input Setting not needed for PM96 Setting not needed for P95 = 1 Setting not needed for P96 = 1 Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) P94 = 1 Refer to 3.4.6 (1) (MM) Setting not needed for P90 Setting not needed for P91 Setting not needed for P92 P93 = 1 Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) Refer to 3.4.6 (1) (MM) PM36 = 0 P36 = 0 Refer to 3.4.6 (2) (MAM) PMnx Bit of PMn Register PM35 = 0 Pnx Bit of Pn Register P35 = 0 Other Bits (Register) Refer to 3.4.6 (2) (MAM)
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Table 14-12. Setting When Port Pin Is Used as Alternate Function (4/4)
Pin Name Alternate Function Function Name P100 to P103 RTP0 to RTP3 A5 to A8 KR0 to KR3 I/O Output Output Input PM100 to PM103 = 1 Setting not needed for P100 to P103 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5
Note
PMnx Bit of PMn Register PM100 to PM103 = 0
Pnx Bit of Pn Register P100 to P103 = 0
Other Bits (Register) - Refer to 3.4.6 (2) (MAM) -
Output Output Input Input Output Output Input
PM104 = 0
P104 = 0
- Refer to 3.4.6 (2) (MAM)
PM104 = 1
Setting not needed for P104
- - - Refer to 3.4.6 (2) (MAM)
PM105 = 0
P105 = 0
PM105 = 1
Setting not needed for P105
-
IETX Note P106, P107 RTP6, RTP7 A11, A12 KR6, KR7
Output Output Output Input
PM105 = 0 PM106, PM107 = 0
P105 = 0 P106, P107 = 0
- - Refer to 3.4.6 (2) (MAM)
PM106, PM107 = 1
Setting not needed for P106 and P107
-
P110
A1 WAIT
Output Input
PM110 = 0 PM110 = 1
P110 = 0 Setting not needed for P110
Refer to 3.4.6 (2) (MAM) WAC = 1 (PAC)
P111 to P113
A2 to A4
Output
PM111 to PM113 = 0
P111 to P113 = 0
Refer to 3.4.6 (2) (MAM)
Note Only in the V850/SB2. Caution When changing the output level of port 0 by setting the port function output mode of port 0, the interrupt request flag will be set because port 0 also has an alternate function as an external interrupt request input. Therefore, be sure to set the corresponding interrupt mask flag to 1 before using the output mode. Remark PMnx bit of PMn register and Pnx bit of Pn register n: 0 (x = 0 to 7) n: 5 (x = 0 to 7) n: 10 (x = 0 to 7) n: 1 (x = 0 to 5) n: 6 (x = 0 to 5) n: 11 (x = 0 to 3) n: 2 (x = 0 to 7) n: 7 (x = 0 to 7) n: 3 (x = 0 to 7) n: 8 (x = 0 to 3) n: 4 (x = 0 to 7) n: 9 (x = 0 to 6)
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14.4 Port Function Operation
Port operation differs according to the input/output mode setting, as follows. 14.4.1 Write operation to I/O port (1) In output mode A value is written to the output latch using a transfer instruction, and the contents of the output latch are output from the pin. Once data has been written to the output latch, it is held until the next data is written to the output latch. (2) In input mode A value is written to the output latch using a transfer instruction. However, since the output buffer is OFF, the pin status does not change. Once data has been written to the output latch, it is held until the next data is written to the output latch. Caution A bit manipulation instruction (CLR1, SET1, NOT1) manipulates 1 bit but accesses a port in 8-bit units. If this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 14.4.2 Read operation from I/O port (1) In output mode The output latch contents are read using a transfer instruction. The output latch contents remain unchanged. (2) In input mode The pin status is read using a transfer instruction. The output latch contents remain unchanged.
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RESET FUNCTION
15.1 General
When a low level is input to the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subclock continues. When the input at the RESET pin changes from low level to high level, the reset status is released and the CPU resumes program execution. necessary. An on-chip noise eliminator uses analog delay to prevent noise-related malfunction at the RESET pin. The contents of the various registers should be initialized within the program as
15.2 Pin Operations
During the system reset period, almost all pins are set to high impedance (all pins except for RESET, X2, XT2, REGC, AVREF, VDD, VSS, AVDD, AVSS, BVDD, BVSS, EVDD, EVSS, and VPP/IC). Accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor for each pin. If such a resistor is not attached, these pins will be set to high impedance, which could damage the data in memory devices. Likewise, make sure the pins are handled so as to prevent a similar effect at the signal outputs of on-chip peripheral I/O functions and output ports. Figure 15-1. System Reset Timing
Hi-Z X1 Oscillation stabilization time
RESET
Analog delay Analog delay Analog delay
Internal system reset signal Eliminated as noise Reset is acknowledged Reset is released
20.2 ms (@ 20 MHz operation)
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REGULATOR
16.1 Outline
The V850/SB1 and V850/SB2 incorporate a regulator to realize a 5 V single power supply, low power consumption, and to reduce noise. This regulator supplies a voltage obtained by stepping down the VDD power supply voltage to the oscillation blocks and on-chip logic circuits (excluding the A/D converter and output buffers). The regulator output voltage is set to 3.3 V (V850/SB1, H versions of V850/SB2) or 3.0 V (A and B versions of V850/SB2). Refer to 2.4 I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins for the power supply corresponding to each pin. Figure 16-1. Regulator EVDD-system I/O buffer
3.0 V to 5.5 V AVDD EVDD On-chip digital circuit 3.3 V: V850/SB1, H versions of V850/SB2 3.0 V: A, B versions of V850/SB2 A/D converter 4.5 V to 5.5 V
Flash memory
Main/Sub oscillators
3.0 V to 5.5 V
BVDD
Regulator
REGC
VDD VPP
Bidirectional level shifter
BVDD-system I/O buffer
16.2 Operation
The regulators of the V850/SB1 and V850/SB2 operate in every mode (STOP, IDLE, HALT). For stabilization of regulator outputs, connect an electrolytic capacitor of about 1 F to the REGC pin.
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ROM CORRECTION FUNCTION
17.1 General
The ROM correction function provided in the V850/SB1 and V850/SB2 is a function that replaces part of a program in the mask ROM with a program in the internal RAM. First, the instruction of the address where the program replacement should start is replaced with the JMP r0 instruction and the program is instructed to jump to 00000000H. The correction request register (CORRQ) is then checked. At this time, if the CORRQn flag is set to 1, program control shifts to the internal RAM after jumping to the internal ROM area by an instruction such as a jump instruction. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction function. Up to four correction addresses can be specified. Cautions 1. The ROM correction function cannot be used for the data in the internal ROM; it can only be used for instruction codes. If ROM correction is carried out on data, that data will replace the instruction code of the JMP r0 instruction. 2. ROM correction for the instructions that access the registers CORCN, CORRQ, or CORAD0 to CORAD3 is prohibited. Figure 17-1. Block Diagram of ROM Correction
Instruction address bus
Correction address register n (CORADn)
JMP r0 instruction generation Comparator
ROM (1 MB area)
Correction control register (CORCNn bit)
S R
Q
Instruction replacement
Instruction data bus
0 clear instruction Remark n = 0 to 3
Correction request register (CORRQn bit)
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17.2 ROM Correction Peripheral I/O Registers
(1) Correction control register (CORCN) CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction when the correction address matches the fetch address (n = 0 to 3). Whether match detection by a comparator is enabled or disabled can be set for each channel. CORCN can be set by a 1-bit or 8-bit memory manipulation instruction.
After reset: 00H 7 CORCN 0 R/W 6 0 Address: FFFFF36CH 5 0 4 0 <3> COREN3 <2> COREN2 <1> COREN1 <0> COREN0
CORENn 0 1
CORADn register and fetch address match detection control Match detection disabled (not detected) Match detection enabled (detected)
Remark
n = 0 to 3
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(2) Correction request register (CORRQ) CORRQ saves the channel in which ROM correction occurred. The JMP r0 instruction makes the program jump to 00000000H after the correction address matches the fetch address. At this time, the program can judge the following cases by reading CORRQ. * Reset input: * ROM correction generation: CORRQ = 00H CORRQn bit = 1 (n = 0 to 3)
* Branch to 00000000H by user program: CORRQ = 00H
After reset: 00H 7 CORRQ 0 R/W 6 0 Address: FFFFF36EH 5 0 4 0 <3> CORRQ3 <2> CORRQ2 <1> CORRQ1 <0> CORRQ0
CORRQn 0 1
Channel n ROM correction request flag No ROM correction request occurred. ROM correction request occurred.
Remark
n = 0 to 3
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(3) Correction address registers 0 to 3 (CORAD0 to CORAD3) CORADn sets the start address of an instruction to be corrected (correction address) in the ROM. Up to four points of the program can be corrected at once since the V850/SB1 and V850/SB2 have four correction address registers (CORADn) (n = 0 to 3). Since the ROM capacity varies depending on the product, set the correction address within following ranges.
PD703031A, 703031AY, 703031B, 703031BY,
703034A, 703034AY, 703034B, 703034BY (128 KB): 00000000H to 0001FFFEH
PD703033A, 703033AY, 703033B, 703033BY,
703035A, 703035AY, 703035B, 703035BY (256 KB): 00000000H to 0003FFFEH
PD703030B, 703030BY, 703036H, 703036HY (384 KB): 00000000H to 0005FFFEH PD703032A, 703032AY, 703032B, 703032BY,
703037A, 703037AY, 703037H, 703037HY (512 KB): 00000000H to 0007FFFEH Bits 0 and 20 to 31 should be fixed to 0.
After reset: 00000000H R/W Address: CORAD0: FFFFF370H CORAD1: FFFFF374H
31 20 19
CORAD2: FFFFF378H CORAD3: FFFFF37CH
1 0
CORADn Fixed to 0 (n = 0 to 3) Correction address
0
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Figure 17-2. ROM Correction Operation and Program Flow
START (reset vector)
CORRQn = 0? Yes
Microcontroller initialization
No
Clears CORRQn flag. JMP channel n correct code address
The address of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM. Executes correction program code
Data for ROM correction setting is loaded from an external memory into the internal RAM to initialize ROM correction function. If there is a correction code, it is loaded in the internal RAM.
Executes internal ROM program
Jumps to internal ROM
Correction address?
No
Yes CORENn = 1?
Yes
No
CORRQn flag set
JMP r0
: Executed by a program stored in the internal ROM : Executed by a program stored in the internal RAM : Executed by the ROM correction function
Caution Check the ROM correction generation from the vector table with a high interrupt level when executing ROM correction during a vector interrupt routine. If an interrupt conflicts with ROM correction, processing is branched to an interrupt vector, where, if ROM correction is being re-executed, CORRQn is set (1) again and multiple CORRQn flags are set (1). The channel for which ROM correction is to be executed is determined by the interrupt level. Remark n = 0 to 3
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The following products are the flash memory versions of the V850/SB1 and V850/SB2. Caution The flash memory versions and mask ROM versions differ in noise immunity and noise radiation. If replacing a flash memory version with a mask ROM version when changing from experimental production to mass production, make a thorough evaluation by using the CS model (not ES model) of the mask ROM version. (1) V850/SB1
PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY: PD70F3030B, 70F3030BY: PD70F3032A, 70F3032AY, 70F3032B, 70F3032BY:
(2) V850/SB2
256 KB flash memory versions 384 KB flash memory versions 512 KB flash memory versions 256 KB flash memory versions 384 KB flash memory versions 512 KB flash memory versions
PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY: PD70F3036H, 70F3036HY: PD70F3037A, 70F3037AY, 70F3037H,70F3037HY:
In the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock, the same as in the mask ROM version. Writing to flash memory can be performed with the memory mounted on the target system (on board). dedicated flash programmer is connected to the target system to perform writing. The following can be considered as the development environment and applications using flash memory. * Software can be altered after the V850/SB1 or V850/SB2 is solder-mounted on the target system. * Small scale production of various models is made easier by differentiating software. * Data adjustment in starting mass production is made easier. A
18.1 Features
* 4-byte/1-clock access (in instruction fetch access) * All area one-shot erase/area unit erase * Communication via serial interface with the dedicated flash programmer * Erase/write voltage: VPP = 7.8 V * On-board programming * Flash memory programming in area (128 KB) units by self-writing
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18.1.1 Erase unit The erase unit differs depending on the product. (1) V850/SB1 (PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY), V850/SB2 (PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY) The erase units for 256 KB flash memory versions are shown below. (a) All area one-shot erase The area of xx000000H to xx03FFFFH can be erased in one shot. (b) Area erase Erasure can be performed in area units (there are two 128 KB unit areas). Area 0: Area 1: The area of xx000000H to xx01FFFFH (128 KB) is erased The area of xx020000H to xx03FFFFH (128 KB) is erased
(2) V850/SB1 (PD70F3033B, 70F3033BY), V850/SB2 (PD70F3036H, 70F3036HY) The erase units for 384 KB flash memory versions are shown below. (a) All area one-shot erase The area of xx000000H to xx05FFFFH can be erased in one shot. (b) Area erase Erasure can be performed in area units (there are three 128 KB unit areas). Area 0: The area of xx000000H to xx01FFFFH (128 KB) is erased Area 1: The area of xx020000H to xx03FFFFH (128 KB) is erased Area 2: The area of xx040000H to xx05FFFFH (128 KB) is erased (3) V850/SB1 (PD70F3032A, 70F3032AY, 70F3032B, 70F3032BY), V850/SB2 (PD70F3037A, 70F3037AY, 70F3037H, 70F3037HY) The erase units for 512 KB flash memory versions are shown below. (a) All area one-shot erase The area of xx000000H to xx07FFFFH can be erased in one shot. (b) Area erase Erasure can be performed in area units (there are four 128 KB unit areas). Area 0: Area 1: Area 2: Area 3: The area of xx000000H to xx01FFFFH (128 KB) is erased The area of xx020000H to xx03FFFFH (128 KB) is erased The area of xx040000H to xx05FFFFH (128 KB) is erased The area of xx060000H to xx07FFFFH (128 KB) is erased
18.1.2 Write/read time The write/read time is shown below. Write time: 50 s/byte Read time: 50 ns (cycle time)
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18.2 Writing with Flash Programmer
Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850/SB1 or V850/SB2 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) Off-board programming Writing to a flash memory are performed by the dedicated program adapter (FA Series), etc., before mounting the V850/SB1 or V850/SB2 on the target system. Remark FA Series is a product of Naito Densei Machida Mfg. Co., Ltd.
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Figure 18-1. Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)
D VD ND G
72 71
56 55
86
PD70F3030B, PD70F3030BY, PD70F3033A, PD70F3033AY, PD70F3033B, PD70F3033BY, PD70F3035A, PD70F3035AY, PD70F3035B, PD70F3035BY, PD70F3036H, PD70F3036HY
Note
38 37 36 35 34
94 95 96
32
Connect to GND. Connect to VDD.
31
99 1
D VD ND G
6
7
18
D N G DD V
SI
SO
SCK
X1
X2 /RESET VPP RESERVE/HS
Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion). An example of the oscillator is shown below.
REGC X1 X2
1 F
Remarks 1. Handle the pins not described above in accordance with the recommended connection of unused pins (refer to 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 100-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using CSI supporting handshake.
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Table 18-1. Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU)
Flash Programmer (PG-FP3) Signal Name SI/RXD SO/TXD SCK CLK /RESET VPP HS I/O Input Output Output - Output Output Input Pin Function Receive signal Transmit signal Transfer clock Unused Reset signal Writing voltage Handshake signal of CSI0 + HS communication VDD - VDD voltage generation/power supply monitoring BVDD AVDD GND - Ground VSS EVSS BVSS AVSS P00/NMI 5 71 37 7 56 72 86 BVDD AVDD VSS EVSS BVSS AVSS P00/NMI 5 71 37 7 56 72 86 BVDD AVDD VSS EVSS BVSS AVSS P00/NMI 5 71 37 7 56 72 86 VDD EVDD 38 6 VDD EVDD 38 6 VDD EVDD 38 6 When Using CSI0 + HS Pin Name P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP 95 94 96 Unnecessary 31 18 Pin No. When Using CSI0 Pin Name P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP Unnecessary 95 94 96 Unnecessary 31 18 Unnecessary Pin No. When Using UART0 Pin Name P14/SO1/TXD0 P13/SO0/RXD0 Unnecessary Unnecessary RESET IC/VPP Unnecessary 97 98 Unnecessary Unnecessary 31 18 Unnecessary Pin No.
P15/SCK4/ASCK0 99
Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion).
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Figure 18-2. Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA)
D VD ND G
75 74
59 58
89
PD70F3030B, PD70F3030BY, PD70F3032A, PD70F3032AY, PD70F3032B, PD70F3032BY, PD70F3033A, PD70F3033AY, PD70F3033B, PD70F3033BY
PD70F3035A, PD70F3035AY, PD70F3035B, PD70F3035BY, PD70F3036H, PD70F3036HY PD70F3037A, PD70F3037AY, PD70F3037H, PD70F3037HY
41 40 39 38 37 Note 35
97 98 99 1
D VD ND G
Connect to GND. Connect to VDD.
34
2
9
10
21
D N G DD V
SI
SO
SCK
X1
X2 /RESET VPP RESERVE/HS
Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply a clock by creating an oscillator on the flash writing adapter (broken-line portion). An example of the oscillator is shown below.
REGC X1 X2
1 F
Remarks 1. Handle the pins not described above in accordance with the recommended connection of unused pins (refer to 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 100-pin plastic QFP package. 3. This diagram shows the wiring when using CSI supporting handshake.
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Table 18-2. Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA)
Flash Programmer (PG-FP3) Signal Name SI/RXD SO/TXD SCK CLK /RESET VPP HS I/O Input Output Output - Output Output Input Pin Function Receive signal Transmit signal Transfer clock Unused Reset signal Writing voltage Handshake signal of CSI0 + HS communication VDD - VDD voltage generation/power supply monitoring BVDD AVDD GND - Ground VSS EVSS BVSS AVSS P00/NMI 8 74 40 10 59 75 89 BVDD AVDD VSS EVSS BVSS AVSS P00/NMI 8 74 40 10 59 75 89 BVDD AVDD VSS EVSS BVSS AVSS P00/NMI 8 74 40 10 59 75 89 VDD EVDD 41 9 VDD EVDD 41 9 VDD EVDD 41 9 When Using CSI0 + HS Pin Name P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP 98 97 99 Unnecessary 34 21 Pin No. When Using CSI0 Pin Name P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP Unnecessary 98 97 99 Unnecessary 34 21 Unnecessary Pin No. When Using UART0 Pin Name P14/SO1/TXD0 P13/SO0/RXD0 Unnecessary Unnecessary RESET IC/VPP Unnecessary Pin No. 100 1 Unnecessary Unnecessary 34 21 Unnecessary
P15/SCK4/ASCK0 2
Note The V850/SB1 and V850/SB2 cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion).
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18.3 Programming Environment
The following shows the environment required for writing programs to the flash memory of the V850/SB1 and V850/SB2. Figure 18-3. Environment Required for Writing Programs to Flash Memory
RS-232C
VPP VDD VSS
RESET
UART/CSI
Host machine
Dedicated flash programmer
V850/SB1, V850/SB2
A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850/SB1 or V850/SB2 to perform writing, erasing, etc. A dedicated program adapter (FA Series) required for off-board writing.
18.4 Communication Mode
The communication between the dedicated flash programmer and the V850/SB1 or V850/SB2 is performed by serial communication using UART0 or CSI0 of the V850/SB1, V850/SB2 . (1) UART0 Transfer rate: 4800 to 76800 bps Figure 18-4. Communication with Dedicated Flash Programmer (UART0)
VPP VDD GND RESET Dedicated flash programmer RXD TXD VPP VDD VSS RESET TXD0 RXD0
V850/SB1, V850/SB2
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(2) CSI0 Serial clock: Up to 1 MHz (MSB first) Figure 18-5. Communication with Dedicated Flash Programmer (CSI0)
VPP VDD GND RESET Dedicated flash programmer SI SO SCK VPP VDD VSS RESET SO0 SI0 SCK0
V850/SB1, V850/SB2
(3) CSI0 + HS Serial clock: Up to 1 MHz (MSB first) Figure 18-6. Communication with Dedicated Flash Programmer (CSI0 + HS)
VPP VDD GND RESET Dedicated flash programmer SI SO SCK HS VPP VDD VSS RESET SO0 SI0 SCK0 P15
V850/SB1, V850/SB2
The dedicated flash programmer outputs the transfer clock, and the V850/SB1 and V850/SB2 operate as slaves. When the PG-FP3 is used as the dedicated flash programmer, it generates the following signals to the V850/SB1 or V850/SB2 . For details, refer to the PG-FP3 User's Manual.
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Table 18-3. Signal Generation of Dedicated Flash Programmer (PG-FP3)
PG-FP3 V850/SB1, V850/SB2 Pin Function Writing voltage VDD voltage generation/ voltage monitoring - Output Ground Clock output to V850/SB1, V850/SB2 Reset signal Receive signal Transmit signal Transfer clock Pin Name VPP VDD Connection Handling CSI0 + HS
Signal Name VPP VDD
I/O Output I/O
CSI0
UART0
GND CLK
Note
VSS X1 x x x
RESET SI/RxD SO/TxD SCK HS
Output Input Output Output Input
RESET SO0/TxD0 SI0/RxD0 SCK0 x x x
Handshake signal of CSI0 + HS P15
Note Supply clocks on the target board. Remark x: : Always connected : Does not need to be connected, if generated on the target board Does not need to be connected
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18.5 Pin Connection
When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. When switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset. Therefore, all the ports enter the output high-impedance status, so that pin handling is required when the external device does not acknowledge the output high-impedance status. 18.5.1 VPP pin In the normal operation mode, 0 V is input to the VPP pin. In the flash memory programming mode, a 7.8 V write voltage is supplied to the VPP pin. The following shows an example of the connection of the VPP pin. Figure 18-7. VPP Pin Connection Example V850/SB1, V850/SB2
Dedicated flash programmer connection pin
VPP
Pull-down resistor (RVPP)
18.5.2 Serial interface pin The following shows the pins used by each serial interface. Table 18-4. Pins Used in Serial Interfaces
Serial Interface CSI0 CSI0 + HS UART0 Pins Used SO0, SI0, SCK0 SO0, SI0, SCK0, P15 TXD0, RXD0
When connecting a dedicated flash programmer to a serial interface pin that is connected to other devices onboard, care should be taken to avoid conflict of signals and malfunction of the other devices, etc.
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(1) Conflict of signals When connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 18-8. Conflict of Signals (Serial Interface Input Pin) V850/SB1, V850/SB2
Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pins
In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side.
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(2) Malfunction of other device When connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. Figure 18-9. Malfunction of Other Device V850/SB1, V850/SB2
Dedicated flash programmer connection pin Pin Other device Input pin
In the flash memory programming mode, if the signal the V850/SB1 or V850/SB2 outputs affects the other device, isolate the signal on the other device side.
V850/SB1, V850/SB2
Dedicated flash programmer connection pin Pin Other device Input pin
In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
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18.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin that is connected to the reset signal generator on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 18-10. Conflict of Signals (RESET Pin) V850/SB1, V850/SB2
Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin
In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side.
18.5.4 Port pins (including NMI) When the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer enter the output high-impedance status. If problems such as disabling output highimpedance status should occur in the external devices connected to the port, connect them to VDD or VSS via resistors. 18.5.5 Other signal pins Connect X1, X2, XT2, and AVREF to the same status as that in the normal operation mode. 18.5.6 Power supply Supply the power supply as follows: VDD = EVDD Supply the same power supply (AVDD, AVSS, BVDD, BVSS) as when in normal operation mode.
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18.6 Programming Method
18.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 18-11. Procedure for Manipulating Flash Memory
Start
Supplies RESET pulse
Switch to flash memory programming mode
Select communication system
Manipulate flash memory
End? Yes End
No
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18.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850/SB1 or V850/SB2 in the flash memory programming mode. When switching modes, set the VPP pin before releasing reset. When performing on-board writing, change modes using a jumper, etc. Figure 18-12. Flash Memory Programming Mode
Flash memory programming mode
7.8 V VPP 3 V 0V RESET
1
2
...
n
VPP 0V 7.8 V
Operation Mode Normal operation mode Flash memory programming mode
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18.6.3 Selection of communication mode In the V850/SB1 and V850/SB2, the communication mode is selected by inputting pulses (16 pulses max.) to the VPP pin after switching to the flash memory programming mode. The VPP pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Table 18-5. List of Communication Modes
VPP Pulse 0 3 8 Others Communication Mode CSI0 CSI0 + HS UART0 RFU Remarks V850/SB1 and V850/SB2 perform slave operation, MSB first V850/SB1 and V850/SB2 perform slave operation, MSB first Communication rate: 9600 bps (at reset), LSB first Setting prohibited
Caution
When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the VPP pulse.
18.6.4 Communication command The V850/SB1 and V850/SB2 communicate with the dedicated flash programmer by means of commands. The command sent from the dedicated flash programmer to the V850/SB1 or V850/SB2 is called a "command". The response signal sent from the V850/SB1 or V850/SB2 to the dedicated flash programmer is called a "response command". Figure 18-13. Communication Command
Command Response command Dedicated flash programmer
V850/SB1, V850/SB2
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The following shows the commands for flash memory control of the V850/SB1 and V850/SB2. processing corresponding to the commands. Table 18-6. Flash Memory Control Command
Category Verify Command Name One-short verify command Function
All of these
commands are issued from the dedicated flash programmer, and the V850/SB1 and V850/SB2 perform the various
Compares the contents of the entire memory and the input data. Compares the contents of the specified area and the input data Erases the specified area. Writes back the erased contents. Checks the erase state of the entire memory. Checks the erase state of the specified area. Writes data by the specification of the write address and the number of bytes to be written, and executes a verify check. Writes data from the address following the highspeed write command executed immediately before, and executes a verify check. Acquires the status of operations. Sets the oscillation frequency.
Area verify command
Erase
Area erase command Writeback command
Blank check
One-shot blank check command Area blank check command
Data write
High-speed write command
Continuous write command
System setting and control
Status read out command Oscillating frequency setting command Erasing time setting command Writing time setting command Writeback time setting command Baud rate setting command Silicon signature command Reset command
Sets the erasing time of one-shot erase. Sets the writing time of data write. Sets the writeback time. Sets the baud rate when using UART. Reads outs the silicon signature information. Escapes from each state.
The V850/SB1 and V850/SB2 send back response commands to the commands issued from the dedicated flash programmer. The following shows the response commands the V850/SB1 and V850/SB2 send out. Table 18-7. Response Command
Response Command Name ACK (acknowledge) NAK (not acknowledge) Function Acknowledges command/data, etc. Acknowledges illegal command/data, etc.
18.6.5 Resources used The resources used in the flash memory programming mode are all the FFE000H to FFE7FFH area of the internal RAM and all the registers. The FFE800H to FFEFFFH area of the internal RAM retains data as long as the power is on. The registers that are initialized by reset are changed to the default values.
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IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To implement IEBus with the V850/SB2, an external IEBus driver and receiver are necessary because they are not provided. The internal IEBus controller of the V850/SB2 is of negative logic.
19.1 IEBus Controller Function
19.1.1 Communication protocol of IEBus The communication protocol of the IEBus is as follows: (1) Multi-task mode All the units connected to the IEBus can transfer data to the other units. (2) Broadcasting communication function Communication between one unit and plural units can be performed as follows: * Group-unit broadcasting communication: Broadcasting communication to group units * All-unit broadcasting communication: (3) Effective transfer rate The effective transfer rate is in mode 1 (the V850/SB2 does not support modes 0 and 2 for the effective transfer rate). * Mode 1: Approx. 17 Kbps Caution Different modes must not be mixed on one IEBus. Broadcasting communication to all units.
(4) Communication mode Data transfer is executed in half-duplex asynchronous communication mode. (5) Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) The priority of the IEBus is as follows: <1> Broadcasting communication takes precedence over individual communication (communication from one unit to another). <2> The lower master address takes precedence. (6) Communication scale The communication scale of IEBus is as follows: * Number of units: * Cable length: Caution 50 MAX. 150 m MAX. (when twisted pair cable is used)
The communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the IEBus driver/receiver and IEBus.
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19.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus. Because only one unit is granted the bus mastership as a result of arbitration, the priority conditions of the bus are predetermined as follows: Caution The bus mastership is released if communication is aborted. (1) Priority by communication type Broadcasting communication (communication from one unit to plural units) takes precedence over normal communication (communication from one unit to another). (2) Priority by master address If the communication type is the same, communication with the lower master address takes precedence. A master address consists of 12 bits, with unit 000H having the highest priority and unit FFFH having the lowest priority. 19.1.3 Communication mode Although the IEBus has three communication modes each having a different transfer rate, the V850/SB2 supports only communication mode 1. The transfer rate and the maximum number of transfer bytes in one communication frame in communication mode 1 are as shown in Table 19-1. Table 19-1. Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1
Communication Mode 1 Maximum Number of Transfer Bytes (Bytes/Frame) 32 Effective Transfer Rate (Kbps)Note Approx. 17
Note The effective transfer rate when the maximum number of transfer bytes is transmitted. Select the communication mode (mode 1) for each unit connected to the IEBus before starting communication. If the communication mode of the master unit and that of the partner unit (slave unit) are not the same, communication is not correctly executed.
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19.1.4 Communication address With the IEBus, each unit is assigned a specific 12-bit address. This communication address consists of the following identification numbers: * Higher 4 bits: Group number (number to identify the group to which each unit belongs) * Lower 8 bits: Unit number (number to identify each unit in a group) 19.1.5 Broadcasting communication Normally, transmission or reception is performed between the master unit and its partner slave unit on a one-toone basis. During broadcasting communication, however, two or more slave units exist and the master unit executes transmission to these slave units. Because plural slave units exist, the slave units do not return an acknowledge signal during communication. Whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit (for this bit, refer to 19.1.6 (2) Broadcasting bit). Broadcasting communication is classified into two types: group-unit broadcasting communication and all-unit broadcasting communication. Group-unit broadcasting and all-unit broadcasting are identified by the value of the slave address (for the slave address, refer to 19.1.6 (4) Slave address field). (1) Group-unit broadcasting communication Broadcasting communication is performed to the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) All-unit broadcasting communication Broadcasting communication is performed to all the units, regardless of the value of the group number.
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19.1.6 Transfer format of IEBus Figure 19-1 shows the transfer signal format of the IEBus. Figure 19-1. IEBus Transfer Signal Format
Master address field Slave address field Telegraph Control field length field
Header
Data field
Frame format
Broad- Master Slave Start Control casting address P address P A PA bit bit bit bit bit
TeleData graph PA length P A bit bit
Data PA bit
Remarks 1. P: Parity bit, A: ACK/NACK bit 2. The master station ignores the acknowledge bit during broadcasting communication. (1) Start bit The start bit is a signal that informs the other units of the start of data transfer. The unit that is to start data transfer outputs a high-level signal (start bit) from the IETX pin for a specific time, and then starts outputting the broadcasting bit. If another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. When the output of the start bit by the other unit is complete, the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit. The units other than the one that has started communication detect this start bit, and enter the reception status. (2) Broadcasting bit This bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcasting communication) as the other party of communication. When the broadcasting bit is 0, it indicates broadcasting communication; when it is 1, individual communication is indicated. Broadcasting communication is classified into two types: group-unit communication and all-unit communication. These communication types are identified by the value of the slave address (for the slave address, refer to 19.1.6 (4) Slave address field). Because two or more slave units exist in the case of broadcasting communication, the acknowledge bit in each field subsequent to the master address field is not returned. If two or more units start transmitting a communication frame at the same time, broadcasting communication takes precedence over individual communication, and wins in arbitration. If one station occupies the bus as the master, the value set to the broadcasting request bit (ALLRQ) of the IEBus control register (BCR) is output.
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(3) Master address field The master address field is output by the master to inform a slave of the master's address. The configuration of the master address field is as shown in Figure 19-2. If two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration. The master address field compares the data it outputs with the data on the bus each time it has output one bit. If the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. As a result, the master stops transmission and enters the reception status. Because the IEBus is configured of wired AND, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. After a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. Next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. If one unit occupies the bus as the master, the address set by the IEBus unit address register (UAR) is output. Figure 19-2. Master Address Field
Master address field Master address (12 bits) MSB LSB Parity
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(4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 19-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. Next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. When the master has detected the acknowledge signal, it starts outputting the control field. During broadcasting communication, however, the master does not detect the acknowledge bit but starts outputting the control field. The slave unit outputs the acknowledge signal if its slave address matches and if the slave detects that the parities of both the master address and slave address are even. The slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. At this time, the master unit is in the standby (monitor) status, and communication ends. During broadcasting communication, the slave address is used to identify group-unit broadcasting or all-unit broadcasting, as follows: If slave address is FFFH: All-unit broadcasting communication
If slave address is other than FFFH: Group-unit broadcasting communication Remark The group No. during group-unit broadcasting communication is the value of the higher 4 bits of the slave address. If one unit occupies the bus as the master, the address set by the slave address register (SAR) is output. Figure 19-3. Slave Address Field
Slave address field Slave address (12 bits) Group No. MSB Unit No. LSB Parity ACK
(5) Control field The master outputs the operation it requires the slave to perform, by using this field. The configuration of the control field is as shown in Figure 19-4. If the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. If the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. The master unit starts outputting the telegraph field after confirming the acknowledge signal. If the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. During broadcasting communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. Table 19-2 shows the contents of the control bits.
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Table 19-2. Contents of Control Bits
Bit 3Note 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reads slave status Undefined Undefined Reads data and locksNote 2 Reads lock address (lower 8 bits)Note 3 Reads lock address (higher 4 bits)Note 3 Reads slave status and unlocksNote 2 Reads data Undefined Undefined Writes command and locksNote 2 Writes data and locksNote 2 Undefined Undefined Writes command Writes data Function
Notes 1.
The telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (MSB). If bit 3 is `1': Transfer from master unit to slave unit If bit 3 is `0': Transfer from slave unit to master unit
2. 3.
This is a control bit that specifies locking or unlocking (refer to 19.1.7 (4) Locking and unlocking). The lock address is transferred in 1-byte (8-bit) units and is configured as follows:
MSB Control bit: 4H Lower 8 bits LSB
Control bit: 5H
Undefined
Higher 4 bits
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If the control bit received from the master unit is not as shown in Table 19-3, the unit locked by the master unit rejects acknowledging the control bit, and does not output the acknowledge bit. Table 19-3. Control Field for Locked Slave Unit
Bit 3Note 1 0 0 0 Bit 2 0 1 0 Bit 1 0 0 0 Bit 0 0 0 1 Reads slave status Reads lock address (lower 8 bits) Reads lock address (higher 4 bits) Function
Moreover, units for which lock is not set by the master unit reject acknowledgment and do not output an acknowledge bit when the control data shown in Table 19-4 is acknowledged. Table 19-4. Control Field for Unlocked Slave Unit
Bit 3 0 0 Bit 2 1 1 Bit 1 0 0 Bit 0 0 1 Function Lock address read (lower 8 bits) Lock address read (higher 4 bits)
If one unit occupies the bus as the master, the value set to the IEBus control register (CDR) is output. Figure 19-4. Control Field
Control field Control bit (4 bits) MSB LSB Parity ACK
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Table 19-5. Acknowledge Signal Output Condition of Control Field (a) If received control data is AH, BH, EH, or FH
Communication Type (ALL TRANS) Independent communication = 0 Broadcasting communication = 1 0 Communication Target (SLVRQ) Slave Specification = 1 No Specification = 0 Lock Status (LOCK) Lock = 1 Unlock = 0 Master Unit Identification (Match with PAR) Lock Request Unit = 1 Other = 0 don't care 1 Other than above x CHAPTER 19 Slave Transmission Enable (ENSLVTX) Slave Reception Enable (ENSLVRX) Received Control Data AH BH EH FH
1
0 1
don't care
1
(b) If received control data is 0H, 3H, 4H, 5H, 6H, or 7H
Communication Type (ALL TRANS) Independent communication = 0 Broadcasting communication = 1 0 Communication Target (SLVRQ) Slave Specification = 1 No Specification = 0 Lock Status (LOCK) Lock = 1 Unlock = 0 Master Unit Identification (Match with PAR) Lock Request Unit = 1 Other = 0 don't care Slave Transmission Enable (ENSLVTX) Slave Reception Enable (ENSLVRX) Received Control Data 0H 3H 4H 5H 6H 7H
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1
0
0 1
don't care
x x x
x x
x x x
x x x
1 1
don't care
1 Other than above x
Caution If the received control data is other than the data shown in Table 19-5, x (ACK is not returned) is unconditionally assumed. Remarks 1. : ACK is returned. x: ACK is not returned. 2. ENSLVTX: Bit 4 of the IEBus unit control register (BCR) ENSLVRX: Bit 3 of the IEBus unit control register (BCR) LOCK: SLVRQ: Bit 2 of the IEBus unit status register (USR) Bit 6 of the IEBus unit status register (USR) IEBus partner address register
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(6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 19-5. Table 19-6 shows the relationship between the telegraph length bit and the number of transmit data. Figure 19-5. Telegraph Length Field
Telegraph length field Telegraph length bit (8 bits) MSB LSB Parity ACK
Table 19-6. Contents of Telegraph Length Bit
Telegraph Length Bit (Hex) 01H 02H | FFH 00H Number of Transmit Data Bytes 1 byte 2 bytes | 255 bytes 256 bytes
The operation of the telegraph length field differs depending on whether the master transmits data (when control bit 3 is 1) or receives data (when control bit 3 is 0). (a) When master transmits data The telegraph length bit and parity bit are output by the master unit and the synchronization signals of bits are output by the master unit. When the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. During broadcasting communication, however, the slave unit does not output the acknowledge signal. If the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. At this time, the master unit also returns to the standby status, and communication ends. (b) When master receives data The telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. acknowledge signal. If the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby status. At this time, the slave unit also returns to the standby status, and communication ends. If the master unit detects that the parity bit is even, it outputs the
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(7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 19-6. Data Field
Data field (number specified by telegraph length field) One data Control bit (8 bits) MSB LSB Parity ACK Parity ACK
Following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. Use broadcasting communication only for when the master unit transmits data. At this time, the acknowledge bit is ignored.
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The operation differs as follows depending on whether the master transmits or receives data. (a) When master transmits data When the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. If the parity is even and the receive data is not stored in the IEBus data register (DR) when the slave unit has received the data bit and parity bit, the slave unit outputs an acknowledge signal. If the parity is odd or if the receive data is stored in the IEBus data register (DR), the slave unit rejects receiving the data, and does not output the acknowledge signal. If the slave unit does not output the acknowledge signal, the master unit transmits the same data again. This operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. If the data has continuation and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. During broadcasting communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. If the parity is odd or the DR register is storing receive data after the slave unit has received the data bit and parity bit during broadcasting communication, the slave unit judges that reception has not been performed correctly, and stops reception. (b) When master receives data When the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. The master unit reads the data and parity bits output by the slave unit, and checks the parity. If the parity is odd, or if the DR register is storing a receive data, the master unit rejects accepting the data, and does not output the acknowledge signal. If the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. If the parity is even and the DR register is not storing a receive data, the master unit accepts the data and returns the acknowledge signal. If the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. Caution Do not operate master reception in broadcasting communication, because the slave unit cannot be defined and data transfer cannot be performed correctly. (8) Parity bit The parity bit is used to check to see if the transmit data has no error. The parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. The parity is an even parity. If the number of bits in data that are `1' is odd, the parity bit is `1'. If the number of bits in the data that are `1' is even, the parity bit is `0'.
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(9) Acknowledge bit During normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. * End of slave address field * End of control field * End of telegraph length field * End of data field The definition of the acknowledge bit is as follows: * 0: Indicates that the transmit data is recognized (ACK). * 1: Indicates that the transmit data is not recognized (NACK). During broadcasting communication, however, the contents of the acknowledge bit are ignored. (a) Last acknowledge bit of slave field The last acknowledge bit of the slave field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the master address bit or slave address bit is incorrect * If a timing error (error in bit format) occurs * If a slave unit does not exist (b) Last acknowledge bit of control field The last acknowledge bit of the control field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the control bit is incorrect * If control bit 3 is `1' (write operation) when the slave reception enable flag (ENSLVRX) is not set (1) (ENSLVTX) is not set (1) locking is set * If the control bit indicates reading of lock addresses (4H, 5H) even when locking is not set * If a timing error occurs * If the control bit is undefined Note Refer to 19.3.2 (1) IEBus control register (BCR). Cautions 1. Even when the slave transmission enable flag (ENSLVTX) is not set (1), ACK is always returned if slave status request control data is received. 2. Even when slave reception enable flag (ENSLVRX) is not set (1), NACK is always returned by the acknowledge bit in the control field if data/command writing control data is acknowledged. Slave reception can be disabled (communication stopped) by ENSLVRX flag only in the case of independent communication. In the case of broadcasting communication, communication is maintained and the data request interrupt (INTIE1) or IEBus end interrupt (INTIE2) is generated.
Note Note
* If the control bit indicates reading of data (3H or 7H) when the slave transmission enable flag * If a unit other than that has set locking requests 3H, 6H, 7H, AH, BH, EH, or FH of the control bit when
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(c) Last acknowledge bit of telegraph length field The last acknowledge bit of the telegraph length field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the telegraph length bit is incorrect * If a timing error occurs (d) Last acknowledge bit of data field The last acknowledge bit of the data field serves as NACK in any of the following cases, and transmission is stopped. * If the parity of the data bit is incorrect
Note
* If a timing error occurs after the preceding acknowledge bit has been transmitted * If the receive data is stored in the IEBus data register (DR) and no more data can be received
Note
Note In this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. reception side and reception stops. 19.1.7 Transfer data (1) Slave status The master unit can learn why the slave unit did not return the acknowledge bit (ACK) by reading the slave status. The slave status is determined according to the result of the last communication the slave unit has executed. All the slave units can supply information on the slave status. The configuration of the slave status is shown below. For broadcasting communication, the transmission side does not execute transmission again, a communication error occurs on the
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Figure 19-7. Bit Configuration of Slave Status
MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0
Bit 0Note 1 0 1
Meaning Transmit data is not written in IEBus data register (DR) Transmit data is written in IEBus data register (DR)
Bit 1Note 2 0 1
Meaning Receive data is not stored in IEBus data register (DR) Receive data is stored in IEBus data register (DR)
Bit 2 0 1 Unit is not locked Unit is locked
Meaning
Bit 3 0 Fixed to 0
Meaning
Bit 4Note 3 0 1 Slave transmission is stopped Slave transmission is ready
Meaning
Bit 5 0 Fixed to 0
Meaning
Bit 7 0 0 1 1
Bit 6 0 1 0 1 Mode 0 Mode 1 Mode 2 Not used
Meaning Indicates the highest mode supported by unitNote 4.
Notes 1. 3. 4.
After reset: Bit 0 is set to 1. When the V850/SB2 serves as a slave unit, this bit corresponds to the status indicated by bit 4 (ENSLVTX) of the IEBus control register (BCR). When the V850/SB2 serves as a slave unit, bits 7 and 6 are fixed to `0' and `1' (mode 1), respectively.
2. The receive buffer size is 1 byte.
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(2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 19-8. Configuration of Lock Address
MSB Control bit: 4H Lower 8 bits LSB
Control bit: 5H
Undefined
Higher 4 bits
(3) Data If the control bit indicates reading of data (3H or 7H), the data in the data buffer of the slave unit is read by the master unit. If the control bit indicates writing of data (BH or FH), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) Locking and unlocking The lock function is used when a message is transferred in two or more communication frames. The unit that is locked does not receive data from units other than the one that has locked the unit (does not receive broadcasting communication). A unit is locked or unlocked as follows: (a) Locking If the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ACK = 0) by the control bit that specifies locking (3H, AH, or BH), the slave unit is locked by the master unit. At this time, the bit (bit 2) in the byte indicating the slave status is set to `1'. (b) Unlocking After transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3H, AH, or BH), or the control bit that has specified unlocking (6H), the slave unit is unlocked by the master unit. At this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to `0'. Locking or unlocking is not performed during broadcasting communication. Locking and unlocking conditions are shown below.
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(c) Lock setting conditions
Control Data Broadcasting Communication Communication End 3H, 6HNote AH, BH 0H, 4H, 5H, EH, FH Cannot be locked Cannot be locked Cannot be locked Cannot be locked Frame End Individual Communication Communication End Cannot be locked Cannot be locked Cannot be locked Frame End Lock set Lock set Cannot be locked
(d) Unlock release conditions (while locked)
Control Data Broadcasting Communication from Lock Request Unit Communication End 3H, 6HNote AH, BH 0H, 4H, 5H, EH, FH Unlocked Remains locked Unlocked Remains locked Frame End Individual Communication from Lock Request Unit Communication End Unlocked Unlocked Remains locked Frame End Remains locked Remains locked Remains locked
Note The frame end of control data 6H (slave status read/unlock) occurs when the parity in the data field is odd, and when the acknowledge signal from the IEBus unit is repeated up to the maximum number of transfer bytes without being output. 19.1.8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below. Figure 19-9. Bit Format of IEBus
Logic "1" Logic "0" Preparation period Synchronization Data period period Stop period
Preparation period: Data period: Stop period:
First low-level (logic "1") period Period indicating value of bit Last low-level (logic "1") period
Synchronization period: Next high-level (logic "0") period
The synchronization period and data period are almost equal to each other in length. The IEBus synchronizes each bit. The specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. The master and slave units monitor whether each period (preparation period, synchronization period, data period, and stop period) is output for specified time while they are in communication. If a period is not output for the specified time, the master and slave units report a timing error, immediately terminate communication and enter the standby status.
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19.2 IEBus Controller Configuration
The block diagram of the IEBus controller is shown below. Figure 19-10. IEBus Controller Block Diagram
CPU interface block Internal registers 8 BCR(8) 8 12 12 12 8 8 8 12 UAR(12) 12 SAR(12) 12 PAR(12) 8 CDR(8) 8 DLR(8) 8 DR(8) 8 USR(8) 8 8 ISR(8) 8 8 SSR(8) 8 8 8 SCR(8) 8 CCR(8) 8
Internal bus 8 8 RX NF MPX TX/RX PSR (8 bits) 12-bit latch Comparator Contention detection Interrupt controller INT request (handler, DMA transfer) 12
TX
MPX
Parity generation error detection
Interrupt control block
ACK generation IEBus interface block
CLK
5 Internal bus R/W
Bit processing block
Field processing block
(1) Hardware configuration and function The IEBus mainly consists of the following six internal blocks. * CPU interface block * Interrupt control block * Internal registers * Bit processing block * Field processing block * IEBus interface block
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(a) CPU interface block This is a control block that interfaces between the CPU (V850/SB2) and IEBus. (b) Interrupt control block This control block transfers interrupt request signals from IEBus to the CPU. (c) Internal registers These registers set data to the control registers and fields that control IEBus (for the internal registers, refer to 19.3 Internal Registers of IEBus Controller). (d) Bit processing block This block generates and disassembles bit timing, and mainly consists of a bit sequence ROM, 8-bit preset timer, and comparator. (e) Field processing block This block generates each field in the communication frame, and mainly consists of a field sequence ROM, 4-bit down counter, and comparator. (f) IEBus interface block This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, collision detector, parity detector, parity generator, and ACK/NACK generator.
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19.3 Internal Registers of IEBus Controller
19.3.1 Internal register list Table 19-7. Internal Registers of IEBus Controller
Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF3E0H FFFFF3E2H FFFFF3E4H FFFFF3E6H FFFFF3E8H FFFFF3EAH FFFFF3ECH FFFFF3EEH FFFFF3F0H FFFFF3F2H FFFFF3F4H IEBus control register IEBus unit address register IEBus slave address register IEBus partner address register IEBus control data register IEBus telegraph length register IEBus data register IEBus unit status register IEBus interrupt status register IEBus slave status register IEBus communication success counter IEBus transmit counter IEBus clock selection register IEBus high-speed clock selection register BCR UAR SAR PAR CDR DLR DR USR ISR SSR SCR R R/W R R R/W R/W - - - - - - - 8 Bits - - - 16 Bits - - - - - - - - 41H 01H 00H 01H 00H 0000H After Reset
FFFFF3F6H FFFFF3F8H FFFFF3DEH
CCR IECLK IEHCLK
Note
- R/W R/W - -
- - -
20H 00H 00H
Note The IEHCLK register is available only in the V850/SB2.
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19.3.2 Internal registers The internal registers incorporated in the IEBus controller are described below.
(1) IEBus control register (BCR)
After reset: 00H <7> BCR ENIEBUS RW Address: FFFFF3E0H <6> MSTRQ <5> ALLRQ <4> <3> 2 0 1 0 0 0
ENSLVTX ENSLVRX
ENIEBUS 0 1 IEBus unit stopped IEBus unit active
Communication enable flag
MSTRQ 0 1
Master request flag IEBus unit not requested as master IEBus unit requested as master
ALLRQ 0 1
Broadcast request flag Individual communication requested Broadcasting communication requested
ENSLVTX 0 1
Slave transmission enable flag Slave transmission disabled Slave transmission enabled
ENSLVRX 0 1
Slave reception enable flag Slave reception disabled Slave reception enabled
Cautions 1. While the IEBus is operating as the master, writing to the BCR register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. Master requests cannot therefore be multiplexed. However, if the IEBus is specified as a slave while a master request is being held pending, the BCR can be written to at the end of communication to clear the communication end/frame end flag. This is also the case when communication has been forcibly stopped (ENIEBUS flag = 0). 2. If a bit manipulation instruction for the BCR register conflicts with a hardware reset of the MSTRQ flag, the BCR register may not operate normally. The following countermeasures are recommended in this case. * Because the hardware reset is instigated in the acknowledgment period of the slave address field, be sure to observe Caution 1 of (b) Master request flag (MSTRQ) below. * Be sure to observe the caution above regarding writing to the BCR register.
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(a) Communication enable flag (ENIEBUS)...Bit 7 Set: By software Reset: By software Caution Before setting the ENIBUS flag, make the following setting: * Set the interrupt enabled (EI) status and enable the interrupt processing of INTIE2 (IEBMK = 2). * Set the IEBus unit address register (UAR) (b) Master request flag (MSTRQ)...Bit 6 Set: By software ACK period of the slave address field, if a MSTRQ flag setting instruction is sent in this period, it will be invalid. Cautions 1. The master request should be resent by software following a loss in arbitration. When resending the master request in this case, set (1) the MSTRQ flag after securing the required wait period. This flag is unable to be set (1) before the end of this wait period. Reset: By hardware, at the end of the arbitration period. Because the reset signal is generated in the
INTIE2 interrupt signal
Start interrupt generation
MSTRQ flag reset signal
Forcible reset period Wait period (61.7 s MAX)
2. When a master request has been sent and bus mastership acquired, do not set the MSTRQ, ENSLVTX, or ENSLVRX flag until the end of communication (i.e. the ISR register's communication end/frame end flag is set (1)) as setting these flags disables interrupt request generation. However, these flags can be set if communication has been aborted. (c) Broadcast request flag (ALLRQ)...Bit 5 Set: By software Reset: By software Caution When requesting broadcasting communication, always set the ALLRQ flag, then the MSTRQ flag.
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(d) Slave transmission enable flag (ENSLVTX)...Bit 4 Set: By software Reset: By software Cautions 1. Clear the ENSLVTX flag before setting the MSTRQ flag when making a master request. If a slave transmission request is sent in slave mode when the ENSLVTX flag is unset, NACK in the control field will be returned. Moreover, when returning to an enabled state from a disabled state, transmission becomes valid from the next frame. 2. If the controller receives control data for data/control writing (3H, 7H) when the ENSLVTX flag is unset, NACK will be returned via the acknowledge bit of the control field. 3. The status interrupt (INTIE2) will be generated and communication continued when the control data of a slave status request is returned, even if the ENSLVTX flag is in the reset status. (e) Slave reception enable flag (ENSLVRX)...Bit 3 Set: By software Reset: By software Caution If the ENSLVRX flag is reset when the IEBus is busy with other CPU processing, NACK will be returned via the acknowledge bit of the control field, making it possible to disable slave reception. Note that resetting this flag only disables individual communication, not If the received slave address matches the unit address broadcasting communication.
during individual communication, however, the start interrupt (INTIE2) is generated. If CPU processing has priority (neither reception nor transmission occurs), be sure to stop the IEBus unit by resetting the ENIEBUS flag. Note also that when returning to an enabled state from a disabled state, transmission becomes valid from the next frame.
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(2) IEBus unit address register (UAR) This register sets the unit address of an IEBus unit. communication. Sets the unit address (12 bits) to bits 11 to 0.
15 14 13 12 11 10 UAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E2H After reset R/W 0000H R/W
This register must be always set before starting
(3) IEBus slave address register (SAR) During master request, the value of this register is reflected in the value of the transmit data in the slave address field. This register must be always set before starting communication. Sets the slave address (12 bits) to bits 11 to 0.
15 14 13 12 11 10 SAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E4H After reset R/W 0000H R/W
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(4) IEBus partner address register (PAR) (a) When slave unit The value of the receive data in the master address field (address of the master unit) is written to this register. If a request "4H" to read the lock address (lower 8 bits) is received from the master, the CPU must read the value of this register, and write it to the lower 8 bits IEBus data register (DR). If a request "5H" to read the lock address (higher 4 bits) is received from the master, the CPU must read the value of this register and write the data of the higher 4 bits to DR. Sets the partner address (12 bits) to bits 11 to 0.
15 14 13 12 11 10 PAR 0 0 0 0 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E6H After reset R/W 0000H R
(5) IEBus control data register (CDR) (a) When master unit The data of the lower 4 bits is reflected in the data transmitted in the control field. During master request, this register must be set in advance before starting communication. (b) When slave unit The data received in the control field is written to the lower 4 bits. When the status transmission flag (STATUS) of the IEBus interrupt status register (ISR) is set, an interrupt (INTIE2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of CDR.
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After reset: 01H 7 CDR 0
R/W 6 0
Address: FFFFF3E8H 5 0 4 0 3 MOD 2 SELCL2 1 SELCL1 0 SELCL0
MOD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SELCL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SELCL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SELCL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Function Reads slave status Undefined Undefined Reads data and locks Reads lock address (lower 8 bits) Reads lock address (lower 4 bits) Reads slave status and unlocks Reads data Undefined Undefined Writes command and locks Writes data and locks Undefined Undefined Writes command Writes data
Cautions 1. Because the slave unit must judge whether the received data is a "command" or "data", it must read the value of this register after completing communication. 2. If the master unit sets an undefined value, NACK is returned from the slave unit, and communication is aborted. During broadcasting communication, however, the master unit continues communication without recognizing ACK/NACK; therefore, make sure not to set an undefined value to this register during broadcasting communication. 3. In the case of defeat in a bus conflict and a slave status request is received from the unit that won, the telegraph length register (DLR) is fixed to "01H". Therefore, when a re-request of the master follows, the appointed telegraph length must be set to DLR.
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(c) Slave status return operation When the IEBus receives a request to transfer from master to slave status or a lock address request (control data: 0H, 6H), whether ACK in the control field is returned or not depends on the status of the IEBus unit. (1) If 0H or 6H control data was received in the unlocked state (2) If 4H or 5H control data was received in the unlocked state (3) If 0H, 4H, 5H or 6H control data was received in the locked state from the unit that sent the lock request (4) If 0H, 4H, or 5H control data was received in the locked state from other than the unit that sent the lock request (5) If 6H control data was received in the locked state from other than the unit that sent the lock request ACK not returned ACK returned ACK returned ACK returned ACK not returned
In all of the above cases, the acknowledgment of a slave status or lock request will cause the STATUSF flag (bit 4 of the ISR register) to be set and the status interrupt (INTIE2) to be generated. The generation timing is at the end of the control field parity bit (at the start of the ACK bit). However, if ACK is not returned, a NACK error is generated after the ACK bit, and communication is terminated. Figure 19-11. Interrupt Generation Timing (for (1), (3), and (4))
Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) Telegraph length field Telegraph length bits (8 bits)
INTIE2
Flag set by reception of 0H, 4H, 5H, 6H STATUSF flag
Flag reset by CPU processing
Internal NACK flag
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Figure 19-12. Interrupt Generation Timing (for (2) and (5))
Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) ACK bit (1 bit) Terminated by communication error
INTIE2 Flag reset by CPU processing
Flag set by reception of 0H, 4H, 5H, 6H STATUSF flag
Internal NACK flag
Error generated by detection of NACK
Because in (4) and (5) the communication was from other than the unit that sent the lock request while the IEBus was in the locked state, the start or communication complete interrupt (INTIE2) is not generated, even if the IEBus unit is the communication target. The STATUSF flag (bit 4 of the ISR register) is set and the status interrupt (INTIE2) generated, however, if a slave status or lock address request is acknowledged. Note that even if the same control data is received while the IEBus is in the locked state, the interrupt generation timing for INTIE2 differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. Figure 19-13. Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5))
Start Broadcasting Master address (12 + P) Slave address (12 + P + A) Telegraph Control DataNote lengthNote (4 + P + A) (8 + P + A) (8 + P + A)
IEBus sequence
INTIE2
Status interrupt
Note The telegraph length and data modes are not set in the case of (5) because ACK is not returned. Remark P: Parity bit, A: ACK/NACK bit
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Figure 19-14. Timing of INTIE2 Interrupt Generation in Locked State (for (3))
Start Broadcasting Master address (12 + P) Slave address (12 + P + A) Control Telegraph length Data (4 + P + A) (8 + P + A) (8 + P + A)
IEBus sequence
INTIE2
Start interrupt
Status interrupt
Communication complete interrupt
Remark
P: Parity bit, A: ACK/NACK bit
(6) IEBus telegraph length register (DLR) (a) When transmission unit ... Master transmission, slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. This register must be set in advance before transmission. (b) When reception unit ... Master reception, slave reception The receive data in the telegraph length field transmitted from the transmission unit is written to this register. Remark The IEBus telegraph length register consists of a write register and a read register. Consequently, data written to this register cannot be read as is. The data that can be read is the data received during IEBus communication.
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After reset: 01H 7 DLR
R/W 6
Address: FFFFF3EAH 5 4 3 2 1 0
Bit 7 0 0 : 0 : 1 0 6 0 0 : 0 : 1 0 5 0 0 : 1 : 1 0 4 0 0 : 0 : 1 0 3 0 0 : 0 : 1 0 2 0 0 : 0 : 1 0 1 0 1 : 0 : 1 0 0 1 0 : 0 : 1 0
Setting value 01H 02H : 20H : FFH 00H
Remaining number of communication data bytes 1 byte 2 bytes : 32 bytes : 255 bytes 256 bytes
Cautions 1. If the master issues a request "0H, 4H, 5H, or 6H" to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to "01H" by hardware; therefore, the CPU does not have to set this register. 2. In the case of defeat in a bus conflict and a slave status request is received from the unit that won, DLR is fixed to "01H". Therefore, if a re-request of the master follows, the appointed telegraph length must be set to DLR.
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(7) IEBus data register (DR) The IEBus data register (DR) sets the communication data. Sets the communication data (8 bits) to bits 7 to 0. Remark The IEBus data register consists of a write register and a read register. Consequently, data written to this register cannot be read as is. The data that can be read is the data received during IEBus communication. (a) When transmission unit The data (1 byte) written to the IEBus data register (DR) is stored to the IEBus interface shift register of the IEBus. It is then output from the most significant bit, and an interrupt (INTIE1) is issued to the CPU each time 1 byte has been transmitted. If NACK is received after 1-byte data has been transferred during individual transfer, data is not transferred from DR to the shift register, and the same data is retransmitted. At this time, INTIE1 is not generated. INTIE1 is issued when the IEBus interface shift register stores the IEBus data register value. However, when the last byte and 32nd byte (the last byte of 1 communication frame) is stored in the shift register, INTIE1 is not issued. (b) When reception unit One byte of the data received by the shift register of the IEBus interface block is stored to this register. Each time 1 byte has been correctly received, an interrupt (INTIE1) is issued. When transmit/receive data is transferred to and from the IEBus data register, using DMA can reduce the CPU processing load.
After reset: 00H 7 DR R/W 6 Address: FFFFF3ECH 5 4 3 2 1 0
Cautions 1. If the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (INTIE2) occurs, stopping transmission. 2. When the IEBus is a receiving unit, if the reading of the data is too late for the next data reception timing, the unit will enter the overrun state. At this time, during individual communication reception, NACK will be returned at the acknowledge bit of the data field, and the master unit will be requested to retransmit the data. If an overrun error occurs during broadcasting communication, the communication error interrupt (INTIE2) is generated.
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(8) IEBus unit status register (USR)
After reset: 00H 7 USR 0 R Address: FFFFF3EEH <6> SLVRQ <5> ARBIT <4> ALLTRNS <3> ACK <2> LOCK 1 0 0 0
SLVRQ 0 1
Slave request flag No request from master to slave Request from master to slave
ARBIT 0 1 Arbitration win Arbitration loss
Arbitration result flag
ALLTRNS 0 1
Broadcasting communication flag Individual communication status Broadcasting communication status
ACK 0 1 NACK transmitted ACK transmitted
ACK transmission flag
LOCK 0 1 Unit unlocked Unit locked
Lock status flag
(a) Slave request flag (SLVRQ)...Bit 6 A flag indicating whether there has been a slave request from the master. Set: When the unit is requested as a slave (if the received slave address and unit UAR match during individual communication reception, or if the higher 4 bits of the received slave address match or if the received slave address is FFFH during broadcasting communication reception), this flag is set by hardware when the acknowledge period of the slave address field starts. Reset: This flag is reset by hardware when the unit is not requested as a slave. The reset timing is the same as the set timing. If the unit is requested as a slave immediately after communication has been correctly received (when the SLVRQ bit is set), and if a parity error occurs in the slave address field for that communication, the flag is not reset.
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(b) Arbitration result flag (ARBIT)...Bit 5 A flag that indicates the result of arbitration. Set: When the data output by the IEBus unit during the arbitration period does not match the bus line data. Reset: By the start bit timing. Cautions 1. The timing at which the arbitration result flag (ARBIT) is reset differs depending on whether the unit outputs a start bit. * If start bit is output: The flag is reset at the output start timing. * If start bit is not output: The flag is reset at the detection timing of the start bit (approx. 160 s after output) 2. The flag is reset at the detection timing of the start bit if the other unit outputs the start bit earlier and the unit does not output the start bit after the master request. (c) Broadcasting communication flag (ALLTRNS)...Bit 4 A flag indicating whether the unit is performing broadcasting communication. The contents of the flag are updated in the broadcast field of each frame. Except for initialization (reset) by system reset, the set/reset conditions vary depending on the receive data of the broadcast field bit. Set: When "broadcasting" is received by the broadcast field Reset: When "individual" is received by the broadcast field, or upon the input of a system reset. Caution The broadcast flag is updated regardless of whether IEBus is the communication target or not. Figure 19-15. Example of Broadcasting Communication Flag Operation
IEBus sequence Start Broadcasting M11 M10 Start Individual M11 M10
Broadcasting communication flag Set Not reset by start bit Reset
(d) ACK transmission flag (ACK)...Bit 3 A flag that indicates whether ACK has been transmitted in the ACK period of the ACK field when the IEBus is a receiving unit. The contents of the flag are updated in the ACK period of each frame. However, if the internal circuit is initialized by the occurrence of a parity error, etc., the contents are not updated in the ACK period of that field.
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(e) Lock status flag (LOCK)...Bit 2 A flag that indicates whether the unit is locked. Set: When the communication end flag goes low level and the frame end flag goes high level after receipt of a lock specification (3H, 6H, AH, BH) in the control field. Reset: When the communication enable flag is cleared. When the communication end flag is set after receipt of a lock release (3H, 6H, AH, BH) in the control field. Caution Lock specification/release is not possible in broadcasting communication. In the lock status, individual communication from a unit other than the one that requests locking is not acknowledged. However, even communication from a unit other than the one that requests locking is acknowledged as long as the communication is a slave status request.
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(9) IEBus interrupt status register (ISR) This register indicates the status when IEBus issues an interrupt. The ISR is read to generate an interrupt, after which the specified interrupt processing is carried out. Reset the ISR register after reading it. Until it is reset, the INTIE2 interrupt signal is not generated (nor held pending). To reset the ISR register, reset each flag, satisfying the reset conditions in Table 19-8. Table 19-8. Reset Conditions of Flags in ISR Register
Flag Name IEERR, STARTF, STATUSF Reset Condition Byte write operation of ISR register. Any value can be written. Set MSTRQ, ENSLVTX, or ENSLVRX flag. Processing Example ISR = 00H, etc.
ENDTRNS, ENDFRAM
BCR register = 88H or ENSLVTX = 1, etc.
Caution
Even if 0 is written to the ENDTRNS or ENDFRAM flag by accessing the ISR register, these flags are not reset. Reset them as described above.
Remark
MSTRQ:
Bit 6 of the IEBus control register (BCR)
ENSLVTX: Bit 4 of the IEBus control register (BCR) ENSLVRX: Bit 3 of the IEBus control register (BCR)
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After reset: 00H 7 ISR 0
R/W Address: FFFFF3F0H <6> IEERR <5> <4> <3> <2> 1 0 0 0
STARTF STATUSF ENDTRNS ENDFRAM
IEERR 0 1
Communication error flag (during communication) No communication error Communication error
STARTF 0 1
Start interrupt flag Start interrupt does not occur Start interrupt occurs
STATUSF 0 1
Status transmission flag (slave) No slave status/lock address (higher 4 bits, lower 8 bits) transmission request Slave status/lock address (higher 4 bits, lower 8 bits) transmission request
ENDTRNS 0 1
Communication end flag Communication does not end after the number of bytes set in the telegraph length field have been transferred Communication ends after the number of bytes set in the telegraph length field have been transferred
ENDFRAM 0 1
Frame end flag The frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) does not end The frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) ends
Caution Each of IEERR, STARTF, STATUSF, ENDTRNS, and ENDFRAM are generation triggers for the interrupt request signal (INTIE2) (see Figure 19-16). Because of this, if any one of these interrupt triggers have been set, no new interrupt will be generated by a subsequent trigger. Clear the flag of the interrupt source by the interrupt processing program, before the next interrupt occurs.
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(a) Communication error flag (IEERR)...Bit 6 A flag that indicates the detection of an error during communication. Set: The flag is set if a timing error, parity error (except in the data field), NACK reception (except in the data field), underrun error, or overrun error (that occurs during broadcasting communication reception) occurs. Reset: By software (b) Start interrupt flag (STARTF)...Bit 5 A flag that indicates whether the interrupt was in the ACK period of the slave address field. Set: In the slave address field, upon a master request. When IEBus is a slave unit, this flag is set upon a request from the master (only if it was a slave request in the locked state from the unit requesting a lock). Reset: By software (c) Status transmission flag (STATUSF)...Bit 4 A flag indicating that the transmission status is either the master to slave status, or the lock address (higher 4 bits, lower 8 bits), when IEBus is a slave unit. Set: When 0H, 4H, 5H, or 6H is received in the control field from the master when the IEBus is a slave unit. Reset: By software (d) Communication end flag (ENDTRANS)...Bit 3 A flag that indicates whether communication ends after the number of bytes set in the telegraph length field have been transferred. Set: When the value of the SCR counter is 0. Reset: When the MSTRQ, ENSLVTX, or ENSLVRX flag is set. (e) Frame end flag (ENDFRAM)...Bit 2 A flag that indicates whether communication ends after the maximum number of bytes (32 bytes) prescribed by mode 1 have been transferred. Set: When the value of the CCR counter is 0. Reset: When the MSTRQ, ENSLVTX, or ENSLVRX flag is set.
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(f) Communication error triggers * Timing error Occurrence conditions: Occurs if the high/low level width of the communication bit has shifted from the prescribed value. Remark: The respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer. An interrupt is generated when a timing error occurs. * Parity error Occurrence conditions: Occurs if the generated parity and the received parity in each field do not match when IEBus is a receiving unit. Remark: During individual communication, an interrupt is generated if a parity error occurs in a field other than the data field. During broadcasting communication, an interrupt is generated even if a parity error occurs in the data field. Restriction: If there is a slave request that has lost in arbitration to a broadcast request, no interrupt is generated, even if a parity error occurs. * NACK reception error Occurrence conditions: This error occurs when NACK is received during the ACK period in each of the slave address, control, and telegraph length fields during individual communication, regardless of whether the unit is the master or a slave unit. A NACK reception error only occurs in individual communication. ACK and NACK are not discriminated in broadcasting communication. Remark: An interrupt is generated if NACK is received in a field other than the data field. * Underrun Occurrence conditions: Occurs during data transmission if there was insufficient time to write the next transmit data to the IEBus data register (DR) before ACK reception. Remark: * Overrun Occurrence conditions: The data interrupt request (INTIE1) that stores each byte of data in the IEBus data register (DR), and the DR register is read by DMA or software. An overrun error occurs if this reading processing is late and its timing becomes that of the next data reception. Remark: In individual communication reception, an acknowledgment is not returned in the ACK period of this data, resulting in the retransmission of the data by the transmit unit. Consequently, the IEBus transfer counter (CCR) is decremented, whereas the IEBus communication success counter (SCR) is not. In broadcasting communication reception, reception is stopped by the occurrence of a communication error (INTIE2), at which time the DR register is not updated. The STATRX flag (bit 1 of the SSR register) also remains set (1) without generating INTIE1. The overrun state is released at the timing of the next data reception following the reading of DR. An interrupt is generated if an underrun occurs.
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(g) Overrun error - supplementary details (i) When the frame ends in the overrun state during individual communication reception If the DR register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (INTIE2) is generated. The overrun state is maintained until the DR register is read after the end of the frame. (ii) If the next reception is started in the case of (i) above, or if the next reception is started without the DR register being read after the final data has been received, regardless of whether the communication is broadcasting or individual Even if communication to the IEBus unit starts in the overrun state, the cause of the overrun, NACK, is not returned in the ACK period of the slave address, control, or telegraph length field (the DR register is not updated). If the next communication is not to the IEBus unit, the DR register is not updated until it is read. Because the IEBus unit is not a communication target, the data interrupt (INTIE1) and communication error interrupt (INTIE2) are not generated. (iii) If the next transmission occurs in the overrun state The data to be transmitted next in the overrun state can be no more than 2 bytes long. Because the data request interrupt (INTIE1) is not generated, the transmit data cannot be set, resulting in an underrun error. Therefore, clear the overrun status before starting transmission. (iv) Overrun state release The overrun state can only be released by reading the DR register or by a system reset. Therefore, be sure to read DR in a communication error interrupt processing program.
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(10)IEBus slave status register (SSR) This register indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, the CPU reads this register, and writes a slave status to the IEBus data register (DR) to transmit the slave status. At this time, the telegraph length is automatically set to "01H" that setting of the IEBus telegraph length register (DLR) is not required (because it is preset by hardware). Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to "01H" (mode 1).
After reset: 41H 7 SSR 0 R 6 1 Address: FFFFF3F2H 5 0 <4> STATSLV 3 0 <2> <1> <0> STATTX
STATLOCK STATRX
STATSLV 0 1
Slave transmission status flag Slave transmission stops Slave transmission enabled
STATLOCK 0 1 Unlock status Lock status
Lock status flag
STATRX 0 1
DR receive status Receiving data not stored in DR Receiving data stored in DR
STATTX 0 1
DR transmit status Transmission data not stored in DR Transmission data stored in DR
(a) Slave transmission status flag (STATSLV)...Bit 4 Reflects the contents of slave transmission enable flag. (b) Lock status flag (STATLOCK)...Bit 2 Reflects the contents of locked flag. (c) DR reception status (STATRX)...Bit 1 This flag indicates the DR reception state. (d) DR transmission status (STATTX)...Bit 0 This flag indicates the DR transmission state.
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(11)IEBus success count register (SCR) The IEBus success count register (SCR) indicates the number of remaining communication bytes. This register reads the count value of the counter that decrements the value set by the telegraph length register by ACK in the data field. When the count value has reached "00H", the communication end flag (ENDTRNS) of the IEBus interrupt status register (ISR) is set.
After reset: 01H 7 SCR R Address: FFFFF3F4H 6 5 4 3 2 1 0
Bit 7 0 0 : 0 : 1 0 6 0 0 : 0 : 1 0 5 0 0 : 1 : 1 0 4 0 0 : 0 : 1 0 3 0 0 : 0 : 1 0 2 0 0 : 0 : 1 0 1 0 1 : 0 : 1 0 0 1 0 : 0 : 1 0
Setting value 01H 02H : 20H : FFH 00H
Remaining number of communication data bytes 1 byte 2 bytes : 32 bytes : 255 bytes 0 byte (end of communication) or 256 bytesNote
Note The actual hard counter consists of 9 bits. When "00H" is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. Therefore, either the communication end flag is used, or if "00H" is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256.
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(12)IEBus communication count register (CCR) The IEBus communication count register (CCR) indicates the number of remaining bytes in the communication byte number specified in the communication mode. Bits 7 to 0 of the IEBus communication count register (CCR) indicate the number of transfer bytes. This register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1. Whereas SCR (IEBus communication success counter) is decremented during normal communication (ACK), CCR is decremented when 1 byte has been communicated, regardless of whether ACK or NACK. When the count value has reached "00H", the frame end flag (ENDFRAM) is set. The maximum number of transfer bytes of the preset value of mode 1 per frame is 20H (32 bytes).
After reset: 20H 7 CCR R 6 Address: FFFFF3F6H 5 4 3 2 1 0
(13)IEBus clock selection register (IECLK) This register selects the clock of IEBus. The main clock frequencies that can be used are shown below. Main clock frequencies other than the following cannot be used. * 6.0 MHz/6.291 MHz * 12.0 MHz/12.582 MHz Remark More IEBus clock types can be selected for the PD703036H, 703036HY, 70F3036H, 70F3036HY, 703037H, 703037HY, 70F3037H, and 70F3037HY by setting in combination with the IEBus high-speed clock selection register (IEHCLK).
After reset: 00H 7 IECLK 0 R/W 6 0 Address: FFFFF3F8H 5 0 4 0 3 0 2 0 1 0 0 IECS
IECS 0 1
IEBus clock selection @ fXX = 6.0 MHz or fXX = 6.291 MHz @ fXX = 12.0 MHz or fXX = 12.582 MHz
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(14)IEBus high-speed clock selection register (IEHCLK) This register selects the clock of IEBus. The main clock frequencies that can be used are shown below. Main clock frequencies other than the following cannot be used. * 6.0 MHz/6.291 MHz * 12.0 MHz/12.582 MHz * 18.0 MHz/18.873 MHz Caution The IEHCLK register is available only in the H versions of the V850/SB2 (PD703036H, 703036HY, 70F3036H, 70F3036HY, 703037H, 703037HY, 70F3037H, and 70F3037HY).
After reset: 00H 7 IEHCLK 0 R/W 6 0 Address: FFFFF3DEH 5 0 4 0 3 0 2 0 1 0 0 IECS1
IECS1 0 0 1 1
IECSNote 0 1 0 1
IEBus clock selection @ fXX = 6.0 MHz or fXX = 6.291 MHz @ fXX = 12.0 MHz or fXX = 12.582 MHz @ fXX = 18.0 MHz or fXX = 18.873 MHz Setting prohibited
Note Bit 0 of the IECLK register
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19.4 Interrupt Operations of IEBus Controller
19.4.1 Interrupt control block Interrupt request signal <1> Communication error <2> Start interrupt <3> Status communication <4> End of communication <5> End of frame <6> Transmit data write request <7> Receive data read request IEERR STARTF STATUSF ENDTRNS ENDFRAM STATTX STATRX
1 through 5 of the above interrupt requests are assigned to the interrupt status register (ISR). For details, refer to Table 19-9 Interrupt Source List. The configuration of the interrupt control block is illustrated below. Figure 19-16. Configuration of Interrupt Control Block
IEERR STARTF STATUSF ENDTRNS ENDFRAM STATTX STATRX INTIE1 INTIE2 IEBus macro Interrupt control block V850/SB2 CPU
Cautions 1. OR output of STATRX and STATTX is treated as a DMA transfer start signal (INTIE1). 2. OR output of IEERR, STARTF, STATUSF, ENDTRNS, and ENDFRAM is treated as a vector interrupt request signal (INTIE2) for V850/SB2.
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19.4.2 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850/SB2 can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified through software manipulation. The interrupt sources are listed below. Table 19-9. Interrupt Source List
Interrupt Source Condition of Generation Unit Timing error Parity error Communication error Master/slave Reception Field All fields Other than data (individual) All fields (broadcasting) NACK reception Reception (Transmission) Transmission Reception Other than data (individual) Data Data (broadcasting) Slave/address Slave request judgment Contention judgment (If loses, remaster processing) Communication preparation processing Slave request judgment Communication preparation processing Refer to transmission processing example such as slave status. Interrupt always occurs if loses in contention during master request CPU Processing after Generation of Interrupt Undo communication processing Remark
Communication error is OR output of timing error, parity error, NACK reception, underrun error, and overrun error
Underrun error Overrun error
Start interrupt
Master
Slave
Slave/address
Generated only during slave request
Status transmission
Slave
Control
Interrupt occurs regardless of slave transmission enable flag Interrupt occurs if NACK is returned in the control field. Set if SCR is cleared to 0
End of communication
Transmission Reception
Data Data
DMA transfer end processing DMA transfer end processing Receive data processing Retransmission preparation processing Re-reception preparation processing Reading of transmit dataNote.
End of frame
Transmission
Data
Set if CCR is cleared to 0
Reception
Data
Transmit data write
Transmission
Data
Set after transfer transmission data to internal shift register This does not occur when the last data is transferred. Set after normal data reception
Receive data read
Reception
Data
Reading of received dataNote
Note If DMA transfer or software manipulation is not executed.
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19.4.3 Communication error source processing list The following table shows the occurrence conditions of the communication errors (timing error, NACK reception error, overrun error, underrun error, and parity error), error processing by the internal IEBus controller, and examples of processing by software. Table 19-10. Communication Error Source Processing List (1/2)
Timing Error Occurrence condition Unit status Occurrence condition Location of occurrence Broadcasting communication Hardware processing Reception If bit specification timing is not correct Other than data field Data field Other than data field Data field Transmission
* Reception stops. * INTIE2 occurs * To start bit waiting status Remark Communication between other units does not end.
* Transmission stops. * INTIE2 occurs * To start bit waiting status
Software processing Individual communication Hardware processing
* Error processing (such as retransmission request) * * * * Reception stops. INTIE2 occurs NACK is returned. To start bit waiting status
* Error processing (such as retransmission request * Transmission stops. * INTIE2 occurs * To start bit waiting status * Error processing (such as retransmission request
Software processing
* Error processing (such as retransmission request)
NACK Reception Error Occurrence condition Unit status Occurrence condition Location of occurrence Broadcasting communication Hardware processing Software processing Individual communication Hardware processing Reception Unit NACK transmission Other than data field - - * Reception stops. Data field Transmission Unit NACK transmission Other than data field - - * Reception stops. Data field NACK reception of data of 32nd byte - - * INTIE2 occursNote. * To start bit waiting status
- - * INTIE2 does not occur.
- - * INTIE2 does not occur.
* INTIE2 occurs. * Data * INTIE2 occurs. * Retransretransmitted mission * To start bit * To start bit by other unit is processing waiting status waiting status received. Software processing * Error processing (such as retransmission request) - * Error processing (such as retransmission request) -
* Error processing (such as retransmission request)
Note Both ISR.6 (IEERR) and ISR.2 (ENDFRAM) are set to 1. To reset them, satisfy the conditions in Table 19-8.
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Table 19-10. Communication Error Source Processing List (2/2)
Overrun Error Occurrence condition Unit status Occurrence condition Location of occurrence Broadcasting communication Hardware processing Reception DR cannot be read in time before the next data is received. Other than Data field data field - * Reception stops. * INTIE2 occurs. * To start bit waiting status Remarks 1. Communication between other units does not end. 2. Data cannot be received until the overrun status is cleared. Software processing - * DR is read and overrun status is cleared. * Error processing (such as retransmission request) Individual communication Hardware processing - * INTIE2 does not occur. * NACK is returned. * Data is retransmitted from other unit. Remark Data cannot be received until overrun status is cleared. Software processing - * DR is read and overrun status is cleared. * Error processing (such as retransmission request) - * Error processing (such as retransmission request) - * Transmission stops. * INTIE2 occurs. * To start bit waiting status - * Error processing (such as retransmission request) Transmission DR cannot be written in time before the next data is transmitted. Other than Data field data field - * Transmission stops. * INTIE2 occurs. * To start bit waiting status Underrun Error
Parity Error Occurrence condition Unit status Occurrence condition Location of occurrence Broadcasting communication Hardware processing Reception Received data and received parity do not match. Other than data field * Reception stops. * INTIE2 occurs. * To start bit waiting status Remark Communication between other units does not end. Software processing Individual communication Hardware processing * Error processing (such as retransmission) * Reception stops. * INTIE2 occurs. * To start bit waiting status * * * * Reception does not stop. INTIE2 does not occur. NACK is returned. Data retransmitted by other unit is received. - - - - - Data field Other than data field - Transmission - Data field -
Software processing
* Error processing (such as retransmission request)
-
-
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19.5 Interrupt Generation Timing and Main CPU Processing
19.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, master request, and slave reception). Figure 19-17. Master Transmission
Approx. 624 s (mode 1) <1> Start
Broadcasting
M address P S address P
A
Control
P
A
Telegraph length
P
A
Data 1
Approx. 390 s (mode 1) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A
<1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Judgment of contention result <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Re-communication processing (See 19.5.1 (3) Recommunication processing) Remarks 1. : Interrupt (INTIE1) occurrence (See 19.5.1 (2) Interrupt (INTIE1) occurrence) The transmit data of the second byte and those that follow are written to the IEBus data register (DR) by DMA transfer. At this time, the data transfer direction is RAM (memory) SFR (peripheral) 2. : An interrupt (INTIE1) does not occur. 3. n = Final number of data bytes End of communication processing Error processing Remaster request processing Slave reception processing (See 19.5.1 (1) Slave reception processing) Error processing
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(1) Slave reception processing If a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from RAM (memory) ` SFR (peripheral) to SFR (peripheral) ` RAM (memory) until the first data is received. The maximum pending period of this data transfer direction changing processing is about 1040 s in communication mode 1. (2) Interrupt (INTIE1) occurrence If NACK is received from the slave in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication ends midway. (3) Recommunication processing The vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted.
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19.5.2 Master reception Before performing master reception, it is necessary to notify the slave of slave transmission units. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, set (1) the slave transmission enable flag (ENSLVTX), and waits. Initial preparation processing: Sets a unit address, slave address, and control data. Communication start processing: Sets the bus control register (enables communication and master request). Figure 19-18. Master Reception
Approx. 1014 s (mode 1) <1> Start
Broadcasting Telegraph length
M address P
S address
P
A
Control
P
A
P
A
Data 1
Approx. 390 s (mode 1) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A
<1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request Judgment of collision result <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Frame end processing (See 19.5.2 (2) Frame end processing) Remarks 1. : Interrupt (INTIE1) occurrence (See 19.5.2 (1) Interrupt (INTIE1) occurrence) The receive data stored to the IEBus data register (DR) is read by DMA transfer. At this time, the data transfer direction is SFR (peripheral) RAM (memory). 2. n = Final number of data bytes End of communication processing Error processing Remaster request processing Slave processing Error processing
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(1) Interrupt (INTIE1) occurrence If NACK is transmitted (hardware processing) in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the slave. If the receive data is not read in time until the next data is received, the hardware automatically transmits NACK. (2) Frame end processing The vector interrupt processing in <2> judges whether the data has been correctly received within one frame. If the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame.
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19.5.3 Slave transmission Initial preparation processing: Sets a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Sets the bus control register (enables communication, slave transmission, and slave reception). Figure 19-19. Slave Transmission
Approx. 624 s (mode 1) <1> Start
Broadcasting Telegraph length
M address P S address P
A
Control
P
A
P
A
Data 1
Approx. 390 s (mode 1) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A
<1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Frame end processing (See 19.5.3 (2) Frame end processing) Remarks 1. : Interrupt (INTIE1) occurrence (See 19.5.3 (1) Interrupt (INTIE1) occurrence). The transmit data of the second byte and those that follow are written to the IEBus data register (DR) by DMA transfer. At this time, the data transfer direction is RAM (memory) SFR (peripheral). 2. 3. : An interrupt (INTIE1) does not occur. : Interrupt (INTIE2) occurrence An interrupt occurs only when 0H, 4H, 5H, or 6H is received in the control field in the slave status (for the slave status response operation during locked, refer to 19.3.2 (5) IEBus control data register (CDR)). 4. n = Final number of data bytes End of communication processing Error processing Error processing
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(1) Interrupt (INTIE1) occurrence If NACK is received from the master in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended. (2) Frame end processing The vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the continuation of the data must be transmitted.
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19.5.4 Slave reception Initial preparation processing: Sets a unit address. Communication start processing: Sets the bus control register (enables communication, disables slave transmission, and enables slave reception). Figure 19-20. Slave Reception
Approx. 1014 s (mode 1) <1> Start
Broadcasting Telegraph length
M address P S address P
A
Control
P
A
P
A
Data 1
Approx. 390 s (mode 1) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A
<1> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of slave request <2> Interrupt (INTIE2) occurrence Judgment of occurrence of error Judgment of end of communication Judgment of end of frame Frame end processing (See 19.5.4 (2) Frame end processing). Remarks 1. : Interrupt (INTIE1) occurrence (See 19.5.4 (1) Interrupt (INTIE1) occurrence). The receive data stored to the IEBus data register (DR) is read by DMA transfer. At this time, the data transfer direction is SFR (peripheral) RAM (memory). 2. n = Final number of data bytes End of communication processing Error processing Slave processing Error processing
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(1) Interrupt (INTIE1) occurrence If NACK is transmitted in the data field, an interrupt (INTIE1) is not issued to the CPU, and the same data is retransmitted from the master. If the receive data is not read in time until the next data is received, NACK is automatically transmitted. (2) Frame end processing The vector interrupt processing in <2> judges whether the data has been correctly received within one frame.
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19.5.5 Interval of occurrence of interrupt for IEBus control Each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into consideration. The locations at which the following interrupts may occur are indicated by in the field where it may occur. does not mean that the interrupt occurs at each of the points indicated by . If an error interrupt (timing error, parity error, or ACK error) occurs, the IEBus internal circuit is initialized. As a result, the following interrupt does not occur in that communication frame. (1) Master transmission Figure 19-21. Master Transmission (Interval of Interrupt Occurrence)
Start bit t1 T
Broadcasting Master address P
Slave address T t3
PA
Control A T
PA
Telegraph length
PA
Data A T t5
PA U
T
T t2
A
T t4
T Communication start interrupt
Communication starts
Data T
PA U
Data
Data T t4
PA A
End of communication End of frame
Remarks 1. T: Timing error A: ACK error U: Underrun error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. (IEBus: at 6.29 MHz)
Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - timing error Communication start interrupt - end of communication Transmission data request interrupt interval Symbol t1 t2 t3 t4 t5 MIN. Approx. 93 Approx. 1282 Approx. 15 Approx. 1012 Approx. 375 Unit
s s s s s
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(2) Master reception Figure 19-22. Master Reception (Interval of Interrupt Occurrence)
Start bit t1 T
Broadcasting Master address
P Slave address P A T t3 T A
Control
PA
Telegraph length
PA PA
Data
P
T
T t2
T
A
T t4
T
Communication starts A Data T t5 PA Data Data T t4 PA A
Communication start interrupt
End of communication End of frame
Remarks 1. T: Timing error P: Parity error A: ACK error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. (IEBus: at 6.29 MHz)
Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - timing error Communication start interrupt - end of communication Receive data read interval Symbol t1 t2 t3 t4 t5 MIN. Approx. 93 Approx. 1282 Approx. 15 Approx. 1012 Approx. 375 Unit
s s s s s
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(3) Slave transmission Figure 19-23. Slave Transmission (Interval of Interrupt Occurrence)
Start bit t1 T
Broadcasting Master address
P Slave address P A P T t3 P T
Control
PA
Telegraph length
PA A t7
Data T t5
PA U
T
T t2
T P A t6 t4 T
T
Communication starts Data T t7 PA Data U Data T PA A
Communication start interrupt
Status request
End of communication End of frame
Remarks 1. T: Timing error P: Parity error A: ACK error U: Underrun error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. (IEBus: at 6.29 MHz)
Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - timing error Communication start interrupt - status request Transmission data request interrupt interval Status request - timing error Status request - end of communication Symbol t1 t2 t3 t4 t5 t6 t7 MIN. Approx. 96 Approx. 1192 Approx. 15 Approx. 225 Approx. 375 Approx. 15 Approx. 787 Unit
s s s s s s s
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(4) Slave reception Figure 19-24. Slave Reception (Interval of Interrupt Occurrence)
Start bit t1 T
Broadcasting Master address
P Slave address P A P T A t3 PT
Control T
PA
Telegraph length
PA PA
Data T
P P
T
T t2
PA
T t4
Communication starts A Data T t5 PA O P Data Data T t4 PA OA P
Communication start interrupt
End of communication End of frame
Remarks 1. T: Timing error P: Parity error A: ACK error O: Overrun error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. (IEBus: at 6.29 MHz)
Item Communication starts - timing error Communication starts - communication start interrupt Communication start interrupt - timing error Communication start interrupt - end of communication Receive data read interval Symbol t1 t2 t3 t4 t5 MIN. Approx. 96 Approx. 1192 Approx. 15 Approx. 1012 Approx. 375 Unit
s s s s s
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Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Symbol VDD VPP AVDD BVDD EVDD AVSS BVSS EVSS Input voltage VI1 VI2 Analog input voltage Analog reference input voltage Output current, low VIAN AVREF IOL VDD pin Flash memory versions only, Note 1 AVDD pin BVDD pin EVDD pin AVSS pin BVSS pin EVSS pin Note 2 (BVDD pin) Note 3, RESET (EVDD pin) Note 4 (AVDD pin) AVREF pin Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, CLKOUT Total for P50 to P57, P60 to P65 Output current, high IOH Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, CLKOUT Total for P50 to P57, P60 to P65 Output voltage VO1 VO2 Operating ambient temperature TA Note 2, CLKOUT (BVDD pin) Note 3 (EVDD pin) Normal operation mode Flash memory programming mode Flash memory programming mode Storage temperature Tstg Mask ROM versions Flash memory versions
Note 6
Conditions
Ratings -0.5 to +7.0 -0.5 to +8.5 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to BVDD + 0.5 -0.5 to EVDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to AVDD + 0.5 4.0 25
Note 5
Unit V V V V V V V V V V V V mA mA
Note 5
Note 5
Note 5
25
mA
25 25 -4.0 -25
mA mA mA mA
-25
mA
-25 -25 -0.5 to BVDD + 0.5 -0.5 to EVDD + 0.5 -40 to +85 10 to +85 -20 to +85 -65 to +150 -40 to +125
Note 5
mA mA V V C C
Note 5
Note 7
C C
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Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 1 ms or more after VDD has reached the lower-limit value (4.0 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (4.0 V) of the operating voltage range of VDD (see b in the figure below).
VDD
4.0 V 0V a b
VPP 4.0 V 0V
2. Ports 4, 5, 6, 9, and their alternate-function pins 3. Ports 0, 1, 2, 3, 10, 11, and their alternate-function pins 4. Ports 7, 8, and their alternate-function pins 5. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 6. K rank products of the PD70F3033A, 70F3033AY and K and E rank products of the PD70F3035A, 70F3035AY (The rank is indicated by the letter appearing as the 5th digit from the left in the lot number.) 7. E rank products of the PD70F3033A and 70F3033AY, P rank products of the PD70F3035A and 70F3035AY, and the PD70F3032A, 70F3032AY, 70F3037A, 70F3037AY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, and 70F3037HY (The rank is indicated by the letter appearing as the 5th digit from the left in the lot number.) Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation.
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Capacitance (TA = 25C, VDD = AVDD = BVDD = EVDD = VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Operating Conditions (1) Operating frequency
Operating Frequency (fXX) VDD Note 1 2 to 20 MHz (V850SB1) 2 to 17 MHz (V850/SB1) 2 to 19 MHz (H versions of V850/SB2) 2 to 17 MHz (H versions of V850/SB2) 2 to 13 MHz (A and B versions of V850/SB2) 32.768 kHz Other than IDLE mode IDLE mode 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 3.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V - AVDD Note 2 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V - Note 4 Note 3 BVDD EVDD Remark
Notes 1. When A/D converter is used 2. When A/D converter is not used 3. In STOP mode (when only watch timer is operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or restoring from STOP mode must be performed at VDD = 4.0 V min. 4. Shifting to IDLE mode or restoring from IDLE mode must be performed at VDD = 4.0 V min. (2) CPU operating frequency
Parameter CPU operating frequency Symbol fCPU Conditions Main clock operation (V850/SB1) Main clock operation (H versions of V850/SB2) Main clock operation (A and B versions of V850/SB2) Subclock operation MIN. 0.25 0.25 TYP. MAX. 20 19 Unit MHz MHz
0.25
13
MHz
32.768
kHz
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Recommended Oscillator (1) Main clock oscillator (TA = -40 to +85C) (a) Connection of ceramic resonator or crystal resonator
X1 Rf
X2 Rd C1
C2
Parameter Oscillation frequency (V850/SB1) Oscillation frequency (H versions of V850/SB2) Oscillation frequency (A and B versions of V850/SB2) Oscillation stabilization time
Symbol fXX
Conditions
MIN. 2
TYP.
MAX. 20
Unit MHz
fXX
2
19
MHz
fXX
2
13
MHz
- -
Upon reset release Upon STOP mode release
219/fXX Note
s s
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). Cautions 1. The main clock oscillator operates on the output voltage of the on-chip regulator (3.0 V/3.3 V (for details, refer to CHAPER 16 REGULATOR). External clock input is prohibited. 2. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. Sufficiently evaluate the matching between the V850/SB1 and V850/SB2 devices and the resonator.
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(i)
Murata Mfg. Co., Ltd.: Ceramic resonator (TA = -40 to +85C)
Part Number Oscillation Frequency fXX (MHz) 6.290 Recommended Circuit Constant Oscillation Voltage Range MIN. (V) 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Manufacturer
C1 (pF) On-chip On-chip
C2 (pF) On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip 10 On-chip On-chip On-chip
Rf (k) - - - - - - - - - - - 22 k
Rd (k) 0 0 0 0 0 0 0 0 0 0 0 0
Murata Mfg. CSTLS6M29G53-B0 Co., Ltd. (A, CSTCR6M29G53-R0 B versions of CSTLA12M5T55001-B0 V850/SB2) CSTCV12M5T54J01-R0 Murata Mfg. Co., Ltd. (V850/SB1) CSTLS8M00G56-B0 CSTCC8M00G56-R0 CSTLA12M5T55-B0 CSTCV12M5T54J-R0 CSALS16M0X55-B0 CSTCV16M0X51J-R0 CSTLS20M0X51-B0 CSTCW20M0X51-R0
12.583
On-chip On-chip
8.00
On-chip On-chip
12.5
On-chip On-chip
16.00
10 On-chip
20.00
On-chip On-chip
Caution
This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850/SB1 and V850/SB2 so that the internal operating conditions are within the specifications of the DC and AC characteristics.
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(2) Subclock oscillator (TA = -40 to +85C) (a) Connection of crystal resonator
XT1
XT2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXT -
Conditions
MIN. 32
TYP. 32.768 10
MAX. 35
Unit kHz s
Cautions 1. The subclock oscillator operates on the output voltage of the on-chip regulator (3.0 V/3.3 V (for details, refer to CHAPTER 16 REGULATOR)). External clock input is prohibited. 2. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Sufficiently evaluate the matching between the V850/SB1 and V850/SB2 devices and the resonator.
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DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Input voltage, high Symbol VIH1 Note 1 Conditions 4.0 V BVDD 5.5 V 3.0 V BVDD < 4.0 V VIH2 Note 2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V VIH3 Note 3, RESET 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH1 Note 4 Note 1 Note 2 Note 3, RESET Note 4 Note 1, CLKOUT 3.0 V BVDD 5.5 V, IOH = -100 A 4.0 V BVDD 5.5 V, IOH = -3 mA VOH2 Notes 2, 3 3.0 V EVDD 5.5 V, IOH = -100 A 4.0 V EVDD 5.5 V, IOH = -3 mA Output voltage, low VOL IOL = 3 mA, 3.0 V BVDD, EVDD 5.5 V IOL = 3 mA, 4.0 V BVDD, EVDD 5.5 V VPP power supply voltage VPP1 Normal operation (A and B versions of V850/SB2) Normal operation (V850/SB1 and H versions of V850/SB2) Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VI = VDD = BVDD = EVDD = AVDD VI = 0 V VO = VDD = BVDD = EVDD = AVDD VO = 0 V VIN = 0 V 10 30 0 MIN. 0.7BVDD 0.8BVDD 0.7EVDD 0.8EVDD 0.7EVDD 0.8EVDD 0.7AVDD BVSS EVSS EVSS AVSS BVDD - 0.5 TYP. MAX. BVDD BVDD EVDD EVDD EVDD EVDD AVDD 0.3BVDD 0.3EVDD 0.3EVDD 0.3AVDD Unit V V V V V V V V V V V V
BVDD - 1.0
V
EVDD - 0.5
V
EVDD - 1.0
V
0.5
V
0.4
V
0.54
V
0
0.6
V
5 -5 5 -5 100
A A A A
k
Notes 1. Ports 4, 5, 6, 9, and their alternate-function pins 2. P11, P14, P21, P24, P34, P35, P110 to P113, and their alternate-function pins 3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P100 to P107, and their alternate-function pins 4. Ports 7, 8, and their alternate-function pins
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DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Supply current Symbol IDD1 IDD2 IDD3 Conditions In normal operation mode In HALT modeNote 1 In IDLE modeNote 2 In STOP mode Watch timer operating
Note 1
MIN.
TYP. 25 10 1
MAX. 40 20 4
Unit mA mA mA
PD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY, 703032A, 703032AY, 703032B, 703032BY, 703033A, 703033AY, 703033B, 703033BY, 703036H, 703036HY, 703037H, 703037HY
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped, XT1 = VSS
Note 3
70
A A A A
mA mA mA
Note 4
70
IDD5
In normal operation mode (subclock operation)Note 5 In IDLE mode (subclock operation)Note 5 In normal operation modeNote 6 In HALT mode In IDLE modeNote 7 In STOP mode
Note 6
50
150
IDD6
13 15 6 1
70 25 13 4
PD703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY, 703035B, 703035BY, 703037A, 703037AY
IDD1 IDD2 IDD3
Watch timer operating
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped, XT1 = VSS
Note 8
70
A A A A
Note 9
70
IDD5
In normal operation mode (subclock operation)Note 5 In IDLE mode (subclock operation)Note 5
50
150
IDD6
13
70
Notes 1. fCPU = fXX = 20 MHz, all peripheral functions operating (fXX = 19 MHz in the PD703036H, 703036HY, 703037H, and 703037HY) 2. fXX = 20 MHz (fXX = 19 MHz in the PD703036H, 703036HY, 703037H, and 703037HY) 3. IDD4 = 13 A (PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY) IDD4 = 10 A (PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703036H, 703036HY, 703037H, 703037HY) 4. IDD4 = 8 A (PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY) IDD4 = 5 A (PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703036H, 703036HY, 703037H, 703037HY) 5. fCPU = fXT = 32.768 kHz, main clock oscillator stopped 6. fCPU = fXX = 13 MHz, all peripheral functions operating 7. fXX = 13 MHz 8. IDD4 = 13 A (PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY) IDD4 = 10 A (PD703034B, 703034BY, 703035B, 703035BY) 9. IDD4 = 8 A (PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY) IDD4 = 5 A (PD703034B, 703034BY, 703035B, 703035BY) Remark TYP. values are reference values for when TA = 25C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current consumed by the output buffer is not included.
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DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Supply current Symbol Conditions In normal operation modeNote 1 Note 2 Note 3 Note 4 In HALT mode
Note 1
MIN.
TYP. 33 37 42 10 12 14 1
MAX. 60 65 70 20 24 28 4
Unit mA mA mA mA mA mA mA
PD70F3030B, 70F3030BY, IDD1 70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY, IDD2 70F3036H, 70F3036HY, 70F3037H, 70F3037HY
Note 2 Note 3 Note 4
IDD3
In IDLE modeNote 5 In STOP mode
Watch timer operating
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped, XT1 = VSS
Note 6
100
A A A A A A
Note 7
100
IDD5
In normal operation mode Notes 2, 3 (subclock operation)Note 8 Note 4 In IDLE mode (subclock operation)Note 8 Notes 2, 3 Note 4
200 300 90 170
600 900 180 340
IDD6
Notes 1. fCPU = fXX = 20 MHz, all peripheral functions operating (fXX = 19 MHz in the PD70F3036H, 70F3036HY, 70F3037H, and 70F3037HY) 2. PD70F3033A, 70F3033AY, 70F3033B, 70F3033BY 3. PD70F3030B, 70F3030BY, 70F3036H, 70F3036HY 4. PD70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3037H, 70F3037HY 5. fXX = 20 MHz (fXX = 19 MHz in the PD70F3036H, 70F3036HY, 70F3037H, and 70F3037HY) 6. IDD4 = 13 A (PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY) IDD4 = 10 A (PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY) 7. IDD4 = 8 A (PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY) IDD4 = 5 A (PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY) 8. fCPU = fXT = 32.768 kHz, main clock oscillator stopped Remark TYP. values are reference values for when TA = 25C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current consumed by the output buffer is not included.
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DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Supply current Symbol Conditions In normal operation modeNote 1 In HALT modeNote 1 Note 2 Note 3 Note 2 Note 3 IDD3 In IDLE modeNote 4 In STOP mode Watch timer operating MIN. TYP. 25 30 7 9 1 MAX. 48 58 15 20 4 Unit mA mA mA mA mA
PD70F3035A, 70F3035AY, IDD1 70F3035B, 70F3035BY, 70F3037A, 70F3037AY IDD2
IDD4
Watch timer, subclock oscillator operating Subclock oscillator stopped, XT1 = VSS
Note 5
100
A A A A A A
Note 6
100
IDD5
In normal operation mode (subclock operation)Note 7 In IDLE mode (subclock operation)Note 7
Note 2 Note 3 Note 2 Note 3
200 300 90 170
600 900 180 340
IDD6
Notes 1. fCPU = fXX = 13 MHz, all peripheral functions operating 2. PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY 3. PD70F3037A, 70F3037AY 4. fXX = 13 MHz 5. IDD4 = 13 A (PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY) IDD4 = 10 A (PD70F3035B, 70F3035BY) 6. IDD4 = 8 A (PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY) IDD4 = 5 A (PD70F3035B, 70F3035BY) 7. fCPU = fXT = 32.768 kHz, main clock oscillator stopped Remark TYP. values are reference values for when TA = 25C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current consumed by the output buffer is not included.
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Data Retention Characteristics (TA = -40 to +85C, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Data retention voltage Symbol VDDDR Conditions STOP mode (all functions not operating) TA = -40 to +85C STOP mode (all functions not operating) TA = -40 to +45C STOP mode (all functions not operating) TA = -10 to +45C Data retention current IDDDR VDD = VDDDR, XT1 = VSS (Subclock stopped) Mask ROM versions Note 2 Note 3 MIN. 2.7
Note 1
TYP.
MAX. 5.5
Unit V
2.5Note 1
5.5
V
2.0Note 1
5.5
V
5 8 5 8 200 200 0
70 70 100 100
A A A A s s
ms
Flash memory Note 4 versions Note 5
Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (from STOP mode setting) STOP mode release signal input time Data retention high-level input voltage Data retention low-level input voltage
tRVD tFVD tHVD
tDREL VIHDR VILDR All input ports All input ports
0 0.9VDDDR 0 VDDDR 0.1VDDDR
ms V V
Notes 1. In STOP mode (when only watch timer is operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or restoring from STOP mode must be performed at VDD = 4.0 V min. 2. PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY 3. PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY, 703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY 4. PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY 5. PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY, 70F3035A, 70F3035AY, 70F3037A, 70F3037AY
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Remark
TYP. values are reference values for when TA = 25C.
Setting STOP mode
4.0 VNote VDD tFVD tHVD V DDDR tRVD tDREL
RESET (input)
V IHDR
Stop mode release interrupt (NMI, etc.) (Release by falling edge)
V IHDR
Stop mode release interrupt (NMI, etc.) (Release by rising edge) V ILDR
Note VDD = 4.0 V indicates the minimum operating voltage of the V850/SB1 and V850/SB2.
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AC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V) AC Test Input Measurement Point (VDD: EVDD, BVDD, AVDD)
VDD Input signal 0V
VIH Measurement points VIL
VIH VIL
AC Test Output Measurement Points (VDD: EVDD, BVDD)
VDD Output signal 0V
VOH Measurement points VOL
VOH VOL
Load Conditions
DUT (Device under test) CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
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(1) Clock timing (a) TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V
Parameter CLKOUT output cycle Symbol <1> tCYK V850/SB1 H versions of V850/SB2 A and B versions of V850/SB2 CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time <2> <3> <4> <5> tWKH tWKL tKR tKF Conditions MIN. 50 ns 52.6 ns 76.9 ns 0.4tCYK - 12 0.4tCYK - 12 12 12 MAX. 31.2 s 31.2 s 31.2 s ns ns ns ns Unit
(b) TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V
Parameter CLKOUT output cycle Symbol <1> tCYK V850/SB1 H versions of V850/SB2 A and B versions of V850/SB2 CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time <2> <3> <4> <5> tWKH tWKL tKR tKF Conditions MIN. 58.8 ns 58.8 ns 76.9 ns 0.4tCYK - 15 0.4tCYK - 15 15 15 MAX. 31.2 s 31.2 s 31.2 s ns ns ns ns Unit
<1> <2> CLKOUT (output) <4> <5> <3>
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(2) Output waveform (other than port 4, port 5, port 6, port 9, and CLKOUT) (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = BVSS = EVSS = 0 V)
Parameter Output rise time Output fall time Symbol <6> <7> tOR tOF Conditions MIN. MAX. 20 20 Unit ns ns
<6>
<7>
Output signal
(3) Reset timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter RESET pin high-level width RESET pin low-level width Symbol <8> <9> tWRSH tWRSL Conditions MIN. 500 500 MAX. Unit ns ns
<8>
<9>
RESET (input)
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(4) Bus timing (a) Clock asynchronous (TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float delay time from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time (to ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width Bus output delay time from HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <33> <34> <35> <36> <37> tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 15 -6 (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 32 (1 + n)T - 32 (1 + n)T - 25 T - 20 1.5T - 40 (1.5 + n)T - 40 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 22 T - 15 10 Conditions MIN. 0.5T - 16 0.5T - 15 0 (2 + n)T - 40 (1 + n)T - 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after a read cycle (0 or 1). 4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
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(b) Clock asynchronous (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Symbol <10> <11> tSAST tHSTA Note 1 Note 2 Address float delay time from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time (to ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width Bus output delay time from HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <33> <34> <35> <36> <37> tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 25 -6 (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 45 (1 + n)T - 45 (1 + n)T - 35 T - 25 1.5T - 55 (1.5 + n)T - 55 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 35 T - 15 10 Conditions MIN. 0.5T - 20 0.5T - 20 0.5T - 22 0 (2 + n)T - 50 (1 + n)T - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1. PD703031A, 703031AY, 703031B, 703031BY, 703033A, 703033AY, 703033B, 703033BY, 703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY, 703035B, 703035BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY 2. PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after a read cycle (0 or 1). 4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
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(c) Clock synchronous (TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. 0 -12 MAX. 19 10 Unit ns ns
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
0 0 20 5
19 19
ns ns ns ns
19 20 5 20 5 19
ns ns ns ns ns ns
<50>
tDKHA
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
(d) Clock synchronous (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. 0 -16 MAX. 22 10 Unit ns ns
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
0 0 20 5
19 22
ns ns ns ns
22 24 5 24 5 19
ns ns ns ns ns ns
<50>
tDKHA
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
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(e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
CLKOUT (output)
T2
TW
T3
<38>
A1 to A15 (output) A16 to A21 (output) Note (output)
<13> <39>
<42>
<43>
AD0 to AD15 (I/O)
Address
Data
<40> <10> <11> <16> <40>
ASTB (output)
<21>
<41> <12> <15> <14>
<41> <18> <17> <19>
DSTB, RD (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remarks 1. The broken lines indicate high impedance. 2. WRL and WRH are high level.
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(f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
CLKOUT (output)
T2
TW
T3
<38>
A1 to A15 (output) A16 to A21 (output) Note (output)
<44>
AD0 to AD15 (I/O)
Address
Data
<40> <10> <11> <40>
ASTB (output)
<21>
<41> <22> <15> <23>
<41> <18> <24>
DSTB, WRL, WRH (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remarks 1. The broken lines indicate high impedance. 2. RD is high level.
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(g) Bus hold timing
TH
CLKOUT (output)
TH
TH
TH
TI
<47> <47> <48> HLDRQ (input) <50> <36> HLDAK (output) <34> <49>
A16 to A21 (output) Note (output)
<33>
<50> <37>
<35>
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
ASTB (output)
DSTB, RD (output) WRL, WRH (output)
Note R/W, UBEN, LBEN Remark The broken lines indicate high impedance.
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(5) Interrupt timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter NMI high-level width NMI low-level width INTPn high-level width Symbol <51> <52> <53> tWNIH tWNIL tWITH n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination INTPn low-level width <54> tWITL n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination Conditions MIN. 500 500 500 MAX. Unit ns ns ns
3T + 20 3Tsmp + 20
ns
ns
500
ns
3T + 20 3Tsmp + 20
ns
ns
Remarks 1. T = 1/fXX 2. Tsmp = Noise elimination sampling clock cycle
<51>
<52>
NMI (input)
<53>
<54>
INTPn (input)
Remark n = 0 to 6
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(6) RPU timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter TIn0, TIn1 high-level width TIn0, TIn1 low-level width TIm high-level width TIm low-level width Symbol <55> <56> <57> <58> tTIHn tTILn tTIHm tTILm Conditions n = 0, 1 n = 0, 1 m = 2 to 5 m = 2 to 5 MIN. 2Tsam + 20Note 2Tsam + 20 3T + 20 3T + 20
Note
MAX.
Unit ns ns ns ns
Note Tsam can select the following count clocks by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0, n1 (PRMn0, PRMn1). When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T. Remark T = 1/fXX
<55> <56>
TIn0, TIn1 (input)
<57>
<58>
TIm (input)
Remark
n = 0, 1 m = 2 to 5
(7) Asynchronous serial interface (UART0, UART1) timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol <59> <60> <61> tKCY13 tKH13 tKL13 Conditions MIN. 200 80 80 MAX. Unit ns ns ns
Remark n = 0, 1
<59> <60> <61>
ASCKn (input)
Remark n = 0, 1
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(8) 3-wire serial interface (CSI0 to CSI3) timing (a) Master mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <62> <63> <64> <65> <66> <67> tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
Remark n = 0 to 3 (b) Slave mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = VSS = 0 V)
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <62> <63> <64> <65> <66> <67> tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 4.0 V EVDD 5.5 V Note 1 Note 2 3.0 V EVDD < 4.0 V Conditions MIN. 400 140 140 50 50 60 70 100 MAX. Unit ns ns ns ns ns ns ns ns
Notes 1. PD703031A, 703031AY, 703031B, 703031BY, 703033A, 703033AY, 703033B, 703033BY, 703034A, 703034AY, 703034B, 703034BY, 703035A, 703035AY, 703035B, 703035BY, 70F3033A, 70F3033AY, 70F3033B, 70F3033BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY 2. PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 703036H, 703036HY, 703037A, 703037AY, 703037H, 703037HY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY
Remark n = 0 to 3
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<62> <63> <64>
SCKn (I/O)
<65>
<66>
SIn (input)
Input data
<67>
SOn (output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 3
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(9) 3-wire variable length serial interface (CSI4) timing (a) Master mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter SCK4 cycle Symbol <68> tKCY1 Conditions 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 high-level width <69> tKH1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 low-level width <70> tKL1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 setup time (to SCK4) <71> tSIK1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output <72> <73> tKSI1 tKSO1 MIN. 200 400 60 140 60 140 25 50 20 55 MAX. Unit ns ns ns ns ns ns ns ns ns ns
(b) Slave mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter SCK4 cycle Symbol <68> tKCY2 Conditions 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 high-level width <69> tKH2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 low-level width <70> tKL2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 setup time (to SCK4) <71> tSIK2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output <72> <73> tKSI2 tKSO2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V MIN. 200 400 60 140 60 140 25 50 20 55 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
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<68> <69> <70>
SCK4 (I/O)
<71>
<72>
SI4 (input)
Input data
<73>
SO4 (output)
Output data
Remark
The broken lines indicate high impedance.
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(10) I C bus mode (Y versions only) (1/2) (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus-free time (between stop/start conditions) Hold timeNote 1 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I2C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line <80> <81> tSU:DAT tR - <74> fCLK tBUF 0 4.7 MAX. 100 - High-Speed Mode MIN. 0 1.3 MAX. 400 - kHz Unit
2
s s s s s s
<75> <76> <77> <78>
tHD:STA tLOW tHIGH tSU:STA
4.0 4.7 4.0 4.7
- - - -
0.6 1.3 0.6 0.6
- - - -
<79>
tHD:DAT
5.0
-
-
-
0Note 2 250 -
- - 1000
0Note 2 100
Note 4
0.9Note 3 -
Note 5
s
ns ns
20 + 0.1Cb
300
<82>
tF
-
300
20 + 0.1CbNote 5
300
ns
<83> <84>
tSU:STO tSP
4.0 -
- -
0.6 0
- 50
s
ns
-
Cb
-
400
-
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin.. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the high-speed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF)
2 2 2 2
Remark n = 0, 1
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(10) I C bus mode (Y versions only) (2/2)
2
<76>
<77>
SCLn (I/O)
<82> <75> <81> <79> <80> <78> <75> <84> <83>
SDAn (I/O)
<74> <81> <82>
Stop condition
Start condition
Restart condition
Stop condition
Remark
n = 0, 1
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Resolution Overall error
Note 1
Symbol - - ADM2 = 00H ADM2 = 01H
Conditions
MIN. 10
TYP. 10
MAX. 10 0.6 1.0
Unit bit %FSR %FSR
Conversion time Zero-scale errorNote 1 Full-scale error
Note 1
tCONV
5
10 0.4
s
%FSR %FSR %FSR LSB LSB LSB LSB V V V mA mA mA
ADM2 = 00H ADM2 = 01H
0.4 0.6 4.0 6.0 4.0 6.0 4.5 4.5 AVSS 1 5.5 5.5 AVREF 2 6 8
Integral linearity error
Note 2
ADM2 = 00H ADM2 = 01H
Differential linearity error
Note 2
ADM2 = 00H ADM2 = 01H
Analog reference voltage Analog power supply voltage Analog input voltage AVREF input current AVDD power supply current
AVREF AVDD VIAN AIREF AIDD
AVREF = AVDD
Operating current
ADM2 = 00H ADM2 = 01H
3 4
Notes 1. Excluding quantization error (0.05 %FSR) 2. Excluding quantization error (0.5 LSB) Remarks 1. LSB: Least Significant Bit FSR: Full Scale Range 2. ADM2: A/D converter mode register 2
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IEBus Controller Characteristics (V850/SB2 only) (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter IEBus system clock frequency Symbol fS Conditions Communication mode: fixed to mode 1 MIN. TYP. 6.0Note 1 6.29
Notes 1, 2
MAX.
Unit MHz MHz
Notes 1. 6.0 MHz and 6.29 MHz can not be used together for the IEBus system clock frequency 2. Although the system clock specified in the IEBus specification is 6.0 MHz, operation is guaranteed at 6.29 MHz system clock in the V850/SB2.
Regulator (TA = -40 to +85C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter Output stabilization time Symbol tREG Conditions Stabilization capacitance C = 1 F (Connected to REGC pin) MIN. 1 TYP. MAX. Unit ms
Cautions 1. Be sure to start inputting supply voltage VDD when RESET = VSS = EVSS = BVSS = 0 V (the above state), and make RESET high level after the tREG period has elapsed. 2. If supply voltage BVDD or EVDD is input before the tREG period has elapsed following the input of supply voltage VDD, note that data may be driven from the pins until the tREG period has elapsed because the I/O buffers' power supply was turned on while the circuit was in an undefined state.
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Flash Memory Programming Mode (1) PD70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY Write/erase characteristics (TA = -20 to 85C, VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter VPP power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP = VPP2, fXX = 20 MHz VPP = VPP2 Note 2 When the step erase time = 0.2 s, Note 3 Note 4 When the writeback time = 1 ms, Note 5 1 300 0.2 20 MIN. 7.5 TYP. 7.8 MAX. 8.1 Unit V
VDD power supply current VPP power supply current Step erase time Overall erase time per area Writeback time Number of writebacks per writeback command
IDD IPP tER tERA
Note 1 100
mA mA s s/area
tWB CWB
ms Count/ writeback command Count
Number of erase/writebacks Step writing time Overall writing time per word Number of rewrites per area
CERWB
16
tWR tWRW
Note 6 When the step writing time = 20 s (1 word = 4 bytes), Note 7 1 erase + 1 write after erase = 1 rewrite, Note 8 20
20 200
s s/word
Count/area
CERWR
100
Notes 1. IDD = 63 (PD70F3033B, 70F3033BY), IDD = 68 (PD70F3030B, 70F3030BY), IDD = 73 (PD70F3032A, 70F3032AY, 70F3032B, 70F3032BY) 2. The recommended setting value of the step erase time is 0.2 s. 3. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 4. The recommended setting value of the writeback time is 1 ms. 5. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 6. The recommended setting value of the step writing time is 20 s. 7. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 8. When writing initially to shipped products, both "erase to write" and "write only" are counted as one rewrite. Example (P: Write, E: Erase) Shipped product P E P E P: Shipped product E P E P E P: 3 rewrites 3 rewrites
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH Area 2 = 040000H to 05FFFFH Area 3 = 060000H to 07FFFFH
PD70F3030B, 70F3030BY: Areas 0 to 2 PD70F3032A, 70F3032AY, 70F3032B, 70F3032BY: Areas 0 to 3 PD70F3033B, 70F3033BY: Areas 0 and 1
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(2) PD70F3033A, 70F3033AY Write/erase characteristics (TA = 10 to 85C TA = -20 to +85C ... K rank product, ... E rank product,
VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter VPP power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP = VPP2, fXX = 20 MHz VPP = VPP2 Note 1 When the step erase time = 0.2 s, Note 2 Note 3 When the writeback time = 1 ms, Note 4 1 300 0.2 20 MIN. 7.5 TYP. 7.8 MAX. 8.1 Unit V
VDD power supply current VPP power supply current Step erase time Overall erase time per area Writeback time Number of writebacks per writeback command
IDD IPP tER tERA
63 100
mA mA s s/area
tWB CWB
ms Count/ writeback command Count
Number of erase/writebacks Step writing time Overall writing time per word Number of rewrites per area
CERWB
16
tWR tWRW
Note 5 When the step writing time = 20 s (1 word = 4 bytes), Note 6 1 erase + 1 write after erase = 1 rewrite, Note 7 20
20 200
s s/word
Count/area
CERWR
Note 8
Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 1 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 7. When writing initially to shipped products, both "erase to write" and "write only" are counted as one rewrite for. Example (P: Write, E: Erase) Shipped product P E P E P: Shipped product E P E P E P: 8. K rank product: 20 writes/area E rank product: 100 writes/area Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH 3 rewrites 3 rewrites
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(3) PD70F3035A, 70F3035AY Write/erase characteristics (TA = 10 to 85C TA = -20 to +85C ... K, E rank product, ... P rank product,
VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter VPP power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP = VPP2, fXX = 13 MHz VPP = VPP2 Note 1 When the step erase time = 0.2 s, Note 2 Note 3 When the writeback time = 1 ms, Note 4 1 300 0.2 20 MIN. 7.5 TYP. 7.8 MAX. 8.1 Unit V
VDD power supply current VPP power supply current Step erase time Overall erase time per area Writeback time Number of writebacks per writeback command
IDD IPP tER tERA
51 100
mA mA s s/area
tWB CWB
ms Count/ writeback command Count
Number of erase/writebacks Step writing time Overall writing time per word Number of rewrites per area
CERWB Note 5 When the step writing time = 20 s (1 word = 4 bytes), Note 6 1 erase + 1 write after erase = 1 rewrite, Note 7 20 Note 8
16
tWR tWRW
20 200
s s/word
Count/area
CERWR
Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 1 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 7. When writing initially to shipped products, both "erase to write" and "write only" are counted as one rewrite for. Example (P: Write, E: Erase) Shipped product P E P E P: Shipped product E P E P E P: 8. K, E rank product: 20 writes/area P rank product: 100 writes/area Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH 3 rewrites 3 rewrites
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(4) PD70F3035B, 70F3035BY, 70F3037A, 70F3037AY, Write/erase characteristics (TA = -20 to +85C, VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter VPP power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP = VPP2, fXX = 13 MHz VPP = VPP2 Note 2 When the step erase time = 0.2 s, Note 3 Note 4 When the writeback time = 1 ms, Note 5 1 300 0.2 20 MIN. 7.5 TYP. 7.8 MAX. 8.1 Unit V
VDD power supply current VPP power supply current Step erase time Overall erase time per area Writeback time Number of writebacks per writeback command
IDD IPP tER tERA
Note 1 100
mA mA s s/area
tWB CWB
ms Count/ writeback command Count
Number of erase/writebacks Step writing time Overall writing time per word Number of rewrites per area
CERWB
16
tWR tWRW
Note 6 When the step writing time = 20 s (1 word = 4 bytes), Note 7 1 erase + 1 write after erase = 1 rewrite, Note 8 20
20 200
s s/word
Count/area
CERWR
100
Notes 1. IDD = 51 (PD70F3035B, 70F3035BY), IDD = 61 (PD70F3037A, 70F3037AY) 2. The recommended setting value of the step erase time is 0.2 s. 3. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 4. The recommended setting value of the writeback time is 1 ms. 5. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 6. The recommended setting value of the step writing time is 20 s. 7. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 8. When writing initially to shipped products, both "erase to write" and "write only" are counted as one rewrite. Example (P: Write, E: Erase) Shipped product P E P E P: Shipped product E P E P E P: 3 rewrites 3 rewrites
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH Area 2 = 040000H to 05FFFFH Area 3 = 060000H to 07FFFFH
PD70F3035B, 70F3035BY: Areas 0 and 1 PD70F3037A, 70F3037AY: Areas 0 to 3
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ELECTRICAL SPECIFICATIONS
(5) PD70F3036H, 70F3036HY, 70F3037H, 70F3037HY Write/erase characteristics (TA = -20 to +85C, VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter VPP power supply voltage Symbol VPP2 Conditions During flash memory programming When VPP = VPP2, fXX = 19 MHz VPP = VPP2 Note 2 When the step erase time = 0.2 s, Note 3 Note 4 When the writeback time = 1 ms, Note 5 1 300 0.2 20 MIN. 7.5 TYP. 7.8 MAX. 8.1 Unit V
VDD power supply current VPP power supply current Step erase time Overall erase time per area Writeback time Number of writebacks per writeback command
IDD IPP tER tERA
Note 1 100
mA mA s s/area
tWB CWB
ms Count/ writeback command Count
Number of erase/writebacks Step writing time Overall writing time per word Number of rewrites per area
CERWB
16
tWR tWRW
Note 6 When the step writing time = 20 s (1 word = 4 bytes), Note 7 1 erase + 1 write after erase = 1 rewrite, Note 8 20
20 200
s s/word
Count/area
CERWR
100
Notes 1. IDD = 68 (PD70F3036H, 70F3036HY), IDD = 73 (PD70F3037H, 70F3037HY) 2. The recommended setting value of the step erase time is 0.2 s. 3. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 4. The recommended setting value of the writeback time is 1 ms. 5. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 6. The recommended setting value of the step writing time is 20 s. 7. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 8. When writing initially to shipped products, both "erase to write" and "write only" are counted as one rewrite. Example (P: Write, E: Erase) Shipped product P E P E P: Shipped product E P E P E P: 3 rewrites 3 rewrites
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH Area 2 = 040000H to 05FFFFH Area 3 = 060000H to 07FFFFH
PD70F3036H, 70F3036HY: Areas 0 to 2 PD70F3037H, 70F3037HY: Areas 0 to 3
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PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
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PACKAGE DRAWINGS
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
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RECOMMENDED SOLDERING CONDITIONS
The V850/SB1 and V850/SB2 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 22-1. Surface Mounting Type Soldering Conditions (1/5) (1) PD703031AGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14)
PD703031BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703031AYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703031BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703033AGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703033BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703033AYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703033BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703034AGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703034BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703034AYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703034BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703035AGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703035BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703035AYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703035BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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RECOMMENDED SOLDERING CONDITIONS
Table 22-1. Surface Mounting Type Soldering Conditions (2/5) (2) PD703030BGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703030BYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703036HGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14)
PD703036HYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) PD70F3033AGC-8EU: PD70F3033BGC-8EU: PD70F3033AYGC-8EU: PD70F3033BYGC-8EU: PD70F3035AGC-8EU: PD70F3035BGC-8EU: PD70F3035AYGC-8EU: PD70F3035BYGC-8EU:
Soldering Method
100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 to 72 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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Table 22-1. Surface Mounting Type Soldering Conditions (3/5)
(3)
PD703030BGF-xxx-3BA: PD703031AGF-xxx-3BA: PD703031BGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703035AGF-xxx-3BA: PD703035BGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703030BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20)
PD703035AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703035BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703036HGF-xxx-3BA: PD703037AGF-xxx-3BA: PD703037HGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703031AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703031BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703032AGF-xxx-3BA: PD703032BGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703036HYGF-xxx-3BA: 100-pin plastic QFP (14 x 20)
PD703032AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703032BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703033AGF-xxx-3BA: PD703033BGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703037AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703037HYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD70F3033AGF-3BA: PD70F3033BGF-3BA: PD70F3033AYGF-3BA: PD70F3033BYGF-3BA: PD70F3035AGF-3BA: PD70F3035BGF-3BA: PD70F3035AYGF-3BA: PD70F3035BYGF-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Recommended Condition Symbol IR35-207-2
PD703033AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703033BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703034AGF-xxx-3BA: PD703034BGF-xxx-3BA:
100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20)
PD703034AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703034BYGF-xxx-3BA: 100-pin plastic QFP (14 x 20)
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once Preheating temperature: 120C max. (package surface temperature) Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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RECOMMENDED SOLDERING CONDITIONS
Table 22-1. Surface Mounting Type Soldering Conditions (4/5)
(4) PD70F3030BGF-3BA:
100-pin plastic QFP (14 x 20)
PD70F3030BYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3032AGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3032BGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3032AYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3032BYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3036HGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3036HYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3037AGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3037HGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3037AYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3037HYGF-3BA: 100-pin plastic QFP (14 x 20)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-203-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 20 to 72 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 20 to 72 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: once Preheating temperature: 120C max. (package surface temperature) Exposure limit: 3 daysNote (after that, prebake at 125C for 20 to 72 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-203-2
Wave soldering
WS60-203-1
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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Table 22-1. Surface Mounting Type Soldering Conditions (5/5)
(5) PD70F3030BGC-8EU:
100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14)
PD70F3030BYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD70F3036HGC-8EU: PD70F3036HYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Method Soldering Conditions Recommended Condition Symbol IR30-103-2
Infrared reflow
Package peak temperature: 230C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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APPENDIX A
NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the shape of parts mounted on the target system as shown below. Figure A-1. 100-Pin Plastic LQFP (Fine Pitch) (14 x 14)
Side view
In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703037-MC-EM1
178 mm
Note
Conversion connector YQGUIDE YQPACK100SD NQPACK100SD
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm). Top view
IE-703002-MC
Target system
Pin 1 position
IE-703037-MC-EM1 YQPACK100SD, NQPACK100SD, YQGUIDE
Connection condition diagram
IE-703037-MC-EM1 Connect to IE-703002-MC. Pin 1 position
75 mm
YQGUIDE YQPACK100SD NQPACK100SD
13.3 mm 31.84 mm 17.78 mm 25.4 mm 21.58 mm
Target system
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NOTES ON TARGET SYSTEM DESIGN
Figure A-2. 100-Pin Plastic QFP (14 x 20)
Side view
In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703037-MC-EM1
178 mm
Note
Conversion connector NEXB-100-SD/RB YQGUIDE YQPACK100RB NQPACK100RB
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) to this portion for adjusting the height (height: 3.2 mm). Top view
IE-703002-MC
NEXB-100-SD/RB
Target system
Pin 1 position
IE-703037-MC-EM1
8 mm
20 mm
YQPACK100RB, NQPACK100RB, YQGUIDE
Connection condition diagram
IE-703037-MC-EM1 Connect to IE-703002-MC. Pin 1 position
75 mm
NEXB-100-SD/RB
YQPACK100RB NQPACK100RB
33.2 mm
38 mm 20 mm 28 mm 18.5 mm
Target system
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APPENDIX B
REGISTER INDEX
(1/7) Symbol ADCR ADCRH ADIC ADM1 ADM2 ADS ASIM0 ASIM1 ASIS0 ASIS1 BCC BCR BRGC0 BRGC1 BRGCK4 BRGCN4 BRGMC00 BRGMC01 BRGMC10 BRGMC11 CCR CDR CORAD0 CORAD1 CORAD2 CORAD3 CORCN CORRQ CR00 CR01 CR10 CR11 CR20 CR23 CR30 A/D conversion result register A/D conversion result register H Interrupt control register A/D converter mode register 1 A/D converter mode register 2 Analog input channel specification register Asynchronous serial interface mode register 0 Asynchronous serial interface mode register 1 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Bus cycle control register IEBus control register Baud rate generator control register 0 Baud rate generator control register 1 Baud rate generator output clock selection register 4 Baud rate generator source clock selection register 4 Baud rate generator mode control register 00 Baud rate generator mode control register 01 Baud rate generator mode control register 10 Baud rate generator mode control register 11 IEBus communication count register IEBus control data register Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Correction control register Correction request register 16-bit capture/compare register 00 16-bit capture/compare register 01 16-bit capture/compare register 10 16-bit capture/compare register 11 8-bit compare register 2 16-bit compare register 23 (when TM2 and TM3 are connected in cascade) 8-bit compare register 3 Name Unit ADC ADC INTC ADC ADC ADC UART UART UART UART BCU IEBus UART UART CSI CSI UART UART UART UART IEBus IEBus CPU CPU CPU CPU CPU CPU Timer Timer Timer Timer Timer Timer Timer Page 433 433 162 to 164 435 437 437 402 402 403 403 134 561 404 404 425 424 405 405 405 405 582 565 521 521 521 521 519 520 203 204 203 204 236 250 236
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REGISTER INDEX
(2/7) Symbol CR40 CR45 CR50 CR60 CR67 CR70 CRC0 CRC1 CSIB4 CSIC0 CSIC1 CSIC2 CSIC3 CSIC4 CSIM0 CSIM1 CSIM2 CSIM3 CSIM4 CSIS0 CSIS1 CSIS2 CSIS3 DBC0 DBC1 DBC2 DBC3 DBC4 DBC5 DCHC0 DCHC1 DCHC2 DCHC3 DCHC4 DCHC5 DIOA0 DIOA1 DIOA2 8-bit compare register 4 16-bit compare register 45 (when TM4 and TM5 are connected in cascade) 8-bit compare register 5 8-bit compare register 6 16-bit compare register 67 (when TM6 and TM7 are connected in cascade) 8-bit compare register 7 Capture/compare control register 0 Capture/compare control register 1 Variable-length serial setting register 4 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Serial operation mode register 0 Serial operation mode register 1 Serial operation mode register 2 Serial operation mode register 3 Variable-length serial control register 4 Serial clock selection register 0 Serial clock selection register 1 Serial clock selection register 2 Serial clock selection register 3 DMA byte counter register 0 DMA byte counter register 1 DMA byte counter register 2 DMA byte counter register 3 DMA byte counter register 4 DMA byte counter register 5 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 DMA channel control register 4 DMA channel control register 5 DMA peripheral I/O address register 0 DMA peripheral I/O address register 1 DMA peripheral I/O address register 2 Name Unit Timer Timer Timer Timer Timer Timer Timer Timer CSI INTC INTC INTC INTC INTC CSI CSI CSI CSI CSI CSI CSI CSI CSI DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Page 236 250 236 236 250 236 207 207 423 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 270 270 270 270 422 270 270 270 270 459 459 459 459 459 459 460 460 460 460 460 460 453 453 453
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APPENDIX B
REGISTER INDEX
(3/7) Symbol DIOA3 DIOA4 DIOA5 DLR DMAIC0 DMAIC1 DMAIC2 DMAIC3 DMAIC4 DMAIC5 DMAS DR DRA0 DRA1 DRA2 DRA3 DRA4 DRA5 DWC ECR EGN0 EGP0 EIPC EIPSW FEPC FEPSW IEBIC1 IEBIC2 IECLK IEHCLK IIC0 IIC1 IICC0 IICC1 IICCE0 IICCE1 IICCL0 IICCL1 DMA peripheral I/O address register 3 DMA peripheral I/O address register 4 DMA peripheral I/O address register 5 IEBus telegraph length register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register DMA start factor expansion register IEBus data register DMA internal RAM address register 0 DMA internal RAM address register 1 DMA internal RAM address register 2 DMA internal RAM address register 3 DMA internal RAM address register 4 DMA internal RAM address register 5 Data wait control register Interrupt source register Falling edge specification register 0 Rising edge specification register 0 Status saving register during interrupt Status saving register during interrupt Status saving registers for NMI Status saving registers for NMI Interrupt control register Interrupt control register IEBus clock selection register IEBus high-speed clock selection register IIC shift register 0 IIC shift register 1 IIC control register 0 IIC control register 1 IIC clock expansion register 0 IIC clock expansion register 1 IIC clock selection register 0 IIC clock selection register 1 Name Unit DMAC DMAC DMAC IEBus INTC INTC INTC INTC INTC INTC DMAC IEBus DMAC DMAC DMAC DMAC DMAC DMAC BCU CPU INTC INTC CPU CPU CPU CPU IEBus IEBus IEBus IEBus IC IC IC IC I2C IC IC IC
2 2 2 2 2 2 2
Page 453 453 453 569 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 459 571 454 454 454 454 454 454 132 99 154, 477 154, 477 99 99 99 99 162 to 164 162 to 164 582 583 278, 291, 352 278, 291, 352 280, 339 280, 339 289, 350 289, 350 288, 349 288, 349
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REGISTER INDEX
(4/7) Symbol IICF0 IICF1 IICIC1 IICS0 IICS1 IICX0 IICX1 ISPR ISR KRIC KRM MAM MM NCC OSTS P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 PAC PAR PCC PF1 PF2 PF3 PF10 PIC0 PIC1 PIC2 PIC3 IIC flag register 0 IIC flag register 1 Interrupt control register IIC status register 0 IIC status register 1 IIC function expansion register 0 IIC function expansion register 1 In-service priority register IEBus interrupt status register Interrupt control register Key return mode register Memory address output mode register Memory expansion mode register Noise elimination control register Oscillation stabilization time selection register Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port alternate function control register IEBus partner address register Processor clock control register Port 1 function register Port 2 function register Port 3 function register Port 10 function register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Name Unit I2C IC IC IC I2C I2C IC INTC IEBus KR KR Port Port INTC WDT Port Port Port Port Port Port Port Port Port Port Port Port Port IEBus CG Port Port Port Port INTC INTC INTC INTC
2 2 2 2
Page 347 347 160 to 164 285, 344 285, 344 289, 350 289, 350 165 575 162 to 164 180 116 115 167 187, 262, 267 474 479 483 488 492 492 495 498 498 500 503 507 509 565 184 481 485 490 505 162 to 164 162 to 164 162 to 164 162 to 164
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REGISTER INDEX
(5/7) Symbol PIC4 PIC5 PIC6 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM9 PM10 PM11 PRCMD PRM00 PRM01 PRM10 PRM11 PSC PSW PU0 PU1 PU2 PU3 PU10 PU11 RTBH RTBL RTPC RTPM RX0 RX1 RXB0 RXB1 SAR SCR SERIC0 SERIC1 Interrupt control register Interrupt control register Interrupt control register Port 0 mode register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 9 mode register Port 10 mode register Port 11 mode register Command register Prescaler mode register 00 Prescaler mode register 01 Prescaler mode register 10 Prescaler mode register 11 Power save control register Program status word Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 2 Pull-up resistor option register 3 Pull-up resistor option register 10 Pull-up resistor option register 11 Real-time output buffer register H Real-time output buffer register L Real-time output port control register Real-time output port mode register Receive shift register 0 Receive shift register 1 Receive buffer register 0 Receive buffer register 1 IEBus slave address register IEBus success count register Interrupt control register Interrupt control register Name Unit INYC INTC INTC Port Port Port Port Port Port Port Port Port Port CG RPU RPU RPU RPU CG CPU Port Port Port Port Port Port RTO RTO RTO RTO UART UART UART UART IEBus IEBus INTC INTC Page 162 to 164 162 to 164 162 to 164 476 480 484 489 493 493 496 501 504 508 127 209 209 210 210 186 100 476 480 485 489 505 509 468 468 470 469 400 400 400 400 433, 564 581 162 to 164 162 to 164
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APPENDIX B
REGISTER INDEX
(6/7) Symbol SIO0 SIO1 SIO2 SIO3 SIO4 SSR STIC0 STIC1 SVA0 SVA1 SYC SYS TCL20 TCL21 TCL30 TCL31 TCL40 TCL41 TCL50 TCL51 TCL60 TCL61 TCL70 TCL71 TM0 TM1 TM2 TM23 TM3 TM4 TM45 TM5 TM6 TM67 TM7 TMC0 TMC1 TMC2 Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 2 Serial I/O shift register 3 Variable-length serial I/O shift register 4 IEBus slave status register Interrupt control register Interrupt control register Slave address register 0 Slave address register 1 System control register System status register Timer clock selection register 20 Timer clock selection register 21 Timer clock selection register 30 Timer clock selection register 31 Timer clock selection register 40 Timer clock selection register 41 Timer clock selection register 50 Timer clock selection register 51 Timer clock selection register 60 Timer clock selection register 61 Timer clock selection register 70 Timer clock selection register 71 16-bit timer register 0 16-bit timer register 1 8-bit counter 2 16-bit counter 23 (when TM2 and TM3 are connected in cascade) 8-bit counter 3 8-bit counter 4 16-bit counter 45 (when TM4 and TM5 are connected in cascade) 8-bit counter 5 8-bit counter 6 16-bit counter 67 (when TM6 and TM7 are connected in cascade) 8-bit counter 7 16-bit timer mode control register 0 16-bit timer mode control register 1 8-bit timer mode control register 2 Name Unit CSI CSI CSI CSI CSI IEBus INTC INTC IC IC CG CG Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer
2 2
Page 269 269 269 269 420 580 162 to 164 162 to 164 278, 291, 352 278, 291, 352 129 127 237 237 237 237 237 237 237 237 237 237 237 237 202 202 236 250 236 236 250 236 236 250 236 205 205 240
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REGISTER INDEX
(7/7) Symbol TMC3 TMC4 TMC5 TMC6 TMC7 TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 TMIC6 TMIC7 TOC0 TOC1 TXS0 TXS1 UAR USR WDCS WDTIC WDTM WTNCS WTNHC WTNIC WTNIIC WTNM 8-bit timer mode control register 3 8-bit timer mode control register 4 8-bit timer mode control register 5 8-bit timer mode control register 6 8-bit timer mode control register 7 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register 16-bit timer output control register 0 16-bit timer output control register 1 Transmit shift register 0 Transmit shift register 1 IEBus unit address register IEBus unit status register Watchdog timer clock selection register Interrupt control register Watchdog timer mode register Watch timer clock selection register Watch timer high-speed clock selection register Interrupt control register Interrupt control register Watch timer mode control register Name Unit Timer Timer Timer Timer Timer INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC RPU RPU UART UART IEBus IEBus WDT INTC WDT WT WT INTC INTC WT Page 240 240 240 240 240 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 162 to 164 208 208 400 400 564 572 263 162 to 164 166, 264 257 256 162 to 164 162 to 164 255
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APPENDIX C
INSTRUCTION SET LIST
* How to Read Instruction Set List
This column shows instruction groups. Instructions are divided into each instruction group and described.
This column shows instruction mnemonics.
This column shows instruction operands (refer to Table C-1).
This column shows instruction codes (opcode) in binary format. 32-bit instructions are displayed in 2 lines (refer to Table C-2).
This column shows instruction operations (refer to Table C-3).
This column shows flag statuses (refer to Table C-4).
Instruction Group
Mnemonic
Operand
Opcode
Operation
Flag
CY
OV
S
Z
SAT
Table C-1. Symbols in Operand Description
Symbol reg1 reg2 ep bit#3 immx dispx regID vector cccc Description General-purpose register (r0 to r31): Used as source register General-purpose register (r0 to r31): Mainly used as destination register Element pointer (r30) 3-bit data for bit number specification x-bit immediate data x-bit displacement System register number 5-bit data that specifies trap vector number (00H to 1FH) 4-bit data that indicates condition code
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INSTRUCTION SET LIST
Table C-2. Symbols Used for Opcode
Symbol R r d i cccc bbb Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data 4-bit data that indicates condition code 3-bit data that specifies bit number
Table C-3. Symbols Used for Operation Description
Symbol GR[ ] SR[ ] zero-extend (n) sign-extend (n) load-memory (a,b) store-memory (a,b,c) load-memory-bit (a,b) store-memory-bit (a,b,c) saturated (n) Assignment Genera-purpose register System register Zero-extends n to word length. Sign-extends n to word length. Reads data of size b from address a. Writes data b of size c to address a. Reads bit b from address a. Writes c to bit b of address a Performs saturated processing of n. (n is 2's complements). Result of calculation of n: If n is n 7FFFFFFFH as result of calculation, 7FFFFFFFH. If n is n 80000000H as result of calculation, 80000000H. Reflects result to a flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Add Subtract Bit concatenation Multiply Divide Logical product Logical sum Exclusive logical sum Logical negate Logical left shift Logical right shift Arithmetic right shift Description
result Byte Halfword Word + - || x / AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by
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INSTRUCTION SET LIST
Table C-4. Symbols Used for Flag Operation
Symbol (blank) 0 x R Not affected Cleared to 0 Set of cleared according to result Previously saved value is restored Description
Table C-5. Condition Codes
Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 Conditional Expression OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) No carry No lower (Greater than or equal) Zero Equal Not zero Not equal Not higher (Less than or equal) Higher (Greater than) Negative Positive - SAT = 1 (S XOR OV) = 1 (S XOR OV) = 0 ( (S XOR OV) OR Z) = 1 ( (S XOR OV) OR Z) = 0 Always (unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Description
NC/NL
1001
CY = 0
Z/E
0010
Z=1
NZ/NE
1010
Z=0
NH H N P T SA LT GE LE GT
0011 1011 0100 1100 0101 1101 0110 1110 0111 1111
(CY OR Z) = 1 (CY OR Z) = 0 S=1 S=0
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INSTRUCTION SET LIST
Instruction Set List (1/4)
Instruction Group Load/store Mnemonic Operand Opcode Operation Flag CY OV S SLD.B disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) GR [reg2] sign-extend (Load-memory (adr, Byte)) rrrrr1000ddddddd adr ep + zero-extend (disp8) (Note 1) GR [reg2] sign-extend (Load-memory (adr, Halfword)) rrrrr1010dddddd0 adr ep + zero-extend (disp8) (Note 2) GR [reg2] Load-memory (adr, Word) adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Byte)) Z SAT
SLD.H
disp8 [ep], reg2
SLD.W
disp8 [ep], reg2
LD.B
disp16 rrrrr111000RRRRR [reg1], reg2 dddddddddddddddd
LD.H
adr GR [reg1] + sign-extend (disp16) disp16 rrrrr111001RRRRR [reg1], reg2 ddddddddddddddd0 GR [reg2] sign-extend (Load-memory (Note 3) (adr, Halfword)) adr GR [reg1] + sign-extend (disp16) disp16 rrrrr111001RRRRR [reg1], reg2 ddddddddddddddd1 GR [reg2] Load-memory (adr, Word)) (Note 3) reg2, disp7 [ep] reg2, disp8 [ep] reg2, disp8 [ep] reg2, disp16 [reg1] reg2, disp16 [reg1] reg2, disp16 [reg1] reg1, reg2 rrrrr0111ddddddd adr ep + zero-extend (disp7) Store-memory (adr, GR [reg2], Byte) rrrrr1001ddddddd adr ep + zero-extend (disp8) (Note 1) Store-memory (adr, GR [reg2], Halfword) rrrrr1010dddddd1 adr ep + zero-extend (disp8) (Note 2) Store-memory (adr, GR [reg2], Word) rrrrr111010RRRRR dddddddddddddddd adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Byte)
LD.W
SST.B
SST.H
SST.W
ST.B
ST.H
adr GR [reg1] + sign-extend (disp16) rrrrr111011RRRRR ddddddddddddddd0 Store-memory (adr, GR [reg2], Halfword) (Note 3) adr GR [reg1] + sign-extend (disp16) rrrrr111011RRRRR ddddddddddddddd1 Store-memory (adr, GR [reg2], Word) (Note 3) rrrrr000000RRRRR GR [reg2] GR [reg1] GR [reg2] sign-extend (imm5) GR [reg2] GR [reg1] + (imm16 || 016) GR [reg2] GR [reg1] + sign-extend (imm16)
ST.W
Arithmetic operation
MOV MOV MOVHI
imm5, reg2 rrrrr010000iiiii imm16, reg1, reg2 imm16, reg1, reg2 rrrrr110010RRRRR iiiiiiiiiiiiiiii rrrrr110001RRRRR iiiiiiiiiiiiiiii
MOVEA
Notes 1. 2. 3.
ddddddd is the higher 7 bits of disp8. dddddd is the higher 6 bits of disp8. ddddddddddddddd is the higher 15 bits of disp16.
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INSTRUCTION SET LIST
Instruction Set List (2/4)
Instruction Group Arithmetic operation Mnemonic Operand Opcode Operation Flag CY OV S ADD ADD reg1, reg2 rrrrr001110RRRRR GR [reg2] GR [reg2] + GR [reg1] GR [reg2] GR [reg2] + sign-extend (imm5) GR [reg2] GR [reg1] + sign-extend (imm16) GR [reg2] GR [reg2] - GR [reg1] GR [reg2] GR [reg1] - GR [reg2] GR [reg2] GR [reg2]
Note
Z SAT x x x x x
x x x x x
Note
x x x x x
x x x x x
imm5, reg2 rrrrr010010iiiii
ADDI
imm16, reg1, reg2 reg1, reg2 reg1, reg2 reg1,reg2
rrrrr110000RRRRR iiiiiiiiiiiiiiii rrrrr001101RRRRR rrrrr001100RRRRR rrrrr000111RRRRR
SUB SUBR MULH
x GR [reg1]
(Signed multiplication) MULH imm5, reg2 rrrrr010111iiiii GR [reg2] GR [reg2] (imm5) MULHI imm16, reg1, reg2 reg1, reg2 rrrrr110111RRRRR iiiiiiiiiiiiiiii rrrrr000010RRRRR
Note
x sign-extend x imm16
Note
(Signed multiplication)
Note
GR [reg2] GR [reg1]
(Signed multiplication) GR [reg2] GR [reg2] / GR [reg2] result GR [reg2] - GR [reg1] result GR [reg2] - sign-extend (imm5) if conditions are satisfied then GR [reg2] 00000001H else GR [reg2] 00000000H GR [reg2] saturated (GR [reg2] + GR [reg1]) GR [reg2] saturated (GR [reg2] + signextend (imm5)) GR [reg2] saturated (GR [reg2] - GR [reg1]) GR [reg2] saturated (GR [reg1] - signextend (imm16)) GR [reg2] saturated (GR [reg1] - GR [reg2]) result GR [reg2] AND GR [reg1] GR [reg2] GR [reg2] OR GR [reg1] GR [reg2] GR [reg1] OR zero-extend (imm16) GR [reg2] GR [reg2] AND GR [reg1] GR [reg2] GR [reg1] AND zero-extend (imm16) x x x x x x x x x x 0 0 0 x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x
DIVH
(Signed division) CMP CMP SETF reg1, reg2 rrrrr001111RRRRR
imm5, reg2 rrrrr010011iiiii cccc, reg2 rrrrr1111110cccc 0000000000000000
Saturated operation
SATADD
reg1, reg2
rrrrr000110RRRRR
SATADD
imm5, reg2 rrrrr010001iiiii
SATSUB
reg1, reg2
rrrrr000101RRRRR
SATSUBI
imm16, reg1, reg2 reg1, reg2
rrrrr110011RRRRR iiiiiiiiiiiiiiii rrrrr000100RRRRR
SATSUBR
Logic operation
TST OR ORI
reg1, reg2 reg1, reg2 imm16, reg1, reg2 reg1, reg2 imm16, reg1, reg2
rrrrr001011RRRRR rrrrr001000RRRRR rrrrr110100RRRRR iiiiiiiiiiiiiiii rrrrr001010RRRRR rrrrr110110RRRRR iiiiiiiiiiiiiiii
AND ANDI
0 0
Note Only the lower halfword data is valid.
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INSTRUCTION SET LIST
Instruction Set List (3/4)
Instruction Group Logic operation Mnemonic Operand Opcode Operation Flag CY OV S XOR XORI reg1, reg2 imm16, reg1, reg2 reg1, reg2 reg1, reg2 rrrrr001001RRRRR rrrrr110101RRRRR iiiiiiiiiiiiiiii rrrrr000001RRRRR rrrrr111111RRRRR 0000000011000000 GR [reg2] GR [reg2] XOR GR [reg1] GR [reg2] GR [reg1] XOR zero-extend (imm16) GR [reg2] NOT (GR [reg1]) GR [reg2] GR [reg2] logically shift left by GR [reg1]) GR [reg2] GR [reg2] logically shift left by zero-extend (imm5) SHR reg1, reg2 rrrrr1111111cccc 0000000010000000 GR [reg2] GR [reg2] logically shift right by GR [reg1] GR [reg2] GR [reg2] logically shift right by zero-extend (imm5) SAR reg1, reg2 rrrrr111111RRRRR 0000000010100000 GR [reg2] GR [reg2] arithmetically shift right by GR [reg1] GR [reg2] GR [reg2] arithmetically shift right by zero-extend (imm5) x x 0 x x x x x x 0 x x x x x x 0 0 x x x x x Z SAT x x x x x
NOT SHL
0 0
SHL
imm5, reg2 rrrrr010110iiiii
0
SHR
imm5, reg2 rrrrr010100iiiii
0
SAR
imm5, reg2 rrrrr010101iiiii
0
Jump
JMP JR
[reg1] disp22
00000000011RRRRR PC GR [reg1] 0000011110dddddd PC PC + sign-extend (disp22) ddddddddddddddd0 (Note 1) GR [reg2] PC + 4 rrrrr11110dddddd ddddddddddddddd0 PC PC + sign-extend (disp22) (Note 1) ddddd1011dddcccc if conditions are satisfied (Note 2) then PC PC + sign-extend (disp9) 00bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3) Store memory-bit (adr, bit#3, 1) x
JARL
disp22, reg2 disp9
Bcond
Bit manipulate
SET1
bit#3, disp16 [reg1]
CLR1
bit#3, disp16 [reg1]
10bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3)) Store memory-bit (adr, bit#3, 0)
x
NOT1
bit#3, disp16 [reg1]
01bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag)
x
TST1
bit#3, disp16 [reg1]
11bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3))
x
Notes 1. 2.
ddddddddddddddddddddd is the higher 21 bits of dip22. dddddddd is the higher 8 bits of disp9.
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INSTRUCTION SET LIST
Instruction Set List (4/4)
Instruction Group Special Mnemonic Operand Opcode Operation Flag CY OV S LDSR reg2, regID rrrrr111111RRRRR SR [regID] GR 0000000000100000 [reg2] (Note) regID = EIPC, FEPC regID = EIPSW, FEPSW regID = PSW STSR regID, reg2 rrrrr111111RRRRR 0000000001000000 00000111111iiiii 0000000100000000 GR [reg2] SR [regID] EIPC PC + 4 (Restored PC) EIPSW PSW ECR.EICC Interrupt code PSW.EP 1 PSW.ID 1 PC 00000040H (vector = 00H to 0FH) 00000050H (vector = 10H to 1FH) RETI 0000011111100000 0000000101000000 if PSW.EP = 1 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW HALT 0000011111100000 0000000100100000 0000011111100000 0000000101100000 1000011111100000 0000000101100000 0000000000000000 Stops PSW.ID 1 (Maskable interrupt disabled) PSW.ID 0 (Maskable interrupt enabled) Uses 1 clock cycle without doing anything R R R R R x x x x x Z SAT
TRAP
vector
DI
EI
NOP
Note The opcode of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table. Therefore, the meaning of register specification for mnemonic description and opcode is different from that of the other instructions. rrr = regID specification RRRRR = reg2 specification
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APPENDIX D
INDEX
[Number]
16-bit capture/compare register n0 -------------------- 203 16-bit capture/compare register n1 -------------------- 204 16-bit compare register 23 ------------------------------- 250 16-bit compare register 45 ------------------------------- 250 16-bit compare register 67 ------------------------------- 250 16-bit counter 23 ------------------------------------------- 250 16-bit counter 45 ------------------------------------------- 250 16-bit counter 67 ------------------------------------------- 250 16-bit timer --------------------------------------------------- 200 16-bit timer mode control registers 0, 1 -------------- 205 16-bit timer output control registers 0, 1 ------------- 208 16-bit timer registers 0, 1 -------------------------------- 202 3-wire serial I/O --------------------------------------------- 268 3-wire variable-length serial I/O ------------------------ 419 8-bit compare registers 2 to 7 --------------------------- 236 8-bit counters 2 to 7 ---------------------------------------- 236 8-bit timer ----------------------------------------------------- 234 8-bit timer mode control registers 2 to 7 -------------- 240
ANI0 to ANI11 ------------------------------------------------ 86 Arbitration ---------------------------------------------------- 319 ASCK0 --------------------------------------------------------- 82 ASCK1 --------------------------------------------------------- 83 ASIM0, ASIM1 ---------------------------------------------- 402 ASIS0, ASIS1 ----------------------------------------------- 403 ASTB ----------------------------------------------------------- 88 Asynchronous serial interface -------------------------- 399 Asynchronous serial interface mode registers 0, 1 ------------------------------------------------ 402 Asynchronous serial interface status registers 0, 1 ------------------------------------------------ 403 AVDD ------------------------------------------------------------ 90 AVREF ----------------------------------------------------------- 91 AVSS ------------------------------------------------------------- 91
[B]
Baud rate generator control registers 0, 1 ---------- 404 Baud rate generator mode control registers n0, n1 -------------------------------------------- 405 Baud rate generator source clock selection register 4 ----------------------------------------------------- 424 Baud rate generator output clock selection register 4 ----------------------------------------------------- 425 BCC ----------------------------------------------------------- 134 BCR ----------------------------------------------------------- 561 BCU -------------------------------------------------------- 40, 50 BRGC0, BRGC1 ------------------------------------------- 404 BRGCK4 ----------------------------------------------------- 425 BRGCN4 ----------------------------------------------------- 424 BRGMCn0, BRGMCn1 ----------------------------------- 405 Bus control function --------------------------------------- 128 Bus control pin --------------------------------------------- 128 Bus control unit ------------------------------------------40,50 Bus cycle control register -------------------------------- 134 Bus hold function ------------------------------------------ 135 Bus priority -------------------------------------------------- 144 Bus timing --------------------------------------------------- 137 Bus width ---------------------------------------------------- 130 BVDD ------------------------------------------------------------ 91 BVSS ------------------------------------------------------------- 91 Byte access ------------------------------------------------- 130
[A]
A/D conversion result register -------------------------- 433 A/D conversion result register H ----------------------- 433 A/D converter ----------------------------------------------- 431 A/D converter mode register 1 -------------------------- 435 A/D converter mode register 2 -------------------------- 437 A1 to A4 --------------------------------------------------------90 A13 to A15 -----------------------------------------------------84 A16 to A21 -----------------------------------------------------86 A5 to A12 -------------------------------------------------------89 Absolute maximum ratings ------------------------------- 600 AC characteristics ------------------------------------------ 612 Access clock ------------------------------------------------- 129 AD0 to AD7 ----------------------------------------------------85 AD8 to AD15 --------------------------------------------------85 ADCR --------------------------------------------------------- 433 ADCRH ------------------------------------------------------- 433 Address match detection method ---------------------- 318 Address space ---------------------------------------------- 103 ADIC --------------------------------------------------162 to 164 ADM1 --------------------------------------------------------- 435 ADM2 --------------------------------------------------------- 437 ADS ------------------------------------------------------------ 437 ADTRG ---------------------------------------------------------81 Analog input channel specification register --------- 437
[C]
Capture/compare control registers 0, 1 -------------- 207
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INDEX
CCR ----------------------------------------------------------- 582 CDR ----------------------------------------------------------- 565 CG ---------------------------------------------------------- 40, 51 Channel control block ------------------------------------- 452 CLKOUT ------------------------------------------------------- 90 Clock generation function ------------------------------- 182 Clock generator (CG) ---------------------------------- 40, 51 Clock output function ------------------------------------- 183 Command register ----------------------------------------- 127 Communication command ------------------------------ 539 Communication mode ------------------------------------- 525 Communication reservation ----------------------------- 321 Convertion time --------------------------------------------- 450 CORAD0 to CORAD3 ------------------------------------ 521 CORCN ------------------------------------------------------ 519 Correction address registers 0 to 3 ------------------- 521 Correction control register ------------------------------- 519 Correction request register ------------------------------ 520 CORRQ ------------------------------------------------------ 520 CPU -------------------------------------------------------- 40, 50 CPU address space -------------------------------------- 103 CPU register set --------------------------------------------- 97 CR20 to CR70 ---------------------------------------------- 236 CR23, CR45, CR67 --------------------------------------- 250 CRC0, CRC1 ----------------------------------------------- 207 CRn0 ---------------------------------------------------------- 203 CRn1 ---------------------------------------------------------- 204 CSI0 to CSI3 ------------------------------------------------ 268 CSI4 ----------------------------------------------------------- 419 CSIB4 --------------------------------------------------------- 423 CSIC0 to CSIC4 ---------------------------------- 162 to 164 CSIM0 to CSIM3 ------------------------------------------- 270 CSIM4 -------------------------------------------------------- 422 CSIS0 to CSIS3 -------------------------------------------- 270
DMA transfer request control block --------------------452 DMAIC0 to DMAIC5 ----------------------------- 162 to 164 DMA start factor expansion register -------------------459 DMAS ---------------------------------------------------------459 DR --------------------------------------------------------------571 DRA0 to DRA5 ----------------------------------------------454 DSTB ----------------------------------------------------------- 87 DWC -----------------------------------------------------------132
[E]
ECR ------------------------------------------------------------- 99 EGN0 --------------------------------------------------- 154, 477 EGP0 --------------------------------------------------- 154, 477 EIPC ------------------------------------------------------------ 99 EIPSW --------------------------------------------------------- 99 EP flag ---------------------------------------------------------171 Error detection ----------------------------------------------318 EVDD ------------------------------------------------------------ 91 EVSS ------------------------------------------------------------ 91 Exception trap -----------------------------------------------171 Extension code ---------------------------------------------318 External expansion mode --------------------------------114 External memory -------------------------------------------113 External wait function -------------------------------------133
[F]
Falling edge specification register 0 ----------- 154, 477 FEPC ----------------------------------------------------------- 99 FEPSW -------------------------------------------------------- 99 Flash memory -----------------------------------------------523 Flash memory control -------------------------------------537 Flash memory programming mode ------------- 102, 538 Full-scale error-----------------------------------------------449
[G] [D]
Data wait control register -------------------------------- 132 DBC0 to DBC5 --------------------------------------------- 459 DC characteristics------------------------------------------ 606 DCHC0 to DCHC5 ---------------------------------------- 460 Differential linearity error --------------------------------- 449 DIOA0 to DIOA5 ------------------------------------------- 453 DLR ----------------------------------------------------------- 569 DMA function ---------------------------------------------- 451 DMA byte count registers 0 to 5 ----------------------- 459 DMA channel control registers 0 to 5 ---------------- 460 DMA internal RAM address registers 0 to 5 -------- 454 DMA peripheral I/O address registers 0 to 5 ------- 453 General-purpose register --------------------------------- 98
[H]
Halfword access --------------------------------------------130 HALT mode ------------------------------------------- 188, 189 Handling of unused pins ---------------------------------- 69 Hardware start ----------------------------------------------431 HLDAK --------------------------------------------------------- 88 HLDRQ -------------------------------------------------------- 88 How to read A/D converter characteristics table----447
[I]
I C bus --------------------------------------------------------275
2
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APPENDIX D
INDEX
I C bus mode ------------------------------------------------ 275 I C interrupt request --------------------------------------- 299 IC -----------------------------------------------------------------91 ID flag ---------------------------------------------------------- 165 IDLE mode -------------------------------------------- 188, 192 Idle state insertion function ------------------------------ 134 IEBIC1 -----------------------------------------------162 to 164 IEBIC2 -----------------------------------------------162 to 164 IEBus clock selection register -------------------------- 582 IEBus communication count register ----------------- 582 IEBus control data register ------------------------------ 565 IEBus control register ------------------------------------- 561 IEBus controller -------------------------------------------- 541 IEBus data register ---------------------------------------- 571 IEBus high-speed clock selection register ----------- 583 IEBus interrupt status register -------------------------- 575 IEBus partner address register ------------------------- 565 IEBus slave address register -------------------- 433, 564 IEBus slave status register ------------------------------ 580 IEBus success count register --------------------------- 581 IEBus telegraph length register ------------------------ 569 IEBus unit address register ----------------------------- 564 IEBus unit status register -------------------------------- 572 IECLK --------------------------------------------------------- 582 IEHCLK-------------------------------------------------------- 583 IERX -------------------------------------------------------------89 IETX -------------------------------------------------------------89 IIC clock expansion registers 0, 1 -------------- 289, 350 IIC clock selection registers 0, 1 ---------------- 288, 349 IIC control registers 0, 1 ---------------------------------- 339 IIC flag registers 0, 1--------------------------------------- 347 IIC function expansion registers 0, 1 ----------- 289, 350 IIC shift registers 0, 1 ------------------------------------- 278 IIC status registers 0, 1 ---------------------------- 285, 344 IIC0, IIC1 --------------------------------------- 278, 291, 351 IICC0, IICC1 ------------------------------------------ 280, 339 IICCE0, IICCE1 -------------------------------------- 289, 350 IICCL0, IICCL1 -------------------------------------- 288, 349 IICF0, IICF1 -------------------------------------------------- 347 IICIC1 ------------------------------------------------162 to 164 IICS0, IICS1 ------------------------------------------ 285, 344 IICX0, IICX1 ------------------------------------------ 289, 350 Illegal opcode ----------------------------------------------- 171 Image --------------------------------------------------------- 104 In-service priority register -------------------------------- 165 INTC ------------------------------------------------------- 40, 50 Integral linearity error -------------------------------------- 450 Internal RAM area ----------------------------------------- 110
2
2
Internal ROM area ----------------------------------------- 107 Interrupt control register ------------------------ 162 to 164 Interrupt controller -------------------------------------- 40, 50 Interrupt request signal generator --------------------- 279 Interrupt source register ----------------------------------- 99 Interrupt status saving register --------------------------- 99 Interrupt/exception processing function ------------- 146 Interval timer mode ---------------------------------------- 261 INTP0 to INTP6 ---------------------------------------------- 81 ISPR ---------------------------------------------------------- 165 ISR ------------------------------------------------------------ 575
[K]
Key interrupt function ------------------------------------- 180 Key return mode register -------------------------------- 180 KR0 to KR7 --------------------------------------------------- 89 KRIC ------------------------------------------------- 162 to 164 KRM ----------------------------------------------------------- 180
[L]
LBEN ----------------------------------------------------------- 87 Low power consumption mode ------------------------ 443
[M]
Main clock oscillator -------------------------------------- 182 MAM ---------------------------------------------------------- 116 Maskable interrupt ---------------------------------------- 155 Memory address output mode register -------------- 116 Memory block function ----------------------------------- 131 Memory boundary operation condition --------------- 145 Memory expansion mode register --------------------- 115 Memory map ------------------------------------------------ 106 MM ------------------------------------------------------------ 115 Multiple interrupt ------------------------------------------- 174
[N]
NCC ----------------------------------------------------------- 167 NMI -------------------------------------------------------------- 81 NMI status saving register -------------------------------- 99 Noise elimination control register --------------------- 167 Non-maskable interrupt ---------------------------------- 149 Normal operation mode ---------------------------------- 102
[O]
Off-board programming ---------------------------------- 525 On-board programming ---------------------------------- 525 On-chip peripheral I/O area ----------------------------- 112 Operation mode -------------------------------------------- 102
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INDEX
Oscillation stabilization time ---------------------------- 196 Oscillation stabilization time selection register ----------------------------- 187, 262, 267 OSTS -------------------------------------------- 187, 262, 267 Overall error ------------------------------------------------- 447
PM3 ------------------------------------------------------------489 PM4 ------------------------------------------------------------493 PM5 ------------------------------------------------------------493 PM6 ------------------------------------------------------------496 PM9 ------------------------------------------------------------501 Port -------------------------------------------------------- 42, 52 Port 0 ----------------------------------------------------------474 Port 0 mode register ---------------------------------------476 Port 1 ----------------------------------------------------------479 Port 1 function register -----------------------------------481 Port 1 mode register ---------------------------------------480 Port 10 --------------------------------------------------------503 Port 10 function register ----------------------------------505 Port 10 mode register -------------------------------------504 Port 11 --------------------------------------------------------507 Port 11 mode register -------------------------------------508 Port 2 ----------------------------------------------------------483 Port 2 function register -----------------------------------485 Port 2 mode register ---------------------------------------484 Port 3 ----------------------------------------------------------488 Port 3 function register -----------------------------------490 Port 3 mode register ---------------------------------------489 Port 4 ----------------------------------------------------------492 Port 4 mode register ---------------------------------------493 Port 5 ----------------------------------------------------------492 Port 5 mode register ---------------------------------------493 Port 6 ----------------------------------------------------------495 Port 6 mode register ---------------------------------------496 Port 7 ----------------------------------------------------------498 Port 8 ----------------------------------------------------------498 Port 9 ----------------------------------------------------------500 Port 9 mode register ---------------------------------------501 Port alternate function control register ---------------509 Power save control register -----------------------------186 Power save function ---------------------------------------188 PRCMD -------------------------------------------------------127 Prescaler mode register 0n ------------------------------209 Prescaler mode register 1n ------------------------------210 Priority control -----------------------------------------------174 PRM0n --------------------------------------------------------209 PRM1n --------------------------------------------------------210 Processor clock control register ------------------------184 Program counter -------------------------------------------- 98 Program register set ---------------------------------------- 98 Program status word --------------------------------------100 Programmable wait function -----------------------------132 Programming environment ------------------------------530 Programming method -------------------------------------537
[P]
P0 -------------------------------------------------------------- 474 P00 to P07 ---------------------------------------------------- 81 P1 -------------------------------------------------------------- 479 P10 ------------------------------------------------------------ 503 P10 to P15 ---------------------------------------------------- 82 P100 to P107 ------------------------------------------------- 89 P11 ------------------------------------------------------------ 507 P110 to P113 ------------------------------------------------- 90 P2 -------------------------------------------------------------- 483 P20 to P27 ---------------------------------------------------- 83 P3 -------------------------------------------------------------- 488 P30 to P37 ---------------------------------------------------- 84 P4 -------------------------------------------------------------- 492 P40 to P47 ---------------------------------------------------- 85 P5 -------------------------------------------------------------- 492 P50 to P57 ---------------------------------------------------- 85 P6 -------------------------------------------------------------- 495 P60 to P65 ---------------------------------------------------- 86 P7 -------------------------------------------------------------- 498 P70 to P77 ---------------------------------------------------- 86 P8 -------------------------------------------------------------- 498 P80 to P83 ---------------------------------------------------- 86 P9 -------------------------------------------------------------- 500 P90 to P96 ---------------------------------------------------- 87 PAC ----------------------------------------------------------- 509 PAR ----------------------------------------------------------- 565 PCC ----------------------------------------------------------- 184 Peripheral I/O registers ---------------------------------- 119 PF1 ------------------------------------------------------------ 481 PF10 ---------------------------------------------------------- 505 PF2 ------------------------------------------------------------ 485 PF3 ------------------------------------------------------------ 490 PIC0 to PIC6 --------------------------------------- 162 to 164 Pin function ---------------------------------------------------- 73 Pin I/O buffer power supply ------------------------------- 92 Pin I/O circuit type ------------------------------------------- 92 PM0 ----------------------------------------------------------- 476 PM1 ----------------------------------------------------------- 480 PM10 --------------------------------------------------------- 504 PM11 --------------------------------------------------------- 508 PM2 ----------------------------------------------------------- 484
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PSC ------------------------------------------------------------ 186 PSW ----------------------------------------------------------- 100 PU0 ------------------------------------------------------------ 476 PU1 ------------------------------------------------------------ 480 PU10 ---------------------------------------------------------- 505 PU11 ---------------------------------------------------------- 509 PU2 ------------------------------------------------------------ 485 PU3 ------------------------------------------------------------ 489 Pull-up resistor option register 0 ----------------------- 476 Pull-up resistor option register 1 ----------------------- 480 Pull-up resistor option register 10 --------------------- 505 Pull-up resistor option register 11 --------------------- 509 Pull-up resistor option register 2 ----------------------- 485 Pull-up resistor option register 3 ----------------------- 489
RXB0, RXB1 ------------------------------------------------ 400 RXD0 ----------------------------------------------------------- 82 RXD1 ----------------------------------------------------------- 83
[S]
Sampling time ----------------------------------------------- 450 SAR -----------------------------------------------------433, 564 SCK0, SCK1 -------------------------------------------------- 82 SCK2, SCK3 -------------------------------------------------- 83 SCK4 ----------------------------------------------------------- 84 SCL0 ------------------------------------------------------------ 82 SCL1 ------------------------------------------------------------ 83 SCR ----------------------------------------------------------- 581 SDA0 ----------------------------------------------------------- 82 SDA1 ----------------------------------------------------------- 83 Serial clock counter --------------------------------------- 278 Serial clock selection registers 0 to 3 ---------------- 270 Serial I/O shift registers 0 to 3 -------------------------- 269 Serial interface function ---------------------------------- 268 Serial operation mode registers 0 to 3 --------------- 270 SERIC0, SERIC1 --------------------------------- 162 to 164 SI0, SI1 --------------------------------------------------------- 82 SI2, SI3 --------------------------------------------------------- 83 SI4 --------------------------------------------------------------- 84 Single-chip mode ------------------------------------------ 102 SIO0 to SIO3 ----------------------------------------------- 269 SIO4 ---------------------------------------------------------- 420 Slave address registers 0, 1 --------------- 278, 291, 352 SO latch ------------------------------------------------------ 278 SO0, SO1 ------------------------------------------------------ 82 SO2, SO3 ------------------------------------------------------ 83 SO4 ------------------------------------------------------------- 84 Software exception ---------------------------------------- 169 Software start ----------------------------------------------- 431 Software STOP mode ------------------------------188, 194 Specific register -------------------------------------------- 126 SSR ----------------------------------------------------------- 580 Standby function ------------------------------------------- 418 Start condition ---------------------------------------------- 293 STIC0, STIC1 -------------------------------------- 162 to 164 Stop condition ---------------------------------------------- 296 Subclock oscillator ---------------------------------------- 182 Successive approximation register -------------433, 564 SVA0, SVA1 ----------------------------------- 278, 291, 352 SYC ----------------------------------------------------------- 129 SYS ----------------------------------------------------------- 127 System control register ---------------------------------- 129 System register set ----------------------------------------- 99
[Q]
Quantization error ------------------------------------------ 448
[R]
R/W --------------------------------------------------------------87 RAM ------------------------------------------------------- 40, 50 RD ---------------------------------------------------------------88 Real-time output buffer register H --------------------- 468 Real-time output buffer register L ---------------------- 468 Real-time output function -------------------------------- 466 Real-time output port control register ----------------- 470 Real-time output port mode register ------------------ 469 Receive buffer registers 0, 1 ---------------------------- 400 Receive shift registers 0, 1 ------------------------------ 400 Recommended soldering conditions------------------- 637 Recommended use of address space ---------------- 117 REGC -----------------------------------------------------------90 Regulator ----------------------------------------------------- 517 RESET ----------------------------------------------------------90 Reset function ---------------------------------------------- 516 Resolution ---------------------------------------------------- 447 Rising edge specification register 0 ------------ 154, 477 ROM ------------------------------------------------------- 40, 50 ROM correction function --------------------------------- 518 RTBH ---------------------------------------------------------- 468 RTBL ---------------------------------------------------------- 468 RTO ----------------------------------------------------------- 466 RTP -------------------------------------------------------- 41, 52 RTP0 to RTP7 ------------------------------------------------89 RTPC ---------------------------------------------------------- 470 RTPM --------------------------------------------------------- 469 RTPTRG -------------------------------------------------------81 RX0, RX1 ---------------------------------------------------- 400
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INDEX
System status register ----------------------------------- 127
VDD -------------------------------------------------------------- 91 VPP -------------------------------------------------------------- 91 VSS -------------------------------------------------------------- 91
[T]
TCL20 to TCL70 ------------------------------------------- 237 TCL21 to TCL71 ------------------------------------------- 237 TI00, TI01, TI10, TI11, TI4, TI5 -------------------------- 84 TI2, TI3 --------------------------------------------------------- 83 Timer clock selection registers 20 to 70 ------------- 237 Timer clock selection registers 21 to 71 ------------- 237 Timer/counter function ----------------------------------- 200 TM0, TM1 ---------------------------------------------------- 202 TM2 to TM7 ------------------------------------------------- 236 TM23, TM45, TM67 --------------------------------------- 250 TMC0, TMC1 ----------------------------------------------- 205 TMC2 to TMC7 --------------------------------------------- 240 TMIC00 ---------------------------------------------- 162 to 164 TMIC01 ---------------------------------------------- 162 to 164 TMIC10 ---------------------------------------------- 162 to 164 TMIC11 ---------------------------------------------- 162 to 164 TMIC2 to TMIC7 ---------------------------------- 162 to 164 TO0, TO1, TO4, TO5 --------------------------------------- 84 TO2, TO3 ------------------------------------------------------ 83 TOC0, TOC1 ------------------------------------------------ 208 Transfer completion interrupt request ---------------- 451 Transmit shift registers 0, 1 ----------------------------- 400 TXD0 ------------------------------------------------------------ 82 TXD1 ------------------------------------------------------------ 83 TXS0, TXS1 ------------------------------------------------- 400
[W]
WAIT ----------------------------------------------------------- 90 Wait function ------------------------------------------------132 Wakeup controller ------------------------------------------278 Wakeup function -------------------------------------------320 Watch timer clock selection register ------------------257 Watch timer function --------------------------------------253 Watch timer high-speed clock selection register ---256 Watch timer mode control register ---------------------255 Watchdog timer clock selection register -------------263 Watchdog timer function ---------------------------------260 Watchdog timer mode ------------------------------------261 Watchdog timer mode register ------------------ 166, 264 WDCS ---------------------------------------------------------263 WDTIC ---------------------------------------------- 162 to 164 WDTM -------------------------------------------------- 166, 264 Word access ------------------------------------------------130 Wrap-around of CPU address space -----------------105 WRH ------------------------------------------------------------ 88 Writing with flash programmer --------------------------525 WRL ------------------------------------------------------------ 88 WTNCS -------------------------------------------------------257 WTNHC--------------------------------------------------------256 WTNIC ---------------------------------------------- 162 to 164 WTNIIC --------------------------------------------- 162 to 164 WTNM ---------------------------------------------------------255
[U]
UAR ----------------------------------------------------------- 564 UART0, UART1 -------------------------------------------- 399 UBEN ----------------------------------------------------------- 87 USR ----------------------------------------------------------- 572
[X]
X1 --------------------------------------------------------------- 90 X2 --------------------------------------------------------------- 90 XT1 ------------------------------------------------------------- 90 XT2 ------------------------------------------------------------- 90
[V]
V850/SB1 ------------------------------------------------- 33, 43 V850/SB2 ------------------------------------------------- 53, 63 Variable-length serial control register 4 -------------- 422 Variable-length serial I/O shift register 4 ------------- 420 Variable-length serial setting register 4 -------------- 423
[Z]
Zero-scale error ---------------------------------------------448
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APPENDIX E
REVISION HISTORY
The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/5)
Edition 4th Major Revisions from Previous Edition Modification of 1.2.3 Ordering information (V850/SB1) Modification of 1.3.3 Ordering information (V850/SB2) Modification of description in 2.3 (5) P40 to P47 (Port 4) Modification of description in 2.3 (6) P50 to P57 (Port 5) Modification of description in 2.3 (7) P60 to P65 (Port 6) Modification of description in 2.3 (9) P90 to P96 (Port 9) Modification of Caution in 2.3 (11) (b) (ii) WAIT (Wait) Addition of 2.3 (14) CLKOUT (Clock Out) Addition of 5.8 (1) Acknowledging interrupt servicing after execution of EI instruction Addition of 6.6 Notes on Power Save Function Modification of Caution in 7.1.3 (2) Capture/compare registers n0 (CR00, CR10) Modification of Caution in 7.1.3 (3) Capture/compare registers n1 (CR01, CR11) Modification of Figure 7-34 Data Hold Timing of Capture Register Addition of 7.2.7 (6) (c) One-shot pulse output function Modification of Figure 11-2 A/D Converter Mode Register 1 (ADM1) Addition of description in 11.5 Low Power Consumption Mode Addition of Caution in CHAPTER 18 FLASH MEMORY Addition of Table 19-5 Acknowledge Signal Output Condition of Control Field Addition of description 19.1.8 Bit format Modification of Caution in 19.3.2 (1) (a) Communication enable flag (ENIEBUS) Addition of Note in Figure 19-18 Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5)) Addition of Remark in 19.3.2 (6) IEBus telegraph length register (DLR) Addition of Remark in 19.3.2 (7) IEBus data register (DR) Addition of description in 19.3.2 (7) (a) When transmission unit Modification of description in 19.3.2 (8) (a) Slave request flag (SLVRQ) Addition of Caution in 19.3.2 (8) (b) Arbitration result flag (ARBIT) Addition of description for Caution in 19.3.2 (8) (e) Lock status flag (LOCK) Addition of Table 19-8 Reset Condition of Each Flag of ISR Register Addition of 19.4.3 Communication error source processing list Modification of Figure 19-34 Master Transmission (Interval of Interrupt Occurrence) Modification of Figure 19-35 Master Reception (Interval of Interrupt Occurrence) Modification of Figure 19-36 Slave Transmission (Interval of Interrupt Occurrence) Modification of Figure 19-37 Slave Reception (Interval of Interrupt Occurrence) CHAPTER 11 A/D CONVERTER CHAPTER 18 FLASH MEMORY CHAPTER 19 IEBus CONTROLLER (V850/SB2) CHAPTER 5 INTERRUPT/ EXCEPTION PROCESSING FUNCTION CHAPTER 6 CLOCK GENERATION FUNCTION CHAPTER 7 TIMER/COUNTER FUNCTION Applied to: CHAPTER 1 INTRODUCTION CHAPTER 2 PIN FUNCTIONS
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REVISION HISTORY
(2/5)
Edition 6th Major Revisions from Previous Edition * Addition of the following products. PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY, 703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY, 70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY, 70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY * Deletion of the following products. PD703030A, 703030AY, 703036A, 703036AY Addition of description on minimum instruction execution time in 1.5.1 Addition of description on instruction set in 1.5.1 Addition of description in Table 2-1 Pin I/O Buffer Power Supplies Applied to: Throughout
CHAPTER 1 INTRODUCTION
CHAPTER 2 PIN Modification of description and addition of Notes in Table 2-3 Operating States of Pins FUNCTIONS in Each Operating Mode Addition of description in 2.3 (9) (b) (i) LBEN Modification of P23 I/O circuit type and description on P33 in 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Addition of description on minimum instruction execution time in 3.1 CHAPTER 3 CPU Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW) FUNCTIONS Addition of 3.4.5 (2) (a) V850/SB1 (uPD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) Modification of Note and addition of registers in 3.4.8 Peripheral I/O registers Addition of description in 3.4.9 Specific registers Modification of [Description example] in 3.4.9 Specific registers Modification of Caution 2 in 3.4.9 Specific registers Addition of Remarks in 3.4.9 (2) (b) Reset conditions (PRERR = 1) Addition of Note and Caution in 4.2.2 (1) System control register (SYC) CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 5 INTERRUPT/ EXCEPTION PROCESSING FUNCTION
Addition of Remark in 5.3.3 Priorities of maskable interrupts Addition of Caution 2 in 5.3.4 Interrupt control register (xxICn) Addition of Caution in 5.3.5 In-service priority register (ISPR) Addition of Remark in 5.3.6 ID flag Addition of Remark in 5.6.2 (2) To generate exception in service program Addition of 5.8.1 Interrupt request valid timing after EI instruction Addition of 5.9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer Addition of description in Cautions in 6.3.1 (1) Processor clock control register (PCC) Modification of description in 6.3.1 (1) (b) Example of subclock operation main clock operation setup Modification of description in 6.3.1 (2) Power save control register (PSC) Addition and deletion of description in Table 6-1 Operating Statuses in HALT Mode Modification of description in Table 6-2 Operating Statuses in IDLE Mode Addition of description in 6.4.4 (1) Settings and operating states
CHAPTER 6 CLOCK GENERATION FUNCTION
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APPENDIX E
REVISION HISTORY
(3/5)
Edition 6th Major Revisions from Previous Edition Modification of description in Table 6-3 Operating Statuses in Software STOP Mode Addition of 6.6 (1) While an instruction is being executed on internal ROM Addition of 6.6 (2) While an instruction is being executed on external ROM Addition of description in Caution in 7.1.4 (1) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Addition of description in Caution in 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0, CRC1) Modification of description in Figure 7-5 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Addition of Figure 7-6 Configuration of PPG Output Addition of Figure 7-7 PPG Output Operation Timing Modification of description in Figure 7-8 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-11 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-14 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Figure 7-17 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) Modification of description in Figure 7-18 (a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1) Modification of description in Caution in 7.2.6 (2) One-shot pulse output with external trigger Modification of description in 7.2.7 (6) (a) One-shot pulse output by software Modification of description in 7.2.7 (6) (b) One-shot pulse output with external trigger Addition of 7.3.1 Outline Change of Figure 7-32 Timing of Interval Timer Operation (3/3) Addition of description to Remarks in Figure 7-34 Square Wave Output Operation Timing Addition of description to Remarks in Figure 7-35 Timing of PWM Output Addition of registers and Caution in Figure 8-1 Block Diagram of Watch Timer Addition of registers and Note in Table 8-2 Configuration of Watch Timer Addition of description and Caution in 8.3 Watch Timer Control Register Addition of 8.3 (2) Watch timer high-speed clock selection register (WTNHC) Addition of description in 8.3 (3) Watch timer clock selection register (WTNCS) Addition of Caution in 9.3 (2) Watchdog timer clock selection register (WDCS) CHAPTER 9 WATCHDOG TIMER CHAPTER 10 SERIAL INTERFACE FUNCTION CHAPTER 8 WATCH TIMER CHAPTER 7 TIMER/COUNTER FUNCTION Applied to: CHAPTER 6 CLOCK GENERATION FUNCTION
Addition of description in 10.2 (2) 3-wire serial I/O mode (fixed to MSB first) Modification of Caution in 10.3.2 (1) IIC control registers 0, 1 (IICC0, IICC1) Addition of Caution in 10.3.2 (3) IIC clock selection registers 0, 1 (IICCL0, IICCL1) Addition of 10.4 I2C Bus (B and H Versions)
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REVISION HISTORY
(4/5)
Edition 6th Major Revisions from Previous Edition Addition of description to Cautions in 10.5.2 (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) Addition to Cautions in 10.5.2 (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) Addition of description to Cautions in Figure 10-45 ASIMn Setting (Operation Stop Mode) Addition of description to Cautions in Figure 10-46 ASIMn Setting (Asynchronous Serial Interface Mode) Addition of description to Cautions in Figure 10-49 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) Addition of Caution in 11.3 (2) Analog input channel specification register (ADS) Addition of 11.7 How to Read A/D Converter Characteristics Table Addition of 12.3 Configuration Addition of 12.4 (2) (a) V850/SB1 (PD703031B, 703031BY), V850/SB2 (PD703034B, 703034BY) Addition of Caution in 12.4 (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) Addition of 12.5 Operation Addition of 12.6 Cautions Addition of 13.2 Features Addition of 13.3 (2) Output latch Addition of description in 13.5 Usage Addition of 13.7 (3) Addition of description in Table 14-1 Pin I/O Buffer Power Supplies Addition of Caution in 14.2.8 (1) Function of P9 pins Addition of Caution in 14.2.9 (1) Function of P10 pins Addition of description in Table 14-12 Setting When Port Pin is Used as Alternate Function Addition of 14.4 Port Function Operation Addition of description in 16.1 Outline Addition of description in Figure 16-1 Regulator Addition of 18.1.1 (2) V850/SB1 (PD70F3030B, 70F3030BY), V850/SB2 (uPD70F3036H, 70F3036HY) Addition of Figure 18-1 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU) Addition of Table 18-1 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GC-8EU) Addition of Figure 18-2 Wiring Example of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) Addition of Figure 18-2 Table for Wiring of V850/SB1 and V850/SB2 Flash Writing Adapter (FA-100GF-3BA) CHAPTER 16 REGULATOR CHAPTER 18 FLASH MEMORY CHAPTER 14 PORT FUNCTION CHAPTER 13 REALTIME OUTPUT FUNCTION (RTO) CHAPTER 11 A/D CONVERTER CHAPTER 12 DMA FUNCTIONS Applied to: CHAPTER 10 SERIAL INTERFACE FUNCTION
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APPENDIX E
REVISION HISTORY
(5/5)
Edition 6th Major Revisions from Previous Edition Modification of description in Table 19-5 Acknowledge Signal Output Condition of Control Field Addition of register to Table 19-7 Internal Registers of IEBus Controller Addition of Remark in 19.3.2 (13) IEBus clock selection register (IECLK) Addition of 19.3.2 (14) IEBus high-speed clock selection register (IEHCLK) Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS CHAPTER 20 ELECTRICAL SPECIFICATIONS CHAPTER 21 PACKAGE DRAWINGS CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS APPENDIX A NOTES ON TARGET SYSTEM DESIGN APPENDIX D INDEX APPENDIX E REVISION HISTORY Applied to: CHAPTER 19 IEBus CONTROLLER (V850/SB2)
Addition of CHAPTER 21 PACKAGE DRAWINGS
Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS
Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN
Modification of APPENDIX D INDEX Addition of APPENDIX E REVISION HISTORY
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